/linux-4.4.14/drivers/video/fbdev/via/ |
D | accel.c | 48 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp() 105 writel(tmp, engine + 0x08); in hw_bitblt_1() 114 writel(tmp, engine + 0x0C); in hw_bitblt_1() 122 writel(tmp, engine + 0x10); in hw_bitblt_1() 125 writel(fg_color, engine + 0x18); in hw_bitblt_1() 128 writel(bg_color, engine + 0x1C); in hw_bitblt_1() 138 writel(tmp, engine + 0x30); in hw_bitblt_1() 147 writel(tmp, engine + 0x34); in hw_bitblt_1() 159 writel(tmp, engine + 0x38); in hw_bitblt_1() 172 writel(ge_cmd, engine); in hw_bitblt_1() [all …]
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/linux-4.4.14/drivers/gpu/drm/exynos/ |
D | exynos_dp_reg.c | 34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute() 38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_enable_video_mute() 48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); in exynos_dp_stop_video() 62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); in exynos_dp_lane_swap() 70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); in exynos_dp_init_analog_param() 73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); in exynos_dp_init_analog_param() 76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); in exynos_dp_init_analog_param() 80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); in exynos_dp_init_analog_param() 84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); in exynos_dp_init_analog_param() 90 writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); in exynos_dp_init_interrupt() [all …]
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D | exynos7_drm_decon.c | 116 writel(val, ctx->regs + WINCON(win)); in decon_clear_channels() 188 writel(val, ctx->regs + VIDTCON0); in decon_commit() 191 writel(val, ctx->regs + VIDTCON1); in decon_commit() 200 writel(val, ctx->regs + VIDTCON2); in decon_commit() 203 writel(val, ctx->regs + VIDTCON3); in decon_commit() 209 writel(val, ctx->regs + VIDTCON4); in decon_commit() 211 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); in decon_commit() 218 writel(val, ctx->regs + VIDCON0); in decon_commit() 223 writel(val, ctx->regs + VCLKCON1); in decon_commit() 224 writel(val, ctx->regs + VCLKCON2); in decon_commit() [all …]
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D | exynos5433_drm_decon.c | 78 writel(val, ctx->addr + reg); in decon_set_bits() 96 writel(val, ctx->addr + DECON_VIDINTCON0); in decon_enable_vblank() 110 writel(0, ctx->addr + DECON_VIDINTCON0); in decon_disable_vblank() 120 writel(val, ctx->addr + DECON_TRIGCON); in decon_setup_trigger() 143 writel(val, ctx->addr + DECON_CMU); in decon_commit() 151 writel(val, ctx->addr + DECON_VIDOUTCON0); in decon_commit() 155 writel(val, ctx->addr + DECON_VIDTCON2); in decon_commit() 162 writel(val, ctx->addr + DECON_VIDTCON00); in decon_commit() 166 writel(val, ctx->addr + DECON_VIDTCON01); in decon_commit() 172 writel(val, ctx->addr + DECON_VIDTCON10); in decon_commit() [all …]
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D | exynos_drm_fimd.c | 233 writel(val, ctx->regs + VIDINTCON0); in fimd_enable_vblank() 259 writel(val, ctx->regs + VIDINTCON0); in fimd_disable_vblank() 292 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output() 306 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path() 396 writel(val, timing_base + I80IFCONFAx(0)); in fimd_commit() 399 writel(0, timing_base + I80IFCONFBx(0)); in fimd_commit() 420 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); in fimd_commit() 430 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit() 440 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit() 444 writel(ctx->vidout_con, timing_base + VIDOUT_CON); in fimd_commit() [all …]
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/linux-4.4.14/drivers/video/fbdev/ |
D | wmt_ge_rops.c | 67 writel(p->var.bits_per_pixel == 32 ? 3 : in wmt_ge_fillrect() 69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); in wmt_ge_fillrect() 70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); in wmt_ge_fillrect() 71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); in wmt_ge_fillrect() 72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); in wmt_ge_fillrect() 73 writel(rect->dx, regbase + GE_DESTAREAX_OFF); in wmt_ge_fillrect() 74 writel(rect->dy, regbase + GE_DESTAREAY_OFF); in wmt_ge_fillrect() 75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); in wmt_ge_fillrect() 76 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); in wmt_ge_fillrect() 78 writel(pat, regbase + GE_PAT0C_OFF); in wmt_ge_fillrect() [all …]
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D | w100fb.c | 133 writel(param, remapped_regs + regs); in w100fb_reg_write() 297 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET); in w100_init_graphic_engine() 298 writel(par->xres, remapped_regs + mmDST_PITCH); in w100_init_graphic_engine() 299 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET); in w100_init_graphic_engine() 300 writel(par->xres, remapped_regs + mmSRC_PITCH); in w100_init_graphic_engine() 303 writel(0, remapped_regs + mmSC_TOP_LEFT); in w100_init_graphic_engine() 304 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT); in w100_init_graphic_engine() 305 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT); in w100_init_graphic_engine() 315 writel(dp_cntl.val, remapped_regs + mmDP_CNTL); in w100_init_graphic_engine() 332 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); in w100_init_graphic_engine() [all …]
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D | fb-puv3.c | 164 writel(((u32 *)(info->pseudo_palette))[fg_color], UGE_FCOLOR); in unifb_prim_fillrect() 165 writel(0, UGE_BCOLOR); in unifb_prim_fillrect() 166 writel(src_pitch, UGE_PITCH); in unifb_prim_fillrect() 167 writel(src_offset, UGE_SRCSTART); in unifb_prim_fillrect() 168 writel(dst_offset, UGE_DSTSTART); in unifb_prim_fillrect() 169 writel(awidth, UGE_WIDHEIGHT); in unifb_prim_fillrect() 170 writel(top, UGE_CLIP0); in unifb_prim_fillrect() 171 writel(bottom, UGE_CLIP1); in unifb_prim_fillrect() 172 writel(alpha_r, UGE_ROPALPHA); in unifb_prim_fillrect() 173 writel(src_x0, UGE_SRCXY); in unifb_prim_fillrect() [all …]
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D | wm8505fb.c | 59 writel(0, fbi->regbase + i); in wm8505fb_init_hw() 62 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); in wm8505fb_init_hw() 63 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); in wm8505fb_init_hw() 70 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); in wm8505fb_init_hw() 71 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); in wm8505fb_init_hw() 74 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); in wm8505fb_init_hw() 75 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); in wm8505fb_init_hw() 78 writel(0xf, fbi->regbase + WMT_GOVR_FHI); in wm8505fb_init_hw() 79 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); in wm8505fb_init_hw() 80 writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE); in wm8505fb_init_hw() [all …]
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D | offb.c | 173 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_setcolreg() 175 writel(((red) << 22) | ((green) << 12) | ((blue) << 2), in offb_setcolreg() 177 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_setcolreg() 179 writel(((red) << 22) | ((green) << 12) | ((blue) << 2), in offb_setcolreg() 239 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_blank() 241 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); in offb_blank() 242 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); in offb_blank() 244 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); in offb_blank() 258 writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL); in offb_set_par() 259 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE); in offb_set_par() [all …]
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D | s3c-fb.c | 47 #undef writel 48 #define writel(v, r) do { \ macro 401 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant) in vidosd_set_size() 416 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant)); in vidosd_set_alpha() 432 writel(PRTCON_PROTECT, sfb->regs + PRTCON); in shadow_protect_win() 435 writel(reg | SHADOWCON_WINx_PROTECT(win->index), in shadow_protect_win() 440 writel(0, sfb->regs + PRTCON); in shadow_protect_win() 443 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index), in shadow_protect_win() 474 writel(vidcon0, sfb->regs + VIDCON0); in s3c_fb_enable() 533 writel(0, regs + WINCON(win_no)); in s3c_fb_set_par() [all …]
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D | nuc900fb.c | 60 writel(vbaddr1, regs + REG_LCM_VA_BADDR0); in nuc900fb_set_lcdaddr() 61 writel(vbaddr2, regs + REG_LCM_VA_BADDR1); in nuc900fb_set_lcdaddr() 63 writel(fbi->regs.lcd_va_fbctrl, regs + REG_LCM_VA_FBCTRL); in nuc900fb_set_lcdaddr() 64 writel(fbi->regs.lcd_va_scale, regs + REG_LCM_VA_SCALE); in nuc900fb_set_lcdaddr() 248 writel(fbi->regs.lcd_device_ctrl, regs + REG_LCM_DEV_CTRL); in nuc900fb_activate_var() 249 writel(fbi->regs.lcd_crtc_size, regs + REG_LCM_CRTC_SIZE); in nuc900fb_activate_var() 250 writel(fbi->regs.lcd_crtc_dend, regs + REG_LCM_CRTC_DEND); in nuc900fb_activate_var() 251 writel(fbi->regs.lcd_crtc_hr, regs + REG_LCM_CRTC_HR); in nuc900fb_activate_var() 252 writel(fbi->regs.lcd_crtc_hsync, regs + REG_LCM_CRTC_HSYNC); in nuc900fb_activate_var() 253 writel(fbi->regs.lcd_crtc_vr, regs + REG_LCM_CRTC_VR); in nuc900fb_activate_var() [all …]
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D | pxa168fb.c | 291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider() 326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0() 348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1() 361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start() 386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control() 399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions() 426 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par() 431 writel((var->yres << 16) | var->xres, in pxa168fb_set_par() 451 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); in pxa168fb_set_par() 452 writel((var->yres << 16) | var->xres, in pxa168fb_set_par() [all …]
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/linux-4.4.14/drivers/clocksource/ |
D | timer-u300.c | 193 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_shutdown() 196 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_shutdown() 214 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_set_oneshot() 217 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_set_oneshot() 223 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); in u300_set_oneshot() 225 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, in u300_set_oneshot() 228 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, in u300_set_oneshot() 231 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, in u300_set_oneshot() 242 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, in u300_set_periodic() 245 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, in u300_set_periodic() [all …]
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D | zevio-timer.c | 72 writel(delta, timer->timer1 + IO_CURRENT_VAL); in zevio_timer_set_event() 73 writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH), in zevio_timer_set_event() 85 writel(0, timer->interrupt_regs + IO_INTR_MSK); in zevio_timer_shutdown() 86 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_shutdown() 88 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_shutdown() 98 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK); in zevio_timer_set_oneshot() 99 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_set_oneshot() 112 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK); in zevio_timer_interrupt() 113 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_interrupt() 169 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); in zevio_timer_add() [all …]
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D | nomadik-mtu.c | 95 writel(1 << 1, mtu_base + MTU_IMSC); in nmdk_clkevt_next() 96 writel(evt, mtu_base + MTU_LR(1)); in nmdk_clkevt_next() 98 writel(MTU_CRn_ONESHOT | clk_prescale | in nmdk_clkevt_next() 109 writel(nmdk_cycle, mtu_base + MTU_LR(1)); in nmdk_clkevt_reset() 110 writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); in nmdk_clkevt_reset() 112 writel(MTU_CRn_PERIODIC | clk_prescale | in nmdk_clkevt_reset() 115 writel(1 << 1, mtu_base + MTU_IMSC); in nmdk_clkevt_reset() 124 writel(0, mtu_base + MTU_IMSC); in nmdk_clkevt_shutdown() 126 writel(0, mtu_base + MTU_CR(1)); in nmdk_clkevt_shutdown() 128 writel(0xffffffff, mtu_base + MTU_LR(1)); in nmdk_clkevt_shutdown() [all …]
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D | timer-integrator-ap.c | 50 writel(0xffff, base + TIMER_LOAD); in integrator_clocksource_init() 51 writel(ctrl, base + TIMER_CTRL); in integrator_clocksource_init() 71 writel(1, clkevt_base + TIMER_INTCLR); in integrator_timer_interrupt() 83 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_shutdown() 93 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_set_oneshot() 102 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_set_periodic() 105 writel(timer_reload, clkevt_base + TIMER_LOAD); in clkevt_set_periodic() 107 writel(ctrl, clkevt_base + TIMER_CTRL); in clkevt_set_periodic() 115 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); in clkevt_set_next_event() 116 writel(next, clkevt_base + TIMER_LOAD); in clkevt_set_next_event() [all …]
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D | timer-sp804.c | 77 writel(0, base + TIMER_CTRL); in sp804_timer_disable() 102 writel(0, base + TIMER_CTRL); in __sp804_clocksource_and_sched_clock_init() 103 writel(0xffffffff, base + TIMER_LOAD); in __sp804_clocksource_and_sched_clock_init() 104 writel(0xffffffff, base + TIMER_VALUE); in __sp804_clocksource_and_sched_clock_init() 105 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, in __sp804_clocksource_and_sched_clock_init() 129 writel(1, clkevt_base + TIMER_INTCLR); in sp804_timer_interrupt() 138 writel(0, clkevt_base + TIMER_CTRL); in timer_shutdown() 153 writel(clkevt_reload, clkevt_base + TIMER_LOAD); in sp804_set_periodic() 154 writel(ctrl, clkevt_base + TIMER_CTRL); in sp804_set_periodic() 164 writel(next, clkevt_base + TIMER_LOAD); in sp804_set_next_event() [all …]
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D | moxart_timer.c | 63 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_shutdown() 69 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_set_oneshot() 70 writel(~0, base + TIMER1_BASE + REG_LOAD); in moxart_set_oneshot() 76 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); in moxart_set_periodic() 77 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_set_periodic() 86 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_next_event() 89 writel(u, base + TIMER1_BASE + REG_MATCH1); in moxart_clkevt_next_event() 91 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_next_event() 153 writel(~0, base + TIMER2_BASE + REG_LOAD); in moxart_timer_init() 154 writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); in moxart_timer_init()
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D | vt8500_timer.c | 60 writel(3, regbase + TIMER_CTRL_VAL); in vt8500_timer_read() 83 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); in vt8500_timer_set_next_event() 88 writel(1, regbase + TIMER_IER_VAL); in vt8500_timer_set_next_event() 95 writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); in vt8500_shutdown() 96 writel(0, regbase + TIMER_IER_VAL); in vt8500_shutdown() 112 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_interrupt() 142 writel(1, regbase + TIMER_CTRL_VAL); in vt8500_timer_init() 143 writel(0xf, regbase + TIMER_STATUS_VAL); in vt8500_timer_init() 144 writel(~0, regbase + TIMER_MATCH_VAL); in vt8500_timer_init()
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D | time-armada-370-xp.c | 93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, in local_timer_ctrl_clrset() 112 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); in armada_370_xp_clkevt_next_event() 117 writel(delta, local_base + TIMER0_VAL_OFF); in armada_370_xp_clkevt_next_event() 136 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); in armada_370_xp_clkevt_shutdown() 145 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF); in armada_370_xp_clkevt_set_periodic() 146 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF); in armada_370_xp_clkevt_set_periodic() 164 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); in armada_370_xp_timer_interrupt() 243 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); in armada_370_xp_timer_resume() 244 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); in armada_370_xp_timer_resume() 245 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF); in armada_370_xp_timer_resume() [all …]
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D | mtk_timer.c | 81 writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + in mtk_clkevt_time_stop() 88 writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); in mtk_clkevt_time_setup() 97 writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); in mtk_clkevt_time_start() 109 writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, in mtk_clkevt_time_start() 146 writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); in mtk_timer_interrupt() 155 writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, in mtk_timer_setup() 158 writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, in mtk_timer_setup() 161 writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); in mtk_timer_setup() 163 writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, in mtk_timer_setup() 172 writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); in mtk_timer_enable_irq() [all …]
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D | arm_global_timer.c | 102 writel(ctrl, gt_base + GT_CONTROL); in gt_compare_set() 103 writel(lower_32_bits(counter), gt_base + GT_COMP0); in gt_compare_set() 104 writel(upper_32_bits(counter), gt_base + GT_COMP1); in gt_compare_set() 107 writel(delta, gt_base + GT_AUTO_INC); in gt_compare_set() 112 writel(ctrl, gt_base + GT_CONTROL); in gt_compare_set() 122 writel(ctrl, gt_base + GT_CONTROL); in gt_clockevent_shutdown() 215 writel(0, gt_base + GT_CONTROL); in gt_clocksource_init() 216 writel(0, gt_base + GT_COUNTER0); in gt_clocksource_init() 217 writel(0, gt_base + GT_COUNTER1); in gt_clocksource_init() 219 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); in gt_clocksource_init()
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D | sun4i_timer.c | 62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); in sun4i_clkevt_time_stop() 68 writel(delay, timer_base + TIMER_INTVAL_REG(timer)); in sun4i_clkevt_time_setup() 80 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, in sun4i_clkevt_time_start() 131 writel(0x1, timer_base + TIMER_IRQ_ST_REG); in sun4i_timer_interrupt() 171 writel(~0, timer_base + TIMER_INTVAL_REG(1)); in sun4i_timer_init() 172 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | in sun4i_timer_init() 190 writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), in sun4i_timer_init() 208 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); in sun4i_timer_init()
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/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb/ |
D | espi.c | 65 writel(V_WRITE_DATA(wr_data) | in tricn_write() 71 writel(0, adapter->regs + A_ESPI_GOSTAT); in tricn_write() 92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); in tricn_init() 111 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, in tricn_init() 129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_enable() 130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_enable() 136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); in t1_espi_intr_clear() 137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); in t1_espi_intr_clear() 144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); in t1_espi_intr_disable() 145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); in t1_espi_intr_disable() [all …]
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D | tp.c | 31 writel(val, ap->regs + A_TP_IN_CONFIG); in tp_init() 32 writel(F_TP_OUT_CSPI_CPL | in tp_init() 36 writel(V_IP_TTL(64) | in tp_init() 46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | in tp_init() 77 writel(0xffffffff, in t1_tp_intr_enable() 79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_enable() 85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); in t1_tp_intr_enable() 86 writel(tp_intr | F_PL_INTR_TP, in t1_tp_intr_enable() 98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); in t1_tp_intr_disable() 99 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, in t1_tp_intr_disable() [all …]
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/linux-4.4.14/arch/arm/mach-pxa/ |
D | cm-x2xx-pci.c | 136 writel(0x848, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit() 137 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit() 140 writel(0x840, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit() 141 writel(0, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit() 143 writel(0x20, IT8152_GPIO_GPDR); in cmx2xx_pci_preinit() 146 writel(0x4000, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit() 151 writel(0x408C, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit() 152 writel(0x1022, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit() 154 writel(0x4080, IT8152_PCI_CFG_ADDR); in cmx2xx_pci_preinit() 155 writel(0x3844d060, IT8152_PCI_CFG_DATA); in cmx2xx_pci_preinit() [all …]
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/linux-4.4.14/arch/unicore32/kernel/ |
D | irq.c | 68 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); in puv3_gpio_type() 69 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); in puv3_gpio_type() 79 writel((1 << d->irq), GPIO_GEDR); in puv3_low_gpio_ack() 84 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); in puv3_low_gpio_mask() 89 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); in puv3_low_gpio_unmask() 95 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); in puv3_low_gpio_wake() 97 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); in puv3_low_gpio_wake() 125 writel(mask, GPIO_GEDR); in puv3_gpio_handler() 147 writel(mask, GPIO_GEDR); in puv3_high_gpio_ack() 156 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); in puv3_high_gpio_mask() [all …]
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D | time.c | 29 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_ost0_interrupt() 30 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_ost0_interrupt() 41 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); in puv3_osmr0_set_next_event() 43 writel(next, OST_OSMR0); in puv3_osmr0_set_next_event() 51 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); in puv3_osmr0_shutdown() 52 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); in puv3_osmr0_shutdown() 87 writel(0, OST_OIER); /* disable any timer interrupts */ in time_init() 88 writel(0, OST_OSSR); /* clear status on all timers */ in time_init() 118 writel(0, OST_OSSR); in puv3_timer_resume() 119 writel(osmr[0], OST_OSMR0); in puv3_timer_resume() [all …]
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D | pci.c | 32 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_read_config() 51 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); in puv3_write_config() 54 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) in puv3_write_config() 58 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) in puv3_write_config() 62 writel(value, PCICFG_DATA); in puv3_write_config() 77 writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); in pci_puv3_preinit() 79 writel(0, PCIBRI_AHBCTL0); in pci_puv3_preinit() 80 writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); in pci_puv3_preinit() 81 writel(0xFFFF0000, PCIBRI_AHBAMR0); in pci_puv3_preinit() 82 writel(0, PCIBRI_AHBTAR0); in pci_puv3_preinit() [all …]
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/linux-4.4.14/drivers/media/platform/s5p-jpeg/ |
D | jpeg-hw-exynos3250.c | 26 writel(1, regs + EXYNOS3250_SW_RESET); in exynos3250_jpeg_reset() 38 writel(1, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset() 44 writel(0, regs + EXYNOS3250_JPGDRI); in exynos3250_jpeg_reset() 49 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON); in exynos3250_jpeg_poweron() 54 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) & in exynos3250_jpeg_set_dma_num() 69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_clk_set() 120 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_input_raw_fmt() 132 writel(reg, regs + EXYNOS3250_JPGCMOD); in exynos3250_jpeg_set_y16() 146 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_proc_mode() 168 writel(reg, regs + EXYNOS3250_JPGMOD); in exynos3250_jpeg_subsampling_mode() [all …]
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D | jpeg-hw-exynos4.c | 24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode() 42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | in exynos4_jpeg_set_enc_dec_mode() 129 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_img_fmt() 162 writel(reg, base + EXYNOS4_IMG_FMT_REG); in __exynos4_jpeg_set_enc_out_fmt() 171 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt() 175 writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); in exynos4_jpeg_set_interrupt() 204 writel(reg | EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable() 207 writel(reg & ~EXYNOS4_HUF_TBL_EN, in exynos4_jpeg_set_huf_table_enable() [all …]
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D | jpeg-hw-s5p.c | 24 writel(1, regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 35 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); in s5p_jpeg_poweron() 51 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 66 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_proc_mode() 81 writel(reg, regs + S5P_JPGMOD); in s5p_jpeg_subsampling_mode() 96 writel(reg, regs + S5P_JPGDRI_U); in s5p_jpeg_dri() 101 writel(reg, regs + S5P_JPGDRI_L); in s5p_jpeg_dri() 111 writel(reg, regs + S5P_JPG_QTBL); in s5p_jpeg_qtbl() 122 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_ac() 133 writel(reg, regs + S5P_JPG_HTBL); in s5p_jpeg_htbl_dc() [all …]
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/linux-4.4.14/arch/arm/mach-netx/ |
D | time.c | 40 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in timer_shutdown() 55 writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); in netx_set_oneshot() 56 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in netx_set_oneshot() 67 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); in netx_set_periodic() 68 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); in netx_set_periodic() 76 writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); in netx_set_next_event() 99 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); in netx_timer_interrupt() 118 writel(0, NETX_GPIO_COUNTER_CTRL(0)); in netx_timer_init() 121 writel(0, NETX_GPIO_COUNTER_CURRENT(0)); in netx_timer_init() 123 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0)); in netx_timer_init() [all …]
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D | generic.c | 116 writel(val, NETX_DPMAS_IF_CONF1); in netx_hif_irq_type() 127 writel((1 << 24) << irq, NETX_DPMAS_INT_STAT); in netx_hif_ack_irq() 131 writel(val, NETX_DPMAS_INT_EN); in netx_hif_ack_irq() 144 writel(val, NETX_DPMAS_INT_EN); in netx_hif_mask_irq() 156 writel(val, NETX_DPMAS_INT_EN); in netx_hif_unmask_irq() 179 writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); in netx_init_irq() 192 writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, in netx_restart()
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/linux-4.4.14/drivers/scsi/bfa/ |
D | bfa_ioc_ct.c | 73 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock() 75 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock() 76 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock() 95 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock() 104 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock() 106 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_lock() 124 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock() 128 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); in bfa_ioc_ct_firmware_unlock() 138 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail() 139 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail() [all …]
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D | bfa_ioc_cb.c | 121 writel(~0U, ioc->ioc_regs.err_set); in bfa_ioc_cb_notify_fail() 234 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_start() 235 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); in bfa_ioc_cb_sync_start() 255 writel(1, ioc->ioc_regs.ioc_sem_reg); in bfa_ioc_cb_ownership_reset() 267 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_join() 276 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); in bfa_ioc_cb_sync_leave() 285 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_cur_ioc_fwstate() 302 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), in bfa_ioc_cb_set_alt_ioc_fwstate() 378 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_cb_pll_init() 381 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_cb_pll_init() [all …]
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/linux-4.4.14/drivers/net/ethernet/brocade/bna/ |
D | bfa_ioc_ct.c | 139 writel(1, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock() 141 writel(0, ioc->ioc_regs.ioc_fail_sync); in bfa_ioc_ct_firmware_lock() 165 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_lock() 190 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); in bfa_ioc_ct_firmware_unlock() 199 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); in bfa_ioc_ct_notify_fail() 200 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); in bfa_ioc_ct_notify_fail() 427 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set() 437 writel(1, ioc->ioc_regs.lpu_read_stat); in bfa_ioc_ct2_lpu_read_stat() 460 writel(r32 & __MSIX_VT_OFST_, in bfa_nw_ioc_ct2_poweron() 465 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | in bfa_nw_ioc_ct2_poweron() [all …]
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/linux-4.4.14/arch/arm/mach-gemini/ |
D | time.c | 78 writel(cr + cycles, TIMER_MATCH1(TIMER1_BASE)); in gemini_timer_set_next_event() 96 writel(cr, TIMER_CR); in gemini_timer_shutdown() 99 writel(0, TIMER_COUNT(TIMER1_BASE)); in gemini_timer_shutdown() 100 writel(0, TIMER_LOAD(TIMER1_BASE)); in gemini_timer_shutdown() 106 writel(cr, TIMER_INTR_MASK); in gemini_timer_shutdown() 111 writel(cr, TIMER_CR); in gemini_timer_shutdown() 124 writel(cr, TIMER_CR); in gemini_timer_set_periodic() 128 writel(cr, TIMER_COUNT(TIMER1_BASE)); in gemini_timer_set_periodic() 129 writel(cr, TIMER_LOAD(TIMER1_BASE)); in gemini_timer_set_periodic() 135 writel(cr, TIMER_INTR_MASK); in gemini_timer_set_periodic() [all …]
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/linux-4.4.14/drivers/video/fbdev/exynos/ |
D | exynos_mipi_dsi_lowlevel.c | 40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_func_reset() 51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); in exynos_mipi_dsi_sw_reset() 62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); in exynos_mipi_dsi_sw_reset_release() 90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); in exynos_mipi_dsi_set_interrupt_mask() 100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer() 104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); in exynos_mipi_dsi_init_fifo_pointer() 113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); in exynos_mipi_dsi_set_phy_tunning() 128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_stand_by() 139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_disp_resol() 145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); in exynos_mipi_dsi_set_main_disp_resol() [all …]
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/linux-4.4.14/arch/m68k/coldfire/ |
D | m53xx.c | 311 writel(0x77777777, MCF_SCM_MPR); in scm_init() 315 writel(0, MCF_SCM_PACRA); in scm_init() 316 writel(0, MCF_SCM_PACRB); in scm_init() 317 writel(0, MCF_SCM_PACRC); in scm_init() 318 writel(0, MCF_SCM_PACRD); in scm_init() 319 writel(0, MCF_SCM_PACRE); in scm_init() 320 writel(0, MCF_SCM_PACRF); in scm_init() 323 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); in scm_init() 332 writel(0x10080000, MCF_FBCS1_CSAR); in fbcs_init() 334 writel(0x002A3780, MCF_FBCS1_CSCR); in fbcs_init() [all …]
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D | intc-5272.c | 89 writel(v, intc_irqmap[irq].icr); in intc_irq_mask() 101 writel(v, intc_irqmap[irq].icr); in intc_irq_unmask() 117 writel(v, intc_irqmap[irq].icr); in intc_irq_ack() 135 writel(v, MCFSIM_PITR); in intc_irq_set_type() 166 writel(0x88888888, MCFSIM_ICR1); in init_IRQ() 167 writel(0x88888888, MCFSIM_ICR2); in init_IRQ() 168 writel(0x88888888, MCFSIM_ICR3); in init_IRQ() 169 writel(0x88888888, MCFSIM_ICR4); in init_IRQ()
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/linux-4.4.14/drivers/video/fbdev/geode/ |
D | display_gx1.c | 90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); in gx1_set_mode() 97 writel(tcfg, par->dc_regs + DC_TIMING_CFG); in gx1_set_mode() 104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode() 108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode() 114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); in gx1_set_mode() 135 writel(0, par->dc_regs + DC_FB_ST_OFFSET); in gx1_set_mode() 138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); in gx1_set_mode() 139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, in gx1_set_mode() 166 writel(val, par->dc_regs + DC_H_TIMING_1); in gx1_set_mode() 168 writel(val, par->dc_regs + DC_H_TIMING_2); in gx1_set_mode() [all …]
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D | video_cs5530.c | 92 writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG); in cs5530_set_dclk_frequency() 93 writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */ in cs5530_set_dclk_frequency() 95 writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */ in cs5530_set_dclk_frequency() 96 writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */ in cs5530_set_dclk_frequency() 134 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_configure_display() 184 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); in cs5530_blank_display()
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/linux-4.4.14/drivers/gpu/drm/sti/ |
D | sti_vtg.c | 120 writel(1, vtg->regs + VTG_DRST_AUTOC); in vtg_reset() 143 writel(video_top_field_start, regs + VTG_VID_TFO); in vtg_set_output_window() 144 writel(video_top_field_stop, regs + VTG_VID_TFS); in vtg_set_output_window() 145 writel(video_bottom_field_start, regs + VTG_VID_BFO); in vtg_set_output_window() 146 writel(video_bottom_field_stop, regs + VTG_VID_BFS); in vtg_set_output_window() 158 writel(mode->htotal, vtg->regs + VTG_CLKLN); in vtg_set_mode() 161 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); in vtg_set_mode() 169 writel(tmp, vtg->regs + VTG_H_HD_1); in vtg_set_mode() 173 writel(tmp, vtg->regs + VTG_TOP_V_VD_1); in vtg_set_mode() 174 writel(tmp, vtg->regs + VTG_BOT_V_VD_1); in vtg_set_mode() [all …]
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D | sti_vid.c | 65 writel(val, vid->regs + VID_CTL); in sti_vid_commit() 72 writel((ydo << 16) | xdo, vid->regs + VID_VPO); in sti_vid_commit() 73 writel((yds << 16) | xds, vid->regs + VID_VPS); in sti_vid_commit() 83 writel(val, vid->regs + VID_CTL); in sti_vid_disable() 89 writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL); in sti_vid_init() 92 writel(VID_ALP_OPAQUE, vid->regs + VID_ALP); in sti_vid_init() 95 writel(VID_MPR0_BT709, vid->regs + VID_MPR0); in sti_vid_init() 96 writel(VID_MPR1_BT709, vid->regs + VID_MPR1); in sti_vid_init() 97 writel(VID_MPR2_BT709, vid->regs + VID_MPR2); in sti_vid_init() 98 writel(VID_MPR3_BT709, vid->regs + VID_MPR3); in sti_vid_init() [all …]
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D | sti_vtac.c | 95 writel(VTAC_FIFO_CONFIG_VAL, vtac->regs + VTAC_RX_FIFO_CONFIG); in sti_vtac_rx_set_config() 101 writel(config, vtac->regs + VTAC_CONFIG); in sti_vtac_rx_set_config() 115 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8522); in sti_vtac_tx_set_config() 117 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config() 120 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config() 123 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config() 126 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config() 129 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); in sti_vtac_tx_set_config() 136 writel(config, vtac->regs + VTAC_CONFIG); in sti_vtac_tx_set_config()
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D | sti_hqvdp.c | 530 writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD); in sti_hqvdp_disable() 599 writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset, in sti_hqvdp_vtg_cb() 634 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE); in sti_hqvdp_init_plugs() 635 writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC); in sti_hqvdp_init_plugs() 636 writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC); in sti_hqvdp_init_plugs() 637 writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK); in sti_hqvdp_init_plugs() 638 writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG); in sti_hqvdp_init_plugs() 639 writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE); in sti_hqvdp_init_plugs() 640 writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL); in sti_hqvdp_init_plugs() 642 writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE); in sti_hqvdp_init_plugs() [all …]
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/linux-4.4.14/drivers/media/platform/s5p-mfc/ |
D | s5p_mfc_opr_v6.c | 38 #undef writel 39 #define writel(v, r) \ macro 416 writel(strm_size, mfc_regs->d_stream_data_size); in s5p_mfc_set_dec_stream_buffer_v6() 417 writel(buf_addr, mfc_regs->d_cpb_buffer_addr); in s5p_mfc_set_dec_stream_buffer_v6() 418 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); in s5p_mfc_set_dec_stream_buffer_v6() 419 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); in s5p_mfc_set_dec_stream_buffer_v6() 443 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); in s5p_mfc_set_dec_frame_buffer_v6() 444 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6() 445 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); in s5p_mfc_set_dec_frame_buffer_v6() 447 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); in s5p_mfc_set_dec_frame_buffer_v6() [all …]
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/linux-4.4.14/drivers/net/hippi/ |
D | rrunner.c | 189 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, in rr_init_one() 231 writel(HALT_NIC, &rr->regs->HostCtrl); in rr_remove_one() 272 writel(*(u32*)(cmd), ®s->CmdRing[idx]); in rr_issue_cmd() 300 writel(0x01000000, ®s->TX_state); in rr_reset() 301 writel(0xff800000, ®s->RX_state); in rr_reset() 302 writel(0, ®s->AssistState); in rr_reset() 303 writel(CLEAR_INTA, ®s->LocalCtrl); in rr_reset() 304 writel(0x01, ®s->BrkPt); in rr_reset() 305 writel(0, ®s->Timer); in rr_reset() 306 writel(0, ®s->TimerRef); in rr_reset() [all …]
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/linux-4.4.14/drivers/spi/ |
D | spi-sirf.c | 307 writel(readl(sspi->base + sspi->regs->usp_mode1) & in sirfsoc_usp_hwinit() 309 writel(readl(sspi->base + sspi->regs->usp_mode1) | in sirfsoc_usp_hwinit() 337 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u8() 366 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u16() 396 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u32() 409 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq() 410 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq() 422 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq() 425 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_irq() 428 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq() [all …]
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D | spi-altera.c | 76 writel(1 << spi->chip_select, in altera_spi_chipsel() 79 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 84 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 85 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL); in altera_spi_chipsel() 92 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 96 writel(1 << spi->chip_select, in altera_spi_chipsel() 99 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_txrx() 135 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA); in altera_spi_txrx() 140 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_txrx() [all …]
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D | spi-mxs.c | 98 writel(BM_SSP_CTRL0_LOCK_CS, in mxs_spi_setup_transfer() 101 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | in mxs_spi_setup_transfer() 107 writel(0x0, ssp->base + HW_SSP_CMD0); in mxs_spi_setup_transfer() 108 writel(0x0, ssp->base + HW_SSP_CMD1); in mxs_spi_setup_transfer() 313 writel(BM_SSP_CTRL0_IGNORE_CRC, in mxs_spi_txrx_pio() 318 writel(BM_SSP_CTRL0_IGNORE_CRC, in mxs_spi_txrx_pio() 322 writel(BM_SSP_CTRL0_XFER_COUNT, in mxs_spi_txrx_pio() 324 writel(1, in mxs_spi_txrx_pio() 327 writel(1, ssp->base + HW_SSP_XFER_SIZE); in mxs_spi_txrx_pio() 331 writel(BM_SSP_CTRL0_READ, in mxs_spi_txrx_pio() [all …]
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/linux-4.4.14/sound/soc/ux500/ |
D | ux500_msp_i2s.c | 144 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx() 172 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx() 211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol() 214 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol() 229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk() 261 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk() 268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk() 298 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel() 301 writel(mcfg->tx_channel_0_enable, in configure_multichannel() 303 writel(mcfg->tx_channel_1_enable, in configure_multichannel() [all …]
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/linux-4.4.14/arch/arm/plat-orion/ |
D | time.c | 86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_next_event() 90 writel(u, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_next_event() 95 writel(delta, timer_base + TIMER1_VAL_OFF); in orion_clkevt_next_event() 102 writel(u, timer_base + TIMER_CTRL_OFF); in orion_clkevt_next_event() 118 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); in orion_clkevt_shutdown() 122 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_shutdown() 125 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); in orion_clkevt_shutdown() 140 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); in orion_clkevt_set_periodic() 141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); in orion_clkevt_set_periodic() 145 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); in orion_clkevt_set_periodic() [all …]
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D | pcie.c | 89 writel(stat, base + PCIE_STAT_OFF); in orion_pcie_set_local_bus_nr() 105 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset() 115 writel(reg, base + PCIE_DEBUG_CTRL); in orion_pcie_reset() 135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); in orion_pcie_setup_wins() 136 writel(0, base + PCIE_BAR_LO_OFF(i)); in orion_pcie_setup_wins() 137 writel(0, base + PCIE_BAR_HI_OFF(i)); in orion_pcie_setup_wins() 141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); in orion_pcie_setup_wins() 142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); in orion_pcie_setup_wins() 143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); in orion_pcie_setup_wins() 146 writel(0, base + PCIE_WIN5_CTRL_OFF); in orion_pcie_setup_wins() [all …]
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/linux-4.4.14/drivers/irqchip/ |
D | irq-sun4i.c | 47 writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_irq_ack() 58 writel(val & ~(1 << irq_off), in sun4i_irq_mask() 70 writel(val | (1 << irq_off), in sun4i_irq_unmask() 105 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); in sun4i_of_init() 106 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); in sun4i_of_init() 107 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); in sun4i_of_init() 110 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); in sun4i_of_init() 111 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); in sun4i_of_init() 112 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); in sun4i_of_init() 115 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); in sun4i_of_init() [all …]
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D | irq-vic.c | 105 writel(VIC_VECT_CNTL_ENABLE | i, reg); in vic_init2() 108 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2() 121 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic() 122 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic() 125 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic() 126 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); in resume_one_vic() 130 writel(vic->soft_int, base + VIC_INT_SOFT); in resume_one_vic() 131 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); in resume_one_vic() 156 writel(vic->resume_irqs, base + VIC_INT_ENABLE); in suspend_one_vic() 157 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); in suspend_one_vic() [all …]
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D | irq-armada-370-xp.c | 97 writel(hwirq, main_int_base + in armada_370_xp_irq_mask() 100 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_mask() 109 writel(hwirq, main_int_base + in armada_370_xp_irq_unmask() 112 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_unmask() 242 writel(reg, per_cpu_int_base + in armada_370_xp_msi_init() 246 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); in armada_370_xp_msi_init() 275 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); in armada_xp_set_affinity() 298 writel(hw, per_cpu_int_base + in armada_370_xp_mpic_irq_map() 301 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); in armada_370_xp_mpic_irq_map() 328 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); in armada_xp_mpic_smp_cpu_init() [all …]
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/linux-4.4.14/drivers/net/ethernet/samsung/sxgbe/ |
D | sxgbe_dma.c | 41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init() 57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init() 61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init() 65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); in sxgbe_dma_channel_init() 69 writel(upper_32_bits(dma_tx), in sxgbe_dma_channel_init() 71 writel(lower_32_bits(dma_tx), in sxgbe_dma_channel_init() 74 writel(upper_32_bits(dma_rx), in sxgbe_dma_channel_init() 76 writel(lower_32_bits(dma_rx), in sxgbe_dma_channel_init() 84 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init() 88 writel(lower_32_bits(dma_addr), in sxgbe_dma_channel_init() [all …]
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D | sxgbe_mtl.c | 43 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init() 53 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init() 59 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); in sxgbe_mtl_dma_dm_rxqueue() 60 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); in sxgbe_mtl_dma_dm_rxqueue() 61 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); in sxgbe_mtl_dma_dm_rxqueue() 73 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize() 85 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_rxfifosize() 94 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_enable_txqueue() 103 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_disable_txqueue() 115 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_fc_active() [all …]
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D | sxgbe_core.c | 34 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init() 43 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init() 99 writel(high_word, ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); in sxgbe_core_set_umac_addr() 100 writel(low_word, ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); in sxgbe_core_set_umac_addr() 129 writel(tx_config, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_enable_tx() 141 writel(rx_config, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx() 165 writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_set_speed() 175 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_enable_rxqueue() 185 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_disable_rxqueue() 199 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode() [all …]
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/linux-4.4.14/drivers/media/platform/exynos-gsc/ |
D | gsc-regs.c | 20 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); in gsc_hw_set_sw_reset() 47 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_frm_done_irq_mask() 59 writel(cfg, dev->regs + GSC_IRQ); in gsc_hw_set_gsc_irq_enable() 71 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK); in gsc_hw_set_input_buf_masking() 72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK); in gsc_hw_set_input_buf_masking() 73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK); in gsc_hw_set_input_buf_masking() 85 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); in gsc_hw_set_output_buf_masking() 86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK); in gsc_hw_set_output_buf_masking() 87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK); in gsc_hw_set_output_buf_masking() 95 writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index)); in gsc_hw_set_input_addr() [all …]
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/linux-4.4.14/arch/arm/mach-cns3xxx/ |
D | core.c | 107 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); in cns3xxx_power_off() 118 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_shutdown() 128 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_oneshot() 139 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_set_periodic() 141 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_set_periodic() 150 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); in cns3xxx_timer_set_next_event() 151 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in cns3xxx_timer_set_next_event() 188 writel(val & ~(1 << 2), stat); in cns3xxx_timer_interrupt() 214 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); in __cns3xxx_timer_init() 216 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); in __cns3xxx_timer_init() [all …]
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/linux-4.4.14/arch/mips/ar7/ |
D | irq.c | 54 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_unmask_irq() 60 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_mask_irq() 66 writel(1 << ((d->irq - ar7_irq_base) % 32), in ar7_ack_irq() 72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); in ar7_unmask_sec_irq() 77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); in ar7_mask_sec_irq() 82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); in ar7_ack_sec_irq() 111 writel(0xffffffff, REG(ECR_OFFSET(0))); in ar7_irq_init() 112 writel(0xff, REG(ECR_OFFSET(32))); in ar7_irq_init() 113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); in ar7_irq_init() 114 writel(0xffffffff, REG(CR_OFFSET(0))); in ar7_irq_init() [all …]
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D | gpio.c | 64 writel(tmp, gpio_out); in ar7_gpio_set_value() 79 writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); in titan_gpio_set_value() 88 writel(readl(gpio_dir) | (1 << gpio), gpio_dir); in ar7_gpio_direction_input() 103 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), in titan_gpio_direction_input() 116 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); in ar7_gpio_direction_output() 133 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << in titan_gpio_direction_output() 167 writel(readl(gpio_en) | (1 << gpio), gpio_en); in ar7_gpio_enable_ar7() 177 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), in ar7_gpio_enable_titan() 194 writel(readl(gpio_en) & ~(1 << gpio), gpio_en); in ar7_gpio_disable_ar7() 204 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), in ar7_gpio_disable_titan() [all …]
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/linux-4.4.14/arch/arm/mach-sunxi/ |
D | platsmp.c | 83 writel(virt_to_phys(secondary_startup), in sun6i_smp_boot_secondary() 87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary() 91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); in sun6i_smp_boot_secondary() 95 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary() 99 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); in sun6i_smp_boot_secondary() 104 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); in sun6i_smp_boot_secondary() 108 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun6i_smp_boot_secondary() 112 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); in sun6i_smp_boot_secondary() 165 writel(virt_to_phys(secondary_startup), in sun8i_smp_boot_secondary() 169 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); in sun8i_smp_boot_secondary() [all …]
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/linux-4.4.14/drivers/media/platform/exynos4-is/ |
D | fimc-reg.c | 28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); in fimc_hw_reset() 33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset() 38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_reset() 97 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_rotation() 103 writel(flip, dev->regs + FIMC_REG_MSCTRL); in fimc_hw_set_rotation() 142 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); in fimc_hw_set_target_format() 147 writel(cfg, dev->regs + FIMC_REG_CITAREA); in fimc_hw_set_target_format() 157 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); in fimc_hw_set_out_dma_size() 165 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); in fimc_hw_set_out_dma_size() 179 writel(cfg, dev->regs + FIMC_REG_CIOYOFF); in fimc_hw_set_out_dma() [all …]
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D | fimc-lite-reg.c | 30 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset() 40 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_reset() 47 writel(cfg, dev->regs + FLITE_REG_CISTATUS); in flite_hw_clear_pending_irq() 61 writel(cfg, dev->regs + FLITE_REG_CISTATUS2); in flite_hw_clear_last_capture_end() 83 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_interrupt_mask() 90 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_start() 97 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); in flite_hw_capture_stop() 111 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_test_pattern() 150 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); in flite_hw_set_source_format() 157 writel(cfg, dev->regs + FLITE_REG_CISRCSIZE); in flite_hw_set_source_format() [all …]
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/linux-4.4.14/drivers/i2c/busses/ |
D | i2c-lpc2k.c | 92 writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_reset() 93 writel(0, i2c->base + LPC24XX_I2ADDR); in i2c_lpc2k_reset() 94 writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_reset() 105 writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_clear_arb() 140 writel(data, i2c->base + LPC24XX_I2DAT); in i2c_lpc2k_pump_msg() 141 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_pump_msg() 151 writel(i2c->msg->buf[i2c->msg_idx], in i2c_lpc2k_pump_msg() 155 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); in i2c_lpc2k_pump_msg() 156 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_pump_msg() 171 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); in i2c_lpc2k_pump_msg() [all …]
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D | i2c-bcm-kona.c | 176 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl() 182 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl() 189 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl() 196 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | in bcm_kona_i2c_send_cmd_to_ctrl() 208 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, in bcm_kona_i2c_enable_clock() 214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, in bcm_kona_i2c_disable_clock() 228 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, in bcm_kona_i2c_isr() 231 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); in bcm_kona_i2c_isr() 264 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); in bcm_kona_send_i2c_cmd() 276 writel(0, dev->base + IER_OFFSET); in bcm_kona_send_i2c_cmd() [all …]
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D | i2c-sirf.c | 115 writel(regval, in i2c_sirfsoc_queue_cmd() 128 writel(regval, in i2c_sirfsoc_queue_cmd() 130 writel(siic->buf[siic->finished_len++], in i2c_sirfsoc_queue_cmd() 137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); in i2c_sirfsoc_queue_cmd() 148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq() 160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, in i2c_sirfsoc_irq() 175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq() 191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address() 201 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_set_address() 212 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, in i2c_sirfsoc_xfer_msg() [all …]
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D | i2c-bcm-iproc.c | 115 writel(status, iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_isr() 173 writel(addr, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 184 writel(val, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 197 writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 210 writel(val, iproc_i2c->base + M_CMD_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 215 writel(0, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 228 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 237 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 317 writel(val, iproc_i2c->base + TIM_CFG_OFFSET); in bcm_iproc_i2c_cfg_speed() 332 writel(val, iproc_i2c->base + CFG_OFFSET); in bcm_iproc_i2c_init() [all …]
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D | i2c-axxia.c | 116 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); in i2c_int_disable() 124 writel(int_en | mask, idev->base + MST_INT_ENABLE); in i2c_int_enable() 149 writel(0x01, idev->base + SOFT_RESET); in axxia_i2c_init() 159 writel(0x1, idev->base + GLOBAL_CONTROL); in axxia_i2c_init() 174 writel(t_high, idev->base + SCL_HIGH_PERIOD); in axxia_i2c_init() 176 writel(t_low, idev->base + SCL_LOW_PERIOD); in axxia_i2c_init() 178 writel(t_setup, idev->base + SDA_SETUP_TIME); in axxia_i2c_init() 180 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); in axxia_i2c_init() 182 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); in axxia_i2c_init() 197 writel(prescale, idev->base + TIMER_CLOCK_DIV); in axxia_i2c_init() [all …]
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D | i2c-qup.c | 142 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt() 151 writel(qup_err, qup->base + QUP_ERROR_FLAGS); in qup_i2c_interrupt() 157 writel(QUP_RESET_STATE, qup->base + QUP_STATE); in qup_i2c_interrupt() 162 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt() 165 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); in qup_i2c_interrupt() 217 writel(state, qup->base + QUP_STATE); in qup_i2c_change_state() 254 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); in qup_i2c_set_write_mode() 255 writel(total, qup->base + QUP_MX_WRITE_CNT); in qup_i2c_set_write_mode() 258 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN, in qup_i2c_set_write_mode() 260 writel(total, qup->base + QUP_MX_OUTPUT_CNT); in qup_i2c_set_write_mode() [all …]
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D | i2c-uniphier-f.c | 118 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo() 140 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs() 145 writel(-1, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs() 154 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO, in uniphier_fi2c_stop() 222 writel(UNIPHIER_FI2C_CR_MST | in uniphier_fi2c_interrupt() 254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init() 256 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1, in uniphier_fi2c_tx_init() 271 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); in uniphier_fi2c_rx_init() 280 writel(0, priv->membase + UNIPHIER_FI2C_RBC); in uniphier_fi2c_rx_init() 286 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1, in uniphier_fi2c_rx_init() [all …]
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D | i2c-puv3.c | 62 writel(i2c_reg | I2C_DATACMD_WRITE, I2C_DATACMD); in xfer_read() 68 writel(I2C_DATACMD_READ, I2C_DATACMD); in xfer_read() 101 writel(i2c_reg | I2C_DATACMD_WRITE, I2C_DATACMD); in xfer_write() 104 writel(*buf | I2C_DATACMD_WRITE, I2C_DATACMD); in xfer_write() 128 writel(I2C_ENABLE_DISABLE, I2C_ENABLE); in puv3_i2c_xfer() 131 writel(I2C_CON_MASTER | I2C_CON_SPEED_STD | I2C_CON_SLAVEDISABLE, I2C_CON); in puv3_i2c_xfer() 133 writel(pmsg->addr, I2C_TAR); in puv3_i2c_xfer() 136 writel(I2C_ENABLE_ENABLE, I2C_ENABLE); in puv3_i2c_xfer() 252 writel(I2C_ENABLE_DISABLE, I2C_ENABLE); in puv3_i2c_suspend()
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D | i2c-exynos5.c | 251 writel(readl(i2c->regs + HSI2C_INT_STATUS), in exynos5_i2c_clr_pend_irq() 340 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1); in exynos5_i2c_set_timing() 341 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2); in exynos5_i2c_set_timing() 342 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3); in exynos5_i2c_set_timing() 344 writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_FS1); in exynos5_i2c_set_timing() 345 writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_FS2); in exynos5_i2c_set_timing() 346 writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_FS3); in exynos5_i2c_set_timing() 348 writel(i2c_timing_sla, i2c->regs + HSI2C_TIMING_SLA); in exynos5_i2c_set_timing() 386 writel(i2c_timeout, i2c->regs + HSI2C_TIMEOUT); in exynos5_i2c_init() 388 writel((HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), in exynos5_i2c_init() [all …]
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D | i2c-pxa.c | 341 writel(icr, _ICR(i2c)); in i2c_pxa_abort() 349 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP), in i2c_pxa_abort() 418 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c)); in i2c_pxa_set_master() 468 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c)); in i2c_pxa_set_slave() 478 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c)); in i2c_pxa_set_slave() 479 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c)); in i2c_pxa_set_slave() 498 writel(ICR_UR, _ICR(i2c)); in i2c_pxa_reset() 499 writel(I2C_ISR_INIT, _ISR(i2c)); in i2c_pxa_reset() 500 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c)); in i2c_pxa_reset() 503 writel(i2c->slave_addr, _ISAR(i2c)); in i2c_pxa_reset() [all …]
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D | i2c-nomadik.c | 202 writel(readl(reg) | mask, reg); in i2c_set_bit() 207 writel(readl(reg) & ~mask, reg); in i2c_clr_bit() 230 writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR); in flush_i2c_fifo() 256 writel(mask, dev->virtbase + I2C_IMSCR); in disable_all_interrupts() 267 writel(mask, dev->virtbase + I2C_ICR); in clear_all_interrupts() 358 writel(0x0, dev->virtbase + I2C_CR); in setup_i2c_controller() 359 writel(0x0, dev->virtbase + I2C_HSMCR); in setup_i2c_controller() 360 writel(0x0, dev->virtbase + I2C_TFTR); in setup_i2c_controller() 361 writel(0x0, dev->virtbase + I2C_RFTR); in setup_i2c_controller() 362 writel(0x0, dev->virtbase + I2C_DMAR); in setup_i2c_controller() [all …]
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D | i2c-mv64xxx.c | 207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); in mv64xxx_i2c_hw_init() 208 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); in mv64xxx_i2c_hw_init() 209 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init() 211 writel(0, drv_data->reg_base + in mv64xxx_i2c_hw_init() 215 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); in mv64xxx_i2c_hw_init() 216 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), in mv64xxx_i2c_hw_init() 218 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); in mv64xxx_i2c_hw_init() 219 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); in mv64xxx_i2c_hw_init() 220 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, in mv64xxx_i2c_hw_init() 342 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, in mv64xxx_i2c_send_start() [all …]
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/linux-4.4.14/sound/soc/samsung/ |
D | s3c24xx-i2s.c | 76 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_txctrl() 77 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_txctrl() 78 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_txctrl() 93 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_txctrl() 94 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_txctrl() 95 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_txctrl() 121 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); in s3c24xx_snd_rxctrl() 122 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_rxctrl() 123 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); in s3c24xx_snd_rxctrl() 138 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); in s3c24xx_snd_rxctrl() [all …]
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D | s3c-i2s-v2.c | 113 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_txctrl() 114 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_txctrl() 142 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_txctrl() 143 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_txctrl() 185 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_rxctrl() 186 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_rxctrl() 210 writel(con, regs + S3C2412_IISCON); in s3c2412_snd_rxctrl() 211 writel(mod, regs + S3C2412_IISMOD); in s3c2412_snd_rxctrl() 295 writel(iismod, i2s->regs + S3C2412_IISMOD); in s3c2412_i2s_set_fmt() 334 writel(iismod, i2s->regs + S3C2412_IISMOD); in s3c_i2sv2_hw_params() [all …]
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D | ac97.c | 65 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate() 69 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate() 74 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_activate() 94 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_read() 100 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_read() 131 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_write() 137 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_write() 144 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); in s3c_ac97_write() 152 writel(S3C_AC97_GLBCTRL_COLDRESET, in s3c_ac97_cold_reset() 156 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); in s3c_ac97_cold_reset() [all …]
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/linux-4.4.14/drivers/gpu/ipu-v3/ |
D | ipu-dp.c | 101 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 105 writel(reg | ((u32) alpha << 24), in ipu_dp_set_global_alpha() 109 writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 112 writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 128 writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS); in ipu_dp_set_window_pos() 147 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_csc_init() 152 writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0); in ipu_dp_csc_init() 153 writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1); in ipu_dp_csc_init() 154 writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2); in ipu_dp_csc_init() 155 writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3); in ipu_dp_csc_init() [all …]
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D | ipu-dc.c | 127 writel(reg, dc->base + DC_RL_CH(event)); in dc_link_event() 146 writel(reg1, priv->dc_tmpl_reg + word * 8); in dc_write_tmpl() 147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); in dc_write_tmpl() 232 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_init_sync() 234 writel(0x0, dc->base + DC_WR_CH_ADDR); in ipu_dc_init_sync() 235 writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di)); in ipu_dc_init_sync() 265 writel(reg, dc->base + DC_WR_CH_CONF); in ipu_dc_enable_channel() 276 writel(reg, dc->base + DC_WR_CH_CONF); in dc_irq_handler() 308 writel(val, dc->base + DC_WR_CH_CONF); in ipu_dc_disable_channel() 339 writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config() [all …]
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/linux-4.4.14/sound/soc/fsl/ |
D | imx-ssi.c | 70 writel(sccr, ssi->base + SSI_STCCR); in imx_ssi_set_dai_tdm_slot() 75 writel(sccr, ssi->base + SSI_SRCCR); in imx_ssi_set_dai_tdm_slot() 77 writel(~tx_mask, ssi->base + SSI_STMSK); in imx_ssi_set_dai_tdm_slot() 78 writel(~rx_mask, ssi->base + SSI_SRMSK); in imx_ssi_set_dai_tdm_slot() 152 writel(strcr, ssi->base + SSI_STCR); in imx_ssi_set_dai_fmt() 153 writel(strcr, ssi->base + SSI_SRCR); in imx_ssi_set_dai_fmt() 154 writel(scr, ssi->base + SSI_SCR); in imx_ssi_set_dai_fmt() 182 writel(scr, ssi->base + SSI_SCR); in imx_ssi_set_dai_sysclk() 229 writel(stccr, ssi->base + SSI_STCCR); in imx_ssi_set_dai_clkdiv() 230 writel(srccr, ssi->base + SSI_SRCCR); in imx_ssi_set_dai_clkdiv() [all …]
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/linux-4.4.14/drivers/net/ethernet/sun/ |
D | sungem.c | 128 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_read() 166 writel(cmd, gp->regs + MIF_FRAME); in __sungem_phy_write() 191 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_enable_ints() 197 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); in gem_disable_ints() 368 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); in gem_rxmac_reset() 379 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, in gem_rxmac_reset() 392 writel(0, gp->regs + RXDMA_CFG); in gem_rxmac_reset() 406 writel(gp->swrst_base | GREG_SWRST_RXRST, in gem_rxmac_reset() 434 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); in gem_rxmac_reset() 435 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); in gem_rxmac_reset() [all …]
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D | cassini.c | 298 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); in cas_disable_irq() 315 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, in cas_disable_irq() 320 writel(INTRN_MASK_CLEAR_ALL, cp->regs + in cas_disable_irq() 338 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); in cas_enable_irq() 354 writel(INTRN_MASK_RX_EN, cp->regs + in cas_enable_irq() 390 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, in cas_entropy_reset() 413 writel(cmd, cp->regs + REG_MIF_FRAME); in cas_phy_read() 435 writel(cmd, cp->regs + REG_MIF_FRAME); in cas_phy_write() 688 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, in cas_mif_poll() 690 writel(cfg, cp->regs + REG_MIF_CFG); in cas_mif_poll() [all …]
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/linux-4.4.14/drivers/gpio/ |
D | gpio-sta2x11.c | 82 writel(bit, ®s->dats); in gsta_gpio_set() 84 writel(bit, ®s->datc); in gsta_gpio_set() 103 writel(bit, ®s->dirs); in gsta_gpio_direction_output() 106 writel(bit, ®s->dats); in gsta_gpio_direction_output() 108 writel(bit, ®s->datc); in gsta_gpio_direction_output() 118 writel(bit, ®s->dirc); in gsta_gpio_direction_input() 186 writel(val | bit, ®s->afsela); in gsta_set_config() 195 writel(bit, ®s->dirs); in gsta_set_config() 196 writel(bit, ®s->datc); in gsta_set_config() 199 writel(bit, ®s->dirs); in gsta_set_config() [all …]
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/linux-4.4.14/drivers/isdn/hisax/ |
D | telespci.c | 51 writel(WRITE_ADDR_ISAC | off, adr + 0x200); in readisac() 55 writel(READ_DATA_ISAC, adr + 0x200); in readisac() 68 writel(WRITE_ADDR_ISAC | off, adr + 0x200); in writeisac() 72 writel(WRITE_DATA_ISAC | data, adr + 0x200); in writeisac() 83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in readhscx() 87 writel(READ_DATA_HSCX, adr + 0x200); in readhscx() 99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); in writehscx() 103 writel(WRITE_DATA_HSCX | data, adr + 0x200); in writehscx() 117 writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200); in read_fifo_isac() 119 writel(READ_DATA_ISAC, adr + 0x200); in read_fifo_isac() [all …]
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/linux-4.4.14/arch/arm/mach-orion5x/ |
D | tsx09-common.c | 36 writel(0x83, UART1_REG(LCR)); in qnap_tsx09_power_off() 37 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_tsx09_power_off() 38 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in qnap_tsx09_power_off() 39 writel(0x03, UART1_REG(LCR)); in qnap_tsx09_power_off() 40 writel(0x00, UART1_REG(IER)); in qnap_tsx09_power_off() 41 writel(0x00, UART1_REG(FCR)); in qnap_tsx09_power_off() 42 writel(0x00, UART1_REG(MCR)); in qnap_tsx09_power_off() 45 writel('A', UART1_REG(TX)); in qnap_tsx09_power_off()
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D | terastation_pro2-setup.c | 195 writel(buf[i++], UART1_REG(TX)); in tsp2_miconwrite() 279 writel(0x83, UART1_REG(LCR)); in tsp2_power_off() 280 writel(divisor & 0xff, UART1_REG(DLL)); in tsp2_power_off() 281 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in tsp2_power_off() 282 writel(0x1b, UART1_REG(LCR)); in tsp2_power_off() 283 writel(0x00, UART1_REG(IER)); in tsp2_power_off() 284 writel(0x07, UART1_REG(FCR)); in tsp2_power_off() 285 writel(0x00, UART1_REG(MCR)); in tsp2_power_off()
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/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/ |
D | stmmac_hwtstamp.c | 33 writel(data, ioaddr + PTP_TCR); in stmmac_config_hw_tstamping() 51 writel(data, ioaddr + PTP_SSIR); in stmmac_config_sub_second_increment() 59 writel(sec, ioaddr + PTP_STSUR); in stmmac_init_systime() 60 writel(nsec, ioaddr + PTP_STNSUR); in stmmac_init_systime() 64 writel(value, ioaddr + PTP_TCR); in stmmac_init_systime() 84 writel(addend, ioaddr + PTP_TAR); in stmmac_config_addend() 88 writel(value, ioaddr + PTP_TCR); in stmmac_config_addend() 109 writel(sec, ioaddr + PTP_STSUR); in stmmac_adjust_systime() 110 writel(((add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec), in stmmac_adjust_systime() 115 writel(value, ioaddr + PTP_TCR); in stmmac_adjust_systime()
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D | dwmac_lib.c | 32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); in dwmac_enable_dma_transmission() 37 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac_enable_dma_irq() 42 writel(0, ioaddr + DMA_INTR_ENA); in dwmac_disable_dma_irq() 49 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_tx() 56 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_tx() 63 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_start_rx() 70 writel(value, ioaddr + DMA_CONTROL); in dwmac_dma_stop_rx() 209 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); in dwmac_dma_interrupt() 217 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo() 232 writel(data | GMAC_HI_REG_AE, ioaddr + high); in stmmac_set_mac_addr() [all …]
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D | dwmac1000_dma.c | 41 writel(value, ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init() 76 writel(value, ioaddr + DMA_BUS_MODE); in dwmac1000_dma_init() 95 writel(burst_len, ioaddr + DMA_AXI_BUS_MODE); in dwmac1000_dma_init() 98 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac1000_dma_init() 103 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); in dwmac1000_dma_init() 104 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); in dwmac1000_dma_init() 180 writel(csr6, ioaddr + DMA_CONTROL); in dwmac1000_dma_operation_mode() 204 writel(riwt, ioaddr + DMA_RX_WATCHDOG); in dwmac1000_rx_watchdog()
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D | dwmac1000_core.c | 45 writel(value, ioaddr + GMAC_CONTROL); in dwmac1000_core_init() 48 writel(0x207, ioaddr + GMAC_INT_MASK); in dwmac1000_core_init() 52 writel(0x0, ioaddr + GMAC_VLAN_TAG); in dwmac1000_core_init() 66 writel(value, ioaddr + GMAC_CONTROL); in dwmac1000_rx_ipc_enable() 111 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW); in dwmac1000_set_mchash() 112 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH); in dwmac1000_set_mchash() 127 writel(mcfilterbits[regs], in dwmac1000_set_mchash() 196 writel(value, ioaddr + GMAC_FRAME_FILTER); in dwmac1000_set_filter() 224 writel(flow, ioaddr + GMAC_FLOW_CTRL); in dwmac1000_flow_ctrl() 241 writel(pmt, ioaddr + GMAC_PMT); in dwmac1000_pmt() [all …]
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D | dwmac100_core.c | 40 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL); in dwmac100_core_init() 43 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1); in dwmac100_core_init() 112 writel(0xffffffff, ioaddr + MAC_HASH_HIGH); in dwmac100_set_filter() 113 writel(0xffffffff, ioaddr + MAC_HASH_LOW); in dwmac100_set_filter() 140 writel(mc_filter[0], ioaddr + MAC_HASH_LOW); in dwmac100_set_filter() 141 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH); in dwmac100_set_filter() 144 writel(value, ioaddr + MAC_CONTROL); in dwmac100_set_filter() 155 writel(flow, ioaddr + MAC_FLOW_CTRL); in dwmac100_flow_ctrl()
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D | dwmac100_dma.c | 43 writel(value, ioaddr + DMA_BUS_MODE); in dwmac100_dma_init() 54 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), in dwmac100_dma_init() 58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); in dwmac100_dma_init() 63 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); in dwmac100_dma_init() 64 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); in dwmac100_dma_init() 86 writel(csr6, ioaddr + DMA_CONTROL); in dwmac100_dma_operation_mode()
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/linux-4.4.14/drivers/phy/ |
D | phy-mt65xx-usb3.c | 140 writel(tmp, port_base + U3P_U2PHYDTM0); in phy_instance_init() 144 writel(tmp, port_base + U3P_U2PHYDTM1); in phy_instance_init() 149 writel(tmp, port_base + U3P_U2PHYACR4); in phy_instance_init() 153 writel(tmp, port_base + U3P_USBPHYACR2); in phy_instance_init() 157 writel(tmp, port_base + U3D_U2PHYDCR0); in phy_instance_init() 161 writel(tmp, port_base + U3D_U2PHYDCR0); in phy_instance_init() 165 writel(tmp, port_base + U3P_U2PHYDTM0); in phy_instance_init() 171 writel(tmp, port_base + U3P_USBPHYACR6); in phy_instance_init() 176 writel(tmp, port_base + U3P_U3PHYA_DA_REG0); in phy_instance_init() 181 writel(tmp, port_base + U3P_U3_PHYA_REG9); in phy_instance_init() [all …]
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D | phy-exynos5250-usb2.c | 233 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on() 239 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on() 262 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on() 266 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); in exynos5250_power_on() 285 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); in exynos5250_power_on() 295 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); in exynos5250_power_on() 296 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); in exynos5250_power_on() 299 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); in exynos5250_power_on() 300 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); in exynos5250_power_on() 311 writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL); in exynos5250_power_on() [all …]
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D | phy-berlin-usb.c | 125 writel(priv->pll_divider, in phy_berlin_usb_power_on() 127 writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL | in phy_berlin_usb_power_on() 129 writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5), in phy_berlin_usb_power_on() 131 writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 | in phy_berlin_usb_power_on() 135 writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1); in phy_berlin_usb_power_on() 136 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), in phy_berlin_usb_power_on() 139 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) | in phy_berlin_usb_power_on() 142 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), in phy_berlin_usb_power_on() 144 writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 | in phy_berlin_usb_power_on()
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D | phy-exynos5250-sata.c | 102 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init() 108 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init() 112 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init() 116 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init() 120 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); in exynos_sata_phy_init() 125 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); in exynos_sata_phy_init() 129 writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0); in exynos_sata_phy_init() 133 writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0); in exynos_sata_phy_init() 142 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init() 146 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); in exynos_sata_phy_init()
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/linux-4.4.14/arch/arm/mach-integrator/ |
D | integrator_ap.c | 125 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); in irq_resume() 126 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); in irq_resume() 128 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); in irq_resume() 156 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, in ap_flash_init() 161 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_init() 165 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); in ap_flash_init() 166 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_init() 167 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); in ap_flash_init() 176 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, in ap_flash_exit() 181 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); in ap_flash_exit() [all …]
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/linux-4.4.14/drivers/usb/host/ |
D | xhci-rcar.c | 67 writel(temp, hcd->regs + RCAR_USB3_INT_ENA); in xhci_rcar_start() 69 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK); in xhci_rcar_start() 71 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1); in xhci_rcar_start() 72 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2); in xhci_rcar_start() 73 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3); in xhci_rcar_start() 75 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL); in xhci_rcar_start() 76 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL); in xhci_rcar_start() 95 writel(temp, regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware() 103 writel(data, regs + RCAR_USB3_FW_DATA0); in xhci_rcar_download_firmware() 106 writel(temp, regs + RCAR_USB3_DL_CTRL); in xhci_rcar_download_firmware() [all …]
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/linux-4.4.14/drivers/mtd/spi-nor/ |
D | fsl-quadspi.c | 313 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_unlock_lut() 314 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_unlock_lut() 319 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_lock_lut() 320 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_lock_lut() 330 writel(reg, q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler() 351 writel(0, base + QUADSPI_LUT_BASE + i * 4); in fsl_qspi_init_lut() 367 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut() 369 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), in fsl_qspi_init_lut() 374 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut() 388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut() [all …]
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/linux-4.4.14/drivers/misc/ |
D | spear13xx_pcie_gadget.c | 72 writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access() 74 writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID), in enable_dbi_access() 82 writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access() 84 writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), in disable_dbi_access() 123 writel(val, va_address); in spear_dbi_write_reg() 247 writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID), in pcie_gadget_link_store() 250 writel(readl(&app_reg->app_ctrl_0) in pcie_gadget_link_store() 345 writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID), in pcie_gadget_inta_store() 348 writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID), in pcie_gadget_inta_store() 383 writel(ven_msi, &app_reg->ven_msi_1); in pcie_gadget_send_msi_store() [all …]
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D | tifm_7xx1.c | 54 writel(TIFM_IRQ_ENABLE, fm->addr + FM_CLEAR_INTERRUPT_ENABLE); in tifm_7xx1_isr() 69 writel(irq_status, fm->addr + FM_INTERRUPT_STATUS); in tifm_7xx1_isr() 74 writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE); in tifm_7xx1_isr() 87 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_toggle_sock_power() 101 writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED, in tifm_7xx1_toggle_sock_power() 109 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, in tifm_7xx1_toggle_sock_power() 121 writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED), in tifm_7xx1_toggle_sock_power() 129 writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL), in tifm_7xx1_sock_power_off() 175 writel(0x0e00, sock_addr + SOCK_CONTROL); in tifm_7xx1_switch_media() 202 writel(TIFM_IRQ_FIFOMASK(socket_change_set) in tifm_7xx1_switch_media() [all …]
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D | arm-charlcd.c | 82 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_interrupt() 98 writel(0x00, lcd->virtbase + CHAR_MASK); in charlcd_wait_complete_irq() 132 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_char() 150 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_char() 166 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); in charlcd_4bit_read_bf() 168 writel(0x01, lcd->virtbase + CHAR_MASK); in charlcd_4bit_read_bf() 190 writel(cmdhi, lcd->virtbase + CHAR_COM); in charlcd_4bit_command() 192 writel(cmdlo, lcd->virtbase + CHAR_COM); in charlcd_4bit_command() 201 writel(chhi, lcd->virtbase + CHAR_DAT); in charlcd_4bit_char() 203 writel(chlo, lcd->virtbase + CHAR_DAT); in charlcd_4bit_char() [all …]
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/linux-4.4.14/drivers/usb/phy/ |
D | phy-tegra-usb.c | 215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts() 220 writel(val, base + TEGRA_USB_PORTSC1); in set_pts() 235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd() 242 writel(val, base + TEGRA_USB_PORTSC1); in set_phcd() 280 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_on() 305 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_off() 335 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable() 341 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable() 357 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable() 363 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_enable() [all …]
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/linux-4.4.14/drivers/rtc/ |
D | rtc-stmp3xxx.c | 91 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); in stmp3xxx_wdt_set_timeout() 92 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, in stmp3xxx_wdt_set_timeout() 94 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, in stmp3xxx_wdt_set_timeout() 97 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, in stmp3xxx_wdt_set_timeout() 99 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, in stmp3xxx_wdt_set_timeout() 166 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS); in stmp3xxx_rtc_set_mmss() 177 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ, in stmp3xxx_rtc_interrupt() 191 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | in stmp3xxx_alarm_irq_enable() 195 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, in stmp3xxx_alarm_irq_enable() 198 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | in stmp3xxx_alarm_irq_enable() [all …]
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D | rtc-sun6i.c | 128 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_alarmirq() 149 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, in sun6i_rtc_setaie() 153 writel(alrm_val, chip->base + SUN6I_ALRM_EN); in sun6i_rtc_setaie() 154 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); in sun6i_rtc_setaie() 155 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); in sun6i_rtc_setaie() 237 writel(0, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_setalarm() 240 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_setalarm() 301 writel(time, chip->base + SUN6I_RTC_HMS); in sun6i_rtc_settime() 315 writel(date, chip->base + SUN6I_RTC_YMD); in sun6i_rtc_settime() 382 writel(0, chip->base + SUN6I_ALRM_COUNTER); in sun6i_rtc_probe() [all …]
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D | rtc-sunxi.c | 168 writel(val, chip->base + SUNXI_ALRM_IRQ_STA); in sunxi_rtc_alarmirq() 190 writel(SUNXI_ALRM_IRQ_STA_CNT_IRQ_PEND, in sunxi_rtc_setaie() 194 writel(alrm_val, chip->base + SUNXI_ALRM_EN); in sunxi_rtc_setaie() 195 writel(alrm_irq_val, chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setaie() 306 writel(0, chip->base + SUNXI_ALRM_DHMS); in sunxi_rtc_setalarm() 313 writel(alrm, chip->base + SUNXI_ALRM_DHMS); in sunxi_rtc_setalarm() 315 writel(0, chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setalarm() 316 writel(SUNXI_ALRM_IRQ_EN_CNT_IRQ_EN, chip->base + SUNXI_ALRM_IRQ_EN); in sunxi_rtc_setalarm() 376 writel(0, chip->base + SUNXI_RTC_HMS); in sunxi_rtc_settime() 377 writel(0, chip->base + SUNXI_RTC_YMD); in sunxi_rtc_settime() [all …]
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D | rtc-coh901331.c | 59 writel(1, rtap->virtbase + COH901331_IRQ_EVENT); in coh901331_interrupt() 67 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_interrupt() 96 writel(secs, rtap->virtbase + COH901331_SET_TIME); in coh901331_set_mmss() 122 writel(time, rtap->virtbase + COH901331_ALARM); in coh901331_set_alarm() 123 writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_set_alarm() 135 writel(1, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_alarm_irq_enable() 137 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_alarm_irq_enable() 228 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_suspend() 244 writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_resume() 258 writel(0, rtap->virtbase + COH901331_IRQ_MASK); in coh901331_shutdown()
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D | rtc-pl031.c | 102 writel(RTC_BIT_AI, ldata->base + RTC_ICR); in pl031_alarm_irq_enable() 107 writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC); in pl031_alarm_irq_enable() 109 writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC); in pl031_alarm_irq_enable() 189 writel(bcd_year, ldata->base + RTC_YLR); in pl031_stv2_set_time() 190 writel(time, ldata->base + RTC_LR); in pl031_stv2_set_time() 223 writel(bcd_year, ldata->base + RTC_YMR); in pl031_stv2_set_alarm() 224 writel(time, ldata->base + RTC_MR); in pl031_stv2_set_alarm() 241 writel(RTC_BIT_AI, ldata->base + RTC_ICR); in pl031_interrupt() 269 writel(time, ldata->base + RTC_LR); in pl031_set_time() 297 writel(time, ldata->base + RTC_MR); in pl031_set_alarm() [all …]
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/linux-4.4.14/drivers/mmc/host/ |
D | tifm_sd.c | 150 writel(val, sock->addr + SOCK_MMCSD_DATA); in tifm_sd_write_fifo() 162 writel(val, sock->addr + SOCK_MMCSD_DATA); in tifm_sd_write_fifo() 185 writel(host->bounce_buf_data[0], in tifm_sd_transfer_data() 319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS); in tifm_sd_set_dma_data() 321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN, in tifm_sd_set_dma_data() 324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN, in tifm_sd_set_dma_data() 386 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH); in tifm_sd_exec() 387 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW); in tifm_sd_exec() 388 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND); in tifm_sd_exec() 433 writel(TIFM_MMCSD_EOFB in tifm_sd_check_status() [all …]
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D | davinci_mmc.c | 262 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); in davinci_fifo_data_trans() 361 writel(0x1FFF, host->base + DAVINCI_MMCTOR); in mmc_davinci_start_command() 384 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); in mmc_davinci_start_command() 385 writel(cmd_reg, host->base + DAVINCI_MMCCMD); in mmc_davinci_start_command() 399 writel(im_val, host->base + DAVINCI_MMCIM); in mmc_davinci_start_command() 566 writel(0, host->base + DAVINCI_MMCBLEN); in mmc_davinci_prepare_data() 567 writel(0, host->base + DAVINCI_MMCNBLK); in mmc_davinci_prepare_data() 582 writel(timeout, host->base + DAVINCI_MMCTOD); in mmc_davinci_prepare_data() 583 writel(data->blocks, host->base + DAVINCI_MMCNBLK); in mmc_davinci_prepare_data() 584 writel(data->blksz, host->base + DAVINCI_MMCBLEN); in mmc_davinci_prepare_data() [all …]
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D | moxart-mmc.c | 192 writel(*status & mask, host->base + REG_CLEAR); in moxart_wait_for_status() 209 writel(RSP_TIMEOUT | RSP_CRC_OK | in moxart_send_command() 211 writel(cmd->arg, host->base + REG_ARGUMENT); in moxart_send_command() 225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); in moxart_send_command() 390 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); in moxart_prepare_data() 391 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); in moxart_prepare_data() 392 writel(host->rate, host->base + REG_DATA_TIMER); in moxart_prepare_data() 393 writel(host->data_len, host->base + REG_DATA_LENGTH); in moxart_prepare_data() 394 writel(datactrl, host->base + REG_DATA_CONTROL); in moxart_prepare_data() 421 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); in moxart_request() [all …]
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D | sdhci-esdhc-imx.c | 256 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); in esdhc_clrset_le() 328 writel(SDHCI_INT_RESPONSE, host->ioaddr + in esdhc_readl_le() 355 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le() 357 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); in esdhc_writel_le() 372 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writel_le() 379 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); in esdhc_writel_le() 384 writel(val, host->ioaddr + reg); in esdhc_writel_le() 460 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le() 468 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); in esdhc_writew_le() 475 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); in esdhc_writew_le() [all …]
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/linux-4.4.14/drivers/net/ethernet/allwinner/ |
D | sun4i-emac.c | 99 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed() 112 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex() 193 writel(0, db->membase + EMAC_CTL_REG); in emac_reset() 195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); in emac_reset() 269 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, in emac_setup() 275 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | in emac_setup() 284 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_setup() 287 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); in emac_setup() 290 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, in emac_setup() 294 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, in emac_setup() [all …]
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/linux-4.4.14/drivers/pci/host/ |
D | pci-xgene.c | 115 writel(rtdid_val, port->csr_base + RTDID); in xgene_pcie_set_rtdid_reg() 191 writel(val, csr_base + addr); in xgene_pcie_set_ib_mask() 195 writel(val, csr_base + addr + 0x04); in xgene_pcie_set_ib_mask() 199 writel(val, csr_base + addr + 0x04); in xgene_pcie_set_ib_mask() 203 writel(val, csr_base + addr + 0x08); in xgene_pcie_set_ib_mask() 286 writel(lower_32_bits(cpu_addr), base); in xgene_pcie_setup_ob_reg() 287 writel(upper_32_bits(cpu_addr), base + 0x04); in xgene_pcie_setup_ob_reg() 288 writel(lower_32_bits(mask), base + 0x08); in xgene_pcie_setup_ob_reg() 289 writel(upper_32_bits(mask), base + 0x0c); in xgene_pcie_setup_ob_reg() 290 writel(lower_32_bits(pci_addr), base + 0x10); in xgene_pcie_setup_ob_reg() [all …]
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D | pci-keystone-dw.c | 111 writel(BIT(bit_pos), in ks_dw_pcie_msi_irq_ack() 113 writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI); in ks_dw_pcie_msi_irq_ack() 122 writel(BIT(bit_pos), in ks_dw_pcie_msi_set_irq() 132 writel(BIT(bit_pos), in ks_dw_pcie_msi_clear_irq() 224 writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4)); in ks_dw_pcie_enable_legacy_irqs() 243 writel(offset, ks_pcie->va_app_base + IRQ_EOI); in ks_dw_pcie_handle_legacy_irq() 291 writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS), in ks_dw_pcie_set_dbi_mode() 309 writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS), in ks_dw_pcie_clear_dbi_mode() 325 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); in ks_dw_pcie_setup_rc_app_regs() 326 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); in ks_dw_pcie_setup_rc_app_regs() [all …]
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D | pci-versatile.c | 100 writel(res->start >> 28, PCI_IMAP(mem)); in versatile_pci_parse_request_of_pci_ranges() 101 writel(PHYS_OFFSET >> 28, PCI_SMAP(mem)); in versatile_pci_parse_request_of_pci_ranges() 181 writel(myslot, PCI_SELFID); in versatile_pci_probe() 186 writel(val, local_pci_cfg_base + PCI_COMMAND); in versatile_pci_probe() 191 writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); in versatile_pci_probe() 192 writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); in versatile_pci_probe() 193 writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); in versatile_pci_probe() 206 writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE); in versatile_pci_probe()
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D | pci-imx6.c | 109 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack() 112 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack() 119 writel(val, dbi_base + PCIE_PHY_CTRL); in pcie_phy_wait_ack() 136 writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read() 146 writel(0x00, dbi_base + PCIE_PHY_CTRL); in pcie_phy_read() 163 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write() 167 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write() 175 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write() 184 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write() 193 writel(var, dbi_base + PCIE_PHY_CTRL); in pcie_phy_write() [all …]
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/linux-4.4.14/drivers/scsi/isci/ |
D | host.c | 202 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); in sci_controller_isr() 212 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); in sci_controller_isr() 213 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_isr() 251 writel(0xff, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr() 252 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr() 569 writel(ihost->completion_queue_get, in sci_controller_process_completions() 592 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status); in sci_controller_error_handler() 605 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_handler() 614 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); in isci_intx_isr() 707 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_enable_interrupts() [all …]
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D | phy.c | 101 writel(SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX, in sci_phy_transport_layer_initialization() 110 writel(tl_control, &iphy->transport_layer_registers->control); in sci_phy_transport_layer_initialization() 138 writel(SCU_SAS_TIID_GEN_BIT(SMP_INITIATOR) | in sci_phy_link_layer_initialization() 146 writel(0xFEDCBA98, &llr->sas_device_name_high); in sci_phy_link_layer_initialization() 147 writel(phy_idx, &llr->sas_device_name_low); in sci_phy_link_layer_initialization() 150 writel(phy_oem->sas_address.high, &llr->source_sas_address_high); in sci_phy_link_layer_initialization() 151 writel(phy_oem->sas_address.low, &llr->source_sas_address_low); in sci_phy_link_layer_initialization() 154 writel(0, &llr->identify_frame_phy_id); in sci_phy_link_layer_initialization() 155 writel(SCU_SAS_TIPID_GEN_VALUE(ID, phy_idx), &llr->identify_frame_phy_id); in sci_phy_link_layer_initialization() 162 writel(phy_configuration, &llr->phy_configuration); in sci_phy_link_layer_initialization() [all …]
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/linux-4.4.14/drivers/ata/ |
D | ahci_xgene.c | 107 writel(0x0, ctx->csr_diag + CFG_MEM_RAM_SHUTDOWN); in xgene_ahci_init_memram() 177 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); in xgene_ahci_restart_engine() 219 writel(port_fbs, port_mmio + PORT_FBS); in xgene_ahci_qc_issue() 289 writel(val, mmio + PORTCFG); in xgene_ahci_set_phy_cfg() 292 writel(0x0001fffe, mmio + PORTPHY1CFG); in xgene_ahci_set_phy_cfg() 294 writel(0x28183219, mmio + PORTPHY2CFG); in xgene_ahci_set_phy_cfg() 296 writel(0x13081008, mmio + PORTPHY3CFG); in xgene_ahci_set_phy_cfg() 298 writel(0x00480815, mmio + PORTPHY4CFG); in xgene_ahci_set_phy_cfg() 303 writel(val, mmio + PORTPHY5CFG); in xgene_ahci_set_phy_cfg() 308 writel(val, mmio + PORTAXICFG); in xgene_ahci_set_phy_cfg() [all …]
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D | ahci_ceva.c | 117 writel(tmp, mmio + AHCI_VEND_PAXIC); in ahci_ceva_setup() 122 writel(tmp, mmio + HOST_CTL); in ahci_ceva_setup() 127 writel(tmp, mmio + AHCI_VEND_PCFG); in ahci_ceva_setup() 131 writel(tmp, mmio + AHCI_VEND_PPCFG); in ahci_ceva_setup() 135 writel(tmp, mmio + AHCI_VEND_PP2C); in ahci_ceva_setup() 139 writel(tmp, mmio + AHCI_VEND_PP3C); in ahci_ceva_setup() 143 writel(tmp, mmio + AHCI_VEND_PP4C); in ahci_ceva_setup() 147 writel(tmp, mmio + AHCI_VEND_PP5C); in ahci_ceva_setup() 151 writel(tmp, mmio + AHCI_VEND_PTC); in ahci_ceva_setup() 157 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
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D | ahci_mvebu.c | 37 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config() 38 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config() 39 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config() 45 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config() 48 writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config() 49 writel(((cs->size - 1) & 0xffff0000), in ahci_mvebu_mbus_config() 61 writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR); in ahci_mvebu_regret_option() 62 writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); in ahci_mvebu_regret_option()
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D | ahci_tegra.c | 184 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); in tegra_ahci_controller_init() 197 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra_ahci_controller_init() 207 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra_ahci_controller_init() 218 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra_ahci_controller_init() 221 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, in tegra_ahci_controller_init() 223 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, in tegra_ahci_controller_init() 226 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra_ahci_controller_init() 232 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); in tegra_ahci_controller_init() 234 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); in tegra_ahci_controller_init() 238 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); in tegra_ahci_controller_init() [all …]
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D | ahci_qoriq.c | 113 writel(px_cmd, port_mmio + PORT_CMD); in ahci_qoriq_hardreset() 117 writel(px_is, port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset() 152 writel(SATA_ECC_DISABLE, qpriv->ecc_addr); in ahci_qoriq_phy_init() 153 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init() 154 writel(AHCI_PORT_PHY_2_CFG, reg_base + PORT_PHY2); in ahci_qoriq_phy_init() 155 writel(AHCI_PORT_PHY_3_CFG, reg_base + PORT_PHY3); in ahci_qoriq_phy_init() 156 writel(AHCI_PORT_PHY_4_CFG, reg_base + PORT_PHY4); in ahci_qoriq_phy_init() 157 writel(AHCI_PORT_PHY_5_CFG, reg_base + PORT_PHY5); in ahci_qoriq_phy_init() 158 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); in ahci_qoriq_phy_init() 163 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); in ahci_qoriq_phy_init()
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D | sata_sil24.c | 484 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); in sil24_dev_config() 486 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); in sil24_dev_config() 523 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); in sil24_scr_write() 535 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); in sil24_config_port() 537 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); in sil24_config_port() 548 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); in sil24_config_port() 551 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); in sil24_config_port() 559 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); in sil24_config_pmp() 561 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); in sil24_config_pmp() 569 writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); in sil24_clear_pmp() [all …]
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D | sata_sx4.c | 507 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_dma_prep() 542 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL); in pdc20621_nodata_prep() 574 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in __pdc20621_push_hdma() 577 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT); in __pdc20621_push_hdma() 667 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in pdc20621_packet_start() 670 writel(port_ofs + PDC_DIMM_ATA_PKT, in pdc20621_packet_start() 750 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4)); in pdc20621_host_intr() 752 writel(port_ofs + PDC_DIMM_ATA_PKT, in pdc20621_host_intr() 863 writel(tmp, mmio + PDC_CTLSTAT); in pdc_freeze() 880 writel(tmp, mmio + PDC_CTLSTAT); in pdc_thaw() [all …]
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/linux-4.4.14/arch/arm/mach-s3c64xx/ |
D | setup-usb-phy.c | 29 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_init() 52 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); in s3c_usb_otgphy_init() 55 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); in s3c_usb_otgphy_init() 59 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, in s3c_usb_otgphy_init() 62 writel(0, S3C_RSTCON); in s3c_usb_otgphy_init() 69 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | in s3c_usb_otgphy_exit() 72 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); in s3c_usb_otgphy_exit()
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/linux-4.4.14/drivers/net/ethernet/ |
D | korina.c | 144 writel(0, &ch->dmandptr); in korina_start_dma() 145 writel(dma_addr, &ch->dmadptr); in korina_start_dma() 152 writel(0x10, &ch->dmac); in korina_abort_dma() 157 writel(0, &ch->dmas); in korina_abort_dma() 160 writel(0, &ch->dmadptr); in korina_abort_dma() 161 writel(0, &ch->dmandptr); in korina_abort_dma() 166 writel(dma_addr, &ch->dmandptr); in korina_chain_dma() 244 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), in korina_send_packet() 260 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), in korina_send_packet() 299 writel(0, &lp->eth_regs->miimcfg); in mdio_read() [all …]
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/linux-4.4.14/drivers/thermal/ |
D | hisi_thermal.c | 87 writel(0x0, data->regs + TEMP0_INT_EN); in hisi_thermal_get_sensor_temp() 88 writel(0x1, data->regs + TEMP0_INT_CLR); in hisi_thermal_get_sensor_temp() 91 writel(0x0, data->regs + TEMP0_EN); in hisi_thermal_get_sensor_temp() 94 writel((sensor->id << 12), data->regs + TEMP0_CFG); in hisi_thermal_get_sensor_temp() 97 writel(0x1, data->regs + TEMP0_EN); in hisi_thermal_get_sensor_temp() 119 writel(0x0, data->regs + TEMP0_CFG); in hisi_thermal_enable_bind_irq_sensor() 122 writel(0x0, data->regs + TEMP0_RST_MSK); in hisi_thermal_enable_bind_irq_sensor() 123 writel(0x0, data->regs + TEMP0_EN); in hisi_thermal_enable_bind_irq_sensor() 126 writel((sensor->id << 12), data->regs + TEMP0_CFG); in hisi_thermal_enable_bind_irq_sensor() 129 writel(_temp_to_step(sensor->thres_temp) | 0x0FFFFFF00, in hisi_thermal_enable_bind_irq_sensor() [all …]
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D | armada_thermal.c | 80 writel(reg, priv->control); in armadaxp_init_sensor() 85 writel(reg, priv->control); in armadaxp_init_sensor() 89 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); in armadaxp_init_sensor() 91 writel(reg, priv->control); in armadaxp_init_sensor() 96 writel(reg, priv->sensor); in armadaxp_init_sensor() 106 writel(reg, priv->control); in armada370_init_sensor() 111 writel(reg, priv->control); in armada370_init_sensor() 114 writel(reg, priv->control); in armada370_init_sensor() 129 writel(reg, priv->control + 4); in armada375_init_sensor() 133 writel(reg, priv->control + 4); in armada375_init_sensor() [all …]
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/linux-4.4.14/drivers/tty/serial/ |
D | xilinx_uartps.c | 210 writel(CDNS_UART_IXR_FRAMING, in cdns_uart_isr() 276 writel(CDNS_UART_IXR_TXEMPTY, in cdns_uart_isr() 288 writel(port->state->xmit.buf[ in cdns_uart_isr() 308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); in cdns_uart_isr() 403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET); in cdns_uart_set_baud_rate() 404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); in cdns_uart_set_baud_rate() 405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); in cdns_uart_set_baud_rate() 454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb() 481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); in cdns_uart_clk_notifier_cb() 492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); in cdns_uart_clk_notifier_cb() [all …]
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D | lpc32xx_hs.c | 136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); in lpc32xx_hsuart_console_putchar() 271 writel(LPC32XX_HSU_FE_INT, in __serial_lpc32xx_rx() 294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); in __serial_lpc32xx_tx() 306 writel((u32) xmit->buf[xmit->tail], in __serial_lpc32xx_tx() 321 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); in __serial_lpc32xx_tx() 338 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt() 345 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt() 349 writel(LPC32XX_HSU_RX_OE_INT, in serial_lpc32xx_interrupt() 362 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); in serial_lpc32xx_interrupt() 403 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); in serial_lpc32xx_stop_tx() [all …]
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D | netx-serial.c | 122 writel(val & ~CR_TIE, port->membase + UART_CR); in netx_stop_tx() 129 writel(val & ~CR_RIE, port->membase + UART_CR); in netx_stop_rx() 136 writel(val | CR_MSIE, port->membase + UART_CR); in netx_enable_ms() 144 writel(port->x_char, port->membase + UART_DR); in netx_transmit_buffer() 158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); in netx_transmit_buffer() 172 writel( in netx_start_tx() 209 writel(0, port->membase + UART_SR); in netx_rxint() 264 writel(0, port->membase + UART_IIR); in netx_int() 289 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR); in netx_set_mctrl() 303 writel(line_cr, port->membase + UART_LINE_CR); in netx_break_ctl() [all …]
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D | imx.c | 305 writel(ucr->ucr1, port->membase + UCR1); in imx_port_ucrs_restore() 306 writel(ucr->ucr2, port->membase + UCR2); in imx_port_ucrs_restore() 307 writel(ucr->ucr3, port->membase + UCR3); in imx_port_ucrs_restore() 372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); in imx_stop_tx() 382 writel(temp, port->membase + UCR2); in imx_stop_tx() 386 writel(temp, port->membase + UCR4); in imx_stop_tx() 408 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); in imx_stop_rx() 412 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); in imx_stop_rx() 433 writel(sport->port.x_char, sport->port.membase + URTX0); in imx_transmit_buffer() 453 writel(temp, sport->port.membase + UCR1); in imx_transmit_buffer() [all …]
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D | mxs-auart.c | 302 writel(s->port.x_char, in mxs_auart_tx_chars() 309 writel(xmit->buf[xmit->tail], in mxs_auart_tx_chars() 319 writel(AUART_INTR_TXIEN, in mxs_auart_tx_chars() 322 writel(AUART_INTR_TXIEN, in mxs_auart_tx_chars() 371 writel(stat, s->port.membase + AUART_STAT); in mxs_auart_rx_char() 385 writel(stat, s->port.membase + AUART_STAT); in mxs_auart_rx_chars() 431 writel(ctrl, u->membase + AUART_CTRL2); in mxs_auart_set_mctrl() 546 writel(stat, s->port.membase + AUART_STAT); in dma_rx_callback() 609 writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR, in mxs_auart_dma_exit() 764 writel(ctrl, u->membase + AUART_LINECTRL); in mxs_auart_settermios() [all …]
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/linux-4.4.14/sound/soc/kirkwood/ |
D | kirkwood-i2s.c | 68 writel(value, priv->io+KIRKWOOD_I2S_PLAYCTL); in kirkwood_i2s_set_fmt() 73 writel(value, priv->io+KIRKWOOD_I2S_RECCTL); in kirkwood_i2s_set_fmt() 95 writel(value, io + KIRKWOOD_DCO_CTL); in kirkwood_set_dco() 127 writel(clks_ctrl, priv->io + KIRKWOOD_CLOCKS_CTRL); in kirkwood_set_rate() 220 writel(i2s_value, priv->io+i2s_reg); in kirkwood_i2s_hw_params() 272 writel(value, priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger() 278 writel(value, priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_play_trigger() 282 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger() 289 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); in kirkwood_i2s_play_trigger() 293 writel(value, priv->io + KIRKWOOD_INT_MASK); in kirkwood_i2s_play_trigger() [all …]
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D | kirkwood-dma.c | 57 writel(cause, priv->io + KIRKWOOD_ERR_CAUSE); in kirkwood_dma_irq() 69 writel(status, priv->io + KIRKWOOD_INT_CAUSE); in kirkwood_dma_irq() 88 writel(0, base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win)); in kirkwood_dma_conf_mbus_windows() 89 writel(0, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); in kirkwood_dma_conf_mbus_windows() 95 writel(cs->base & 0xffff0000, in kirkwood_dma_conf_mbus_windows() 97 writel(((cs->size - 1) & 0xffff0000) | in kirkwood_dma_conf_mbus_windows() 145 writel((unsigned int)-1, priv->io + KIRKWOOD_ERR_MASK); in kirkwood_dma_open() 180 writel(0, priv->io + KIRKWOOD_ERR_MASK); in kirkwood_dma_close() 216 writel(count, priv->io + KIRKWOOD_PLAY_BYTE_INT_COUNT); in kirkwood_dma_prepare() 217 writel(runtime->dma_addr, priv->io + KIRKWOOD_PLAY_BUF_ADDR); in kirkwood_dma_prepare() [all …]
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/linux-4.4.14/drivers/virtio/ |
D | virtio_mmio.c | 121 writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features() 125 writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features() 145 writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features() 146 writel((u32)(vdev->features >> 32), in vm_finalize_features() 149 writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features() 150 writel((u32)vdev->features, in vm_finalize_features() 228 writel(le32_to_cpu(l), base + offset); in vm_set() 232 writel(le32_to_cpu(l), base + offset); in vm_set() 234 writel(le32_to_cpu(l), base + offset + sizeof l); in vm_set() 265 writel(status, vm_dev->base + VIRTIO_MMIO_STATUS); in vm_set_status() [all …]
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/linux-4.4.14/drivers/memstick/host/ |
D | tifm_ms.c | 142 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data() 144 writel(host->io_word, sock->addr + SOCK_MS_DATA); in tifm_ms_write_data() 157 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), in tifm_ms_write_data() 238 writel(TIFM_MS_SYS_FDIR in tifm_ms_transfer_data() 241 writel(host->io_word, sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data() 243 writel(TIFM_MS_SYS_FDIR in tifm_ms_transfer_data() 246 writel(0, sock->addr + SOCK_MS_DATA); in tifm_ms_transfer_data() 279 writel(TIFM_FIFO_INT_SETALL, in tifm_ms_issue_cmd() 281 writel(TIFM_FIFO_ENABLE, in tifm_ms_issue_cmd() 294 writel(ilog2(data_len) - 2, in tifm_ms_issue_cmd() [all …]
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D | jmb38x_ms.c | 237 writel(host->io_word[0], host->addr + DATA); in jmb38x_ms_write_data() 357 writel(host->io_word[0], host->addr + TPC_P0); in jmb38x_ms_transfer_data() 358 writel(host->io_word[1], host->addr + TPC_P1); in jmb38x_ms_transfer_data() 360 writel(host->io_word[0], host->addr + DATA); in jmb38x_ms_transfer_data() 430 writel(sg_dma_address(&host->req->sg), in jmb38x_ms_issue_cmd() 432 writel(((1 << 16) & BLOCK_COUNT_MASK) in jmb38x_ms_issue_cmd() 435 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); in jmb38x_ms_issue_cmd() 437 writel(((1 << 16) & BLOCK_COUNT_MASK) in jmb38x_ms_issue_cmd() 445 writel(t_val, host->addr + INT_STATUS_ENABLE); in jmb38x_ms_issue_cmd() 446 writel(t_val, host->addr + INT_SIGNAL_ENABLE); in jmb38x_ms_issue_cmd() [all …]
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/linux-4.4.14/drivers/net/ethernet/moxa/ |
D | moxart_ether.c | 36 writel(value, priv->base + reg); in moxart_emac_write() 88 writel(SW_RST, priv->base + REG_MAC_CTRL); in moxart_mac_reset() 92 writel(0, priv->base + REG_INTERRUPT_MASK); in moxart_mac_reset() 101 writel(0x00001010, priv->base + REG_INT_TIMER_CTRL); in moxart_mac_enable() 102 writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL); in moxart_mac_enable() 103 writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL); in moxart_mac_enable() 106 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); in moxart_mac_enable() 109 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); in moxart_mac_enable() 124 writel(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1); in moxart_mac_setup_desc_ring() 132 writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); in moxart_mac_setup_desc_ring() [all …]
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/linux-4.4.14/drivers/power/reset/ |
D | qnap-poweroff.c | 65 writel(0x83, UART1_REG(LCR)); in qnap_power_off() 66 writel(divisor & 0xff, UART1_REG(DLL)); in qnap_power_off() 67 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); in qnap_power_off() 68 writel(0x03, UART1_REG(LCR)); in qnap_power_off() 69 writel(0x00, UART1_REG(IER)); in qnap_power_off() 70 writel(0x00, UART1_REG(FCR)); in qnap_power_off() 71 writel(0x00, UART1_REG(MCR)); in qnap_power_off() 74 writel(cfg->cmd, UART1_REG(TX)); in qnap_power_off()
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/linux-4.4.14/drivers/net/ethernet/amd/ |
D | amd8111e.c | 123 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | in amd8111e_read_phy() 152 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | in amd8111e_write_phy() 392 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce() 393 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, in amd8111e_set_coalesce() 406 writel(VAL0|STINTEN,mmio+INTEN0); in amd8111e_set_coalesce() 407 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, in amd8111e_set_coalesce() 412 writel(0,mmio+STVAL); in amd8111e_set_coalesce() 413 writel(STINTEN, mmio+INTEN0); in amd8111e_set_coalesce() 414 writel(0, mmio +DLY_INT_B); in amd8111e_set_coalesce() 415 writel(0, mmio+DLY_INT_A); in amd8111e_set_coalesce() [all …]
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/linux-4.4.14/drivers/net/ethernet/alteon/ |
D | acenic.c | 614 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); in acenic_remove_one() 616 writel(readl(®s->CpuBCtrl) | CPU_HALT, ®s->CpuBCtrl); in acenic_remove_one() 621 writel(1, ®s->Mb0Lo); in acenic_remove_one() 853 writel(*(u32 *)(cmd), ®s->CmdRng[idx]); in ace_issue_cmd() 856 writel(idx, ®s->CmdPrd); in ace_issue_cmd() 883 writel(HW_RESET | (HW_RESET << 24), ®s->HostCtrl); in ace_init() 895 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), in ace_init() 898 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), in ace_init() 906 writel(readl(®s->CpuCtrl) | CPU_HALT, ®s->CpuCtrl); in ace_init() 908 writel(0, ®s->Mb0Lo); in ace_init() [all …]
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/linux-4.4.14/drivers/net/ethernet/nxp/ |
D | lpc_eth.c | 454 writel(tmp, LPC_ENET_SA2(pldat->net_base)); in __lpc_set_mac() 456 writel(tmp, LPC_ENET_SA1(pldat->net_base)); in __lpc_set_mac() 458 writel(tmp, LPC_ENET_SA0(pldat->net_base)); in __lpc_set_mac() 494 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); in __lpc_params_setup() 497 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); in __lpc_params_setup() 498 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base)); in __lpc_params_setup() 502 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); in __lpc_params_setup() 505 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); in __lpc_params_setup() 506 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base)); in __lpc_params_setup() 510 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base)); in __lpc_params_setup() [all …]
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/linux-4.4.14/arch/arm/mach-mvebu/ |
D | pm.c | 54 writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); in mvebu_pm_powerdown() 61 writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); in mvebu_pm_powerdown() 123 writel(BOOT_MAGIC_WORD, store_addr++); in mvebu_pm_store_armadaxp_bootinfo() 124 writel(resume_pc, store_addr++); in mvebu_pm_store_armadaxp_bootinfo() 132 writel(MBUS_WINDOW_12_CTRL, store_addr++); in mvebu_pm_store_armadaxp_bootinfo() 133 writel(0x0, store_addr++); in mvebu_pm_store_armadaxp_bootinfo() 139 writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++); in mvebu_pm_store_armadaxp_bootinfo() 140 writel(mvebu_internal_reg_base(), store_addr++); in mvebu_pm_store_armadaxp_bootinfo() 149 writel(BOOT_MAGIC_LIST_END, store_addr); in mvebu_pm_store_armadaxp_bootinfo()
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D | pmsu.c | 116 writel(virt_to_phys(boot_addr), pmsu_mp_base + in mvebu_pmsu_set_cpu_boot_addr() 218 writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); in mvebu_v7_pmsu_enable_l2_powerdown_onidle() 248 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_prepare() 257 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_prepare() 263 writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu)); in mvebu_v7_pmsu_idle_prepare() 352 writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu)); in mvebu_v7_pmsu_idle_exit() 360 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu)); in mvebu_v7_pmsu_idle_exit() 456 writel(reg, mpsoc_base + MPCORE_RESET_CTL); in armada_38x_cpuidle_init() 464 writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY); in armada_38x_cpuidle_init() 551 writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu)); in mvebu_pmsu_dfs_request_local() [all …]
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/linux-4.4.14/drivers/usb/gadget/udc/ |
D | net2280.c | 179 writel(tmp, &ep->dev->regs->pciirqenb0); in enable_pciirqenb() 246 writel(BIT(FIFO_FLUSH), &ep->regs->ep_stat); in net2280_enable() 267 writel(BIT(CLEAR_NAK_OUT_PACKETS_MODE), in net2280_enable() 310 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); in net2280_enable() 315 writel(BIT(CLEAR_NAK_OUT_PACKETS) | in net2280_enable() 321 writel(tmp, &ep->cfg->ep_cfg); in net2280_enable() 331 writel(tmp, &ep->regs->ep_irqenb); in net2280_enable() 335 writel(tmp, &dev->regs->pciirqenb1); in net2280_enable() 343 writel(tmp, &ep->regs->ep_irqenb); in net2280_enable() 396 writel(0, &ep->dma->dmactl); in ep_reset_228x() [all …]
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D | net2280.h | 30 writel(index, ®s->idxaddr); in get_idx_reg() 38 writel(index, ®s->idxaddr); in set_idx_reg() 39 writel(value, ®s->idxdata); in set_idx_reg() 120 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | in allow_status() 134 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp); in allow_status_338x() 196 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | in set_halt() 206 writel(BIT(CLEAR_ENDPOINT_HALT) | in clear_halt() 258 writel(BIT(GPIO3_LED_SELECT) | in net2280_led_init() 287 writel(val, &dev->regs->gpioctl); in net2280_led_speed() 300 writel(val, &dev->regs->gpioctl); in net2280_led_active() [all …]
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D | amd5536udc.c | 283 writel(tmp, &dev->regs->irqmsk); in udc_mask_unused_interrupts() 286 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk); in udc_mask_unused_interrupts() 303 writel(tmp, &dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts() 324 writel(tmp, &dev->regs->irqmsk); in udc_enable_dev_setup_interrupts() 401 writel(tmp, &dev->ep[ep->num].regs->ctl); in udc_ep_enable() 408 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable() 424 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable() 432 writel(tmp, &ep->regs->ctl); in udc_ep_enable() 443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable() 472 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable() [all …]
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D | s3c-hsudc.c | 184 writel(ep_addr, hsudc->regs + S3C_IR); in set_index() 189 writel(readl(ptr) | val, ptr); in __orr32() 197 writel(cfg, S3C2443_PWRCFG); in s3c_hsudc_init_phy() 201 writel(cfg, S3C2443_URSTCON); in s3c_hsudc_init_phy() 206 writel(cfg, S3C2443_URSTCON); in s3c_hsudc_init_phy() 211 writel(cfg, S3C2443_PHYCTRL); in s3c_hsudc_init_phy() 218 writel(cfg, S3C2443_PHYPWR); in s3c_hsudc_init_phy() 223 writel(cfg, S3C2443_UCLKCON); in s3c_hsudc_init_phy() 231 writel(cfg, S3C2443_PWRCFG); in s3c_hsudc_uninit_phy() 233 writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR); in s3c_hsudc_uninit_phy() [all …]
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/linux-4.4.14/drivers/staging/comedi/drivers/ |
D | rtd520.c | 474 writel(0, dev->mmio + LAS0_CGT_CLEAR); in rtd_load_channelgain_list() 475 writel(1, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list() 477 writel(rtd_convert_chan_gain(dev, list[ii], ii), in rtd_load_channelgain_list() 481 writel(0, dev->mmio + LAS0_CGT_ENABLE); in rtd_load_channelgain_list() 482 writel(rtd_convert_chan_gain(dev, list[0], 0), in rtd_load_channelgain_list() 498 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth() 501 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd520_probe_fifo_depth() 518 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd520_probe_fifo_depth() 551 writel(0, dev->mmio + LAS0_ADC_FIFO_CLEAR); in rtd_ai_rinsn() 557 writel(0, dev->mmio + LAS0_ADC_CONVERSION); in rtd_ai_rinsn() [all …]
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D | gsc_hpdi.c | 212 writel(hpdi_intr_status, dev->mmio + INTERRUPT_STATUS_REG); in gsc_hpdi_interrupt() 241 writel(plx_bits, devpriv->plx9080_mmio + PLX_DBR_OUT_REG); in gsc_hpdi_interrupt() 278 writel(0, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cancel() 279 writel(0, dev->mmio + INTERRUPT_CONTROL_REG); in gsc_hpdi_cancel() 298 writel(RX_FIFO_RESET_BIT, dev->mmio + BOARD_CONTROL_REG); in gsc_hpdi_cmd() 310 writel(0, devpriv->plx9080_mmio + PLX_DMA0_TRANSFER_SIZE_REG); in gsc_hpdi_cmd() 311 writel(0, devpriv->plx9080_mmio + PLX_DMA0_PCI_ADDRESS_REG); in gsc_hpdi_cmd() 312 writel(0, devpriv->plx9080_mmio + PLX_DMA0_LOCAL_ADDRESS_REG); in gsc_hpdi_cmd() 317 writel(bits, devpriv->plx9080_mmio + PLX_DMA0_DESCRIPTOR_REG); in gsc_hpdi_cmd() 331 writel(RX_UNDERRUN_BIT | RX_OVERRUN_BIT, dev->mmio + BOARD_STATUS_REG); in gsc_hpdi_cmd() [all …]
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D | s626.c | 113 writel(val, dev->mmio + reg); in s626_mc_enable() 119 writel(cmd << 16, dev->mmio + reg); in s626_mc_disable() 185 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_read() 200 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_write() 201 writel(wdata, dev->mmio + S626_P_DEBIAD); in s626_debi_write() 218 writel(S626_DEBI_CMD_RDWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace() 221 writel(S626_DEBI_CMD_WRWORD | addr, dev->mmio + S626_P_DEBICMD); in s626_debi_replace() 225 writel(val & 0xffff, dev->mmio + S626_P_DEBIAD); in s626_debi_replace() 250 writel(val, dev->mmio + S626_P_I2CCTRL); in s626_i2c_handshake() 400 writel(S626_ISR_AFOU, dev->mmio + S626_P_ISR); in s626_send_dac() [all …]
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D | mite.c | 122 writel(0, mite->mite_io_addr + MITE_IODWBSR); in mite_setup2() 125 writel(mite->daq_phys_addr | WENAB | in mite_setup2() 128 writel(0, mite->mite_io_addr + MITE_IODWCR_1); in mite_setup2() 130 writel(mite->daq_phys_addr | WENAB, in mite_setup2() 143 writel(unknown_dma_burst_bits, in mite_setup2() 156 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); in mite_setup2() 158 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | in mite_setup2() 258 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | in mite_release_channel() 286 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); in mite_dma_arm() 357 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); in mite_prep_dma() [all …]
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/linux-4.4.14/drivers/media/platform/sti/c8sectpfe/ |
D | c8sectpfe-core.c | 130 writel(channel->back_buffer_busaddr, channel->irec + in channel_swdemux_tsklet() 133 writel(wp, channel->irec + DMA_PRDS_BUSWP_TP(0)); in channel_swdemux_tsklet() 186 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); in c8sectpfe_start_feed() 215 writel(channel->fifo, in c8sectpfe_start_feed() 217 writel(channel->fifo + FIFO_LEN - 1, in c8sectpfe_start_feed() 220 writel(channel->fifo, in c8sectpfe_start_feed() 222 writel(channel->fifo, in c8sectpfe_start_feed() 227 writel(channel->back_buffer_busaddr, channel->irec + in c8sectpfe_start_feed() 231 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0)); in c8sectpfe_start_feed() 233 writel(channel->back_buffer_busaddr, channel->irec + in c8sectpfe_start_feed() [all …]
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/linux-4.4.14/drivers/vlynq/ |
D | vlynq.c | 124 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, in vlynq_reset() 131 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, in vlynq_reset() 148 writel(val, &dev->remote->int_device[virq >> 2]); in vlynq_irq_unmask() 161 writel(val, &dev->remote->int_device[virq >> 2]); in vlynq_irq_mask() 191 writel(val, &dev->remote->int_device[virq >> 2]); in vlynq_irq_type() 202 writel(status, &dev->local->status); in vlynq_local_ack() 212 writel(status, &dev->remote->status); in vlynq_remote_ack() 222 writel(status, &dev->local->int_status); in vlynq_irq() 271 writel(readl(&dev->local->status), &dev->local->status); in vlynq_setup_irq() 272 writel(readl(&dev->remote->status), &dev->remote->status); in vlynq_setup_irq() [all …]
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/linux-4.4.14/arch/arm/mach-socfpga/ |
D | platsmp.c | 38 writel(RSTMGR_MPUMODRST_CPU1, in socfpga_boot_secondary() 43 writel(virt_to_phys(secondary_startup), in socfpga_boot_secondary() 51 writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST); in socfpga_boot_secondary() 62 writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + in socfpga_a10_boot_secondary() 66 writel(virt_to_phys(secondary_startup), in socfpga_a10_boot_secondary() 74 writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST); in socfpga_a10_boot_secondary()
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/linux-4.4.14/drivers/net/ethernet/agere/ |
D | et131x.c | 755 writel(csr, &adapter->regs->rxdma.csr); in et131x_rx_dma_enable() 773 writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE, in et131x_rx_dma_disable() 791 writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT), in et131x_tx_dma_enable() 815 writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | in et1310_config_mac_regs1() 823 writel(ipg, ¯egs->ipg); in et1310_config_mac_regs1() 827 writel(0x00A1F037, ¯egs->hfdp); in et1310_config_mac_regs1() 830 writel(0, ¯egs->if_ctrl); in et1310_config_mac_regs1() 832 writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg); in et1310_config_mac_regs1() 847 writel(station1, ¯egs->station_addr_1); in et1310_config_mac_regs1() 848 writel(station2, ¯egs->station_addr_2); in et1310_config_mac_regs1() [all …]
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/linux-4.4.14/drivers/watchdog/ |
D | qcom-wdt.c | 45 writel(0, wdt->base + WDT_EN); in qcom_wdt_start() 46 writel(1, wdt->base + WDT_RST); in qcom_wdt_start() 47 writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME); in qcom_wdt_start() 48 writel(1, wdt->base + WDT_EN); in qcom_wdt_start() 56 writel(0, wdt->base + WDT_EN); in qcom_wdt_stop() 64 writel(1, wdt->base + WDT_RST); in qcom_wdt_ping() 102 writel(0, wdt->base + WDT_EN); in qcom_wdt_restart() 103 writel(1, wdt->base + WDT_RST); in qcom_wdt_restart() 104 writel(timeout, wdt->base + WDT_BITE_TIME); in qcom_wdt_restart() 105 writel(1, wdt->base + WDT_EN); in qcom_wdt_restart()
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D | pnx4008_wdt.c | 90 writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); in pnx4008_wdt_start() 95 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); in pnx4008_wdt_start() 97 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); in pnx4008_wdt_start() 99 writel(MATCH_INT, WDTIM_INT(wdt_base)); in pnx4008_wdt_start() 101 writel(0xFFFF, WDTIM_PULSE(wdt_base)); in pnx4008_wdt_start() 102 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); in pnx4008_wdt_start() 104 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); in pnx4008_wdt_start() 114 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ in pnx4008_wdt_stop()
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D | moxart_wdt.c | 43 writel(1, moxart_wdt->base + REG_COUNT); in moxart_restart_handle() 44 writel(0x5ab9, moxart_wdt->base + REG_MODE); in moxart_restart_handle() 45 writel(0x03, moxart_wdt->base + REG_ENABLE); in moxart_restart_handle() 54 writel(0, moxart_wdt->base + REG_ENABLE); in moxart_wdt_stop() 63 writel(moxart_wdt->clock_frequency * wdt_dev->timeout, in moxart_wdt_start() 65 writel(0x5ab9, moxart_wdt->base + REG_MODE); in moxart_wdt_start() 66 writel(0x03, moxart_wdt->base + REG_ENABLE); in moxart_wdt_start()
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/linux-4.4.14/drivers/input/touchscreen/ |
D | imx6ul_tsc.c | 111 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init() 116 writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); in imx6ul_adc_init() 121 writel(adc_gc, tsc->adc_regs + REG_ADC_GC); in imx6ul_adc_init() 139 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); in imx6ul_adc_init() 154 writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); in imx6ul_tsc_channel_config() 157 writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); in imx6ul_tsc_channel_config() 160 writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); in imx6ul_tsc_channel_config() 163 writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); in imx6ul_tsc_channel_config() 166 writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); in imx6ul_tsc_channel_config() 181 writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING); in imx6ul_tsc_set() [all …]
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/linux-4.4.14/drivers/net/ethernet/natsemi/ |
D | ns83820.c | 469 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) 477 writel(dev->rx_info.phy_descs + in kick_rx() 634 writel(readl(dev->base + TXCFG) in phy_intr() 637 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr() 640 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, in phy_intr() 651 writel((readl(dev->base + TXCFG) in phy_intr() 654 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, in phy_intr() 657 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, in phy_intr() 677 writel(readl(dev->base + TXCFG) in phy_intr() 680 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr() [all …]
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/linux-4.4.14/arch/arm/mach-highbank/ |
D | sysregs.h | 58 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_suspend() 64 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_shutdown() 70 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_soft_reset() 76 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_set_pwr_hard_reset() 82 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); in highbank_clear_pwr_request()
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/linux-4.4.14/drivers/input/keyboard/ |
D | bcm-keypad.c | 112 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); in bcm_kp_report_keys() 153 writel(kp->kpior, kp->base + KPIOR_OFFSET); in bcm_kp_start() 155 writel(kp->imr0_val, kp->base + KPIMR0_OFFSET); in bcm_kp_start() 156 writel(kp->imr1_val, kp->base + KPIMR1_OFFSET); in bcm_kp_start() 158 writel(kp->kpemr, kp->base + KPEMR0_OFFSET); in bcm_kp_start() 159 writel(kp->kpemr, kp->base + KPEMR1_OFFSET); in bcm_kp_start() 160 writel(kp->kpemr, kp->base + KPEMR2_OFFSET); in bcm_kp_start() 161 writel(kp->kpemr, kp->base + KPEMR3_OFFSET); in bcm_kp_start() 163 writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET); in bcm_kp_start() 164 writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET); in bcm_kp_start() [all …]
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/linux-4.4.14/drivers/media/rc/ |
D | st_rc.c | 115 writel(IRB_RX_OVERRUN_INT, in st_rc_rx_interrupt() 153 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); in st_rc_rx_interrupt() 174 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); in st_rc_hardware_init() 177 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); in st_rc_hardware_init() 187 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); in st_rc_hardware_init() 204 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); in st_rc_open() 205 writel(0x01, dev->rx_base + IRB_RX_EN); in st_rc_open() 215 writel(0x00, dev->rx_base + IRB_RX_EN); in st_rc_close() 216 writel(0x00, dev->rx_base + IRB_RX_INT_EN); in st_rc_close() 349 writel(0x00, rc_dev->rx_base + IRB_RX_EN); in st_rc_suspend() [all …]
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/linux-4.4.14/drivers/scsi/arcmsr/ |
D | arcmsr_hba.c | 250 …writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);… in arcmsr_remap_pciregion() 343 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, in arcmsr_hbaA_wait_msgint_ready() 361 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, in arcmsr_hbaB_wait_msgint_ready() 363 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, in arcmsr_hbaB_wait_msgint_ready() 381 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, in arcmsr_hbaC_wait_msgint_ready() 399 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, in arcmsr_hbaD_wait_msgint_ready() 412 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); in arcmsr_hbaA_flush_cache() 428 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell); in arcmsr_hbaB_flush_cache() 444 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, ®->inbound_msgaddr0); in arcmsr_hbaC_flush_cache() 445 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, ®->inbound_doorbell); in arcmsr_hbaC_flush_cache() [all …]
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/linux-4.4.14/drivers/clk/mediatek/ |
D | clk-pll.c | 105 writel(val, pll->pd_addr); in mtk_pll_set_rate_regs() 113 writel(val, pll->pcw_addr); in mtk_pll_set_rate_regs() 120 writel(con1, pll->base_addr + REG_CON1); in mtk_pll_set_rate_regs() 122 writel(con1 + 1, pll->tuner_addr); in mtk_pll_set_rate_regs() 219 writel(r, pll->pwr_addr); in mtk_pll_prepare() 223 writel(r, pll->pwr_addr); in mtk_pll_prepare() 228 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare() 232 writel(r, pll->tuner_addr); in mtk_pll_prepare() 240 writel(r, pll->base_addr + REG_CON0); in mtk_pll_prepare() 254 writel(r, pll->base_addr + REG_CON0); in mtk_pll_unprepare() [all …]
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/linux-4.4.14/arch/arm/mach-ep93xx/ |
D | timer-ep93xx.c | 79 writel(tmode, EP93XX_TIMER3_CONTROL); in ep93xx_clkevt_set_next_event() 82 writel(next, EP93XX_TIMER3_LOAD); in ep93xx_clkevt_set_next_event() 83 writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, in ep93xx_clkevt_set_next_event() 92 writel(0, EP93XX_TIMER3_CONTROL); in ep93xx_clkevt_shutdown() 112 writel(1, EP93XX_TIMER3_CLEAR); in ep93xx_timer_interrupt() 129 writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, in ep93xx_timer_init()
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/linux-4.4.14/arch/mips/jz4740/ |
D | timer.c | 28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_enable_watchdog() 34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_disable_watchdog() 46 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_init() 49 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_init()
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/linux-4.4.14/include/linux/ |
D | goldfish.h | 9 writel((u32)(unsigned long)ptr, portl); in gf_write_ptr() 11 writel((unsigned long)ptr >> 32, porth); in gf_write_ptr() 19 writel((u32)addr, portl); in gf_write_dma_addr() 21 writel(addr >> 32, porth); in gf_write_dma_addr()
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/linux-4.4.14/arch/sparc/kernel/ |
D | ebus.c | 54 writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR); in __ebus_dma_reset() 77 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq() 117 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register() 137 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable() 143 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable() 165 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_unregister() 193 writel(len, p->regs + EBDMA_COUNT); in ebus_dma_request() 194 writel(bus_addr, p->regs + EBDMA_ADDR); in ebus_dma_request() 222 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_prepare() 253 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_enable()
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/linux-4.4.14/drivers/usb/chipidea/ |
D | usbmisc_imx.c | 114 writel(val, usbmisc->base); in usbmisc_imx25_init() 123 writel(val, usbmisc->base); in usbmisc_imx25_init() 146 writel(val | MX25_BM_EXTERNAL_VBUS_DIVIDER, reg); in usbmisc_imx25_post() 179 writel(val, usbmisc->base); in usbmisc_imx27_init() 199 writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); in usbmisc_imx53_init() 222 writel(val, reg); in usbmisc_imx53_init() 246 writel(val, usbmisc->base + data->index * 4); in usbmisc_imx6q_set_wakeup() 251 writel(val, usbmisc->base + data->index * 4); in usbmisc_imx6q_set_wakeup() 271 writel(reg | MX6_BM_OVER_CUR_DIS, in usbmisc_imx6q_init() 277 writel(reg | MX6_BM_NON_BURST_SETTING, in usbmisc_imx6q_init() [all …]
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/linux-4.4.14/sound/arm/ |
D | aaci.c | 54 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec() 87 writel(val << 4, aaci->base + AACI_SL2TX); in aaci_ac97_write() 88 writel(reg << 12, aaci->base + AACI_SL1TX); in aaci_ac97_write() 126 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); in aaci_ac97_read() 203 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); in aaci_fifo_irq() 208 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); in aaci_fifo_irq() 218 writel(0, aacirun->base + AACI_IE); in aaci_fifo_irq() 268 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); in aaci_fifo_irq() 278 writel(0, aacirun->base + AACI_IE); in aaci_fifo_irq() 579 writel(ie, aacirun->base + AACI_IE); in aaci_pcm_playback_stop() [all …]
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/linux-4.4.14/drivers/net/ethernet/nvidia/ |
D | forcedeth.c | 1006 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings() 1008 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysA… in setup_hw_rings() 1011 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr); in setup_hw_rings() 1012 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh); in setup_hw_rings() 1015 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPh… in setup_hw_rings() 1016 …writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingP… in setup_hw_rings() 1063 writel(powerstate, base + NvRegPowerState2); in nv_txrx_gate() 1104 writel(mask, base + NvRegIrqMask); in nv_enable_hw_interrupts() 1113 writel(mask, base + NvRegIrqMask); in nv_disable_hw_interrupts() 1116 writel(0, base + NvRegMSIIrqMask); in nv_disable_hw_interrupts() [all …]
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/linux-4.4.14/drivers/mfd/ |
D | db8500-prcmu.c | 584 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR); in db8500_prcmu_enable_dsipll() 586 writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR); in db8500_prcmu_enable_dsipll() 589 writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ); in db8500_prcmu_enable_dsipll() 590 writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL); in db8500_prcmu_enable_dsipll() 592 writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); in db8500_prcmu_enable_dsipll() 595 writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE); in db8500_prcmu_enable_dsipll() 597 writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET); in db8500_prcmu_enable_dsipll() 605 writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET); in db8500_prcmu_enable_dsipll() 612 writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE); in db8500_prcmu_disable_dsipll() 614 writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV); in db8500_prcmu_disable_dsipll() [all …]
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/linux-4.4.14/arch/mips/include/asm/mach-jz4740/ |
D | timer.h | 66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); in jz4740_timer_stop() 71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); in jz4740_timer_start() 111 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); in jz4740_timer_ack_full() 116 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); in jz4740_timer_irq_full_enable() 117 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); in jz4740_timer_irq_full_enable() 122 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); in jz4740_timer_irq_full_disable()
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/linux-4.4.14/arch/arm/mach-dove/ |
D | mpp.c | 77 writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_nfc() 114 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_cfg_au1() 115 writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); in dove_mpp_cfg_au1() 116 writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); in dove_mpp_cfg_au1() 117 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); in dove_mpp_cfg_au1() 143 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); in dove_mpp_conf_grp()
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/linux-4.4.14/drivers/clk/ |
D | clk-highbank.c | 63 writel(reg, hbclk->reg); in clk_pll_prepare() 80 writel(reg, hbclk->reg); in clk_pll_unprepare() 90 writel(reg, hbclk->reg); in clk_pll_enable() 102 writel(reg, hbclk->reg); in clk_pll_disable() 170 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); in clk_pll_set_rate() 172 writel(reg | HB_PLL_RESET, hbclk->reg); in clk_pll_set_rate() 175 writel(reg | HB_PLL_RESET, hbclk->reg); in clk_pll_set_rate() 176 writel(reg, hbclk->reg); in clk_pll_set_rate() 185 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); in clk_pll_set_rate() 188 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); in clk_pll_set_rate() [all …]
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/linux-4.4.14/drivers/net/ethernet/freescale/ |
D | fec_ptp.c | 136 writel(FEC_T_TF_MASK, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps() 145 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps() 160 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_enable_pps() 192 writel(val, fep->hwp + FEC_TCCR(fep->pps_channel)); in fec_ptp_enable_pps() 200 writel(val, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_enable_pps() 208 writel(val, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps() 213 writel(fep->next_counter, fep->hwp + FEC_TCCR(fep->pps_channel)); in fec_ptp_enable_pps() 216 writel(0, fep->hwp + FEC_TCSR(fep->pps_channel)); in fec_ptp_enable_pps() 243 writel(tempval, fep->hwp + FEC_ATIME_CTRL); in fec_ptp_read() 271 writel(inc << FEC_T_INC_OFFSET, fep->hwp + FEC_ATIME_INC); in fec_ptp_start_cyclecounter() [all …]
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/linux-4.4.14/drivers/mtd/nand/ |
D | sh_flctl.c | 86 writel(flctl->flintdmacr_base | AC1CLR | AC0CLR, FLINTDMACR(flctl)); in empty_fifo() 87 writel(flctl->flintdmacr_base, FLINTDMACR(flctl)); in empty_fifo() 211 writel(addr2, FLADR2(flctl)); in set_addr() 220 writel(addr, FLADR(flctl)); in set_addr() 299 writel(0, FL4ECCCR(flctl)); in wait_recfifo_ready() 325 writel(0, FL4ECCCR(flctl)); in wait_recfifo_ready() 375 writel(reg, FLINTDMACR(flctl)); in flctl_dma_fifo0_transfer() 403 writel(reg, FLINTDMACR(flctl)); in flctl_dma_fifo0_transfer() 473 writel(cpu_to_be32(buf[i]), FLDTFIFO(flctl)); in write_fiforeg() 496 writel(buf[i], FLECFIFO(flctl)); in write_ec_fiforeg() [all …]
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/linux-4.4.14/drivers/net/phy/ |
D | mdio-sun4i.c | 46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_read() 48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read() 59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_read() 73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); in sun4i_mdio_write() 75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write() 86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); in sun4i_mdio_write() 88 writel(value, data->membase + EMAC_MAC_MWTD_REG); in sun4i_mdio_write()
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/linux-4.4.14/drivers/input/serio/ |
D | sun4i-ps2.c | 117 writel(rval, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt() 124 writel(rval, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt() 133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); in sun4i_ps2_interrupt() 134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); in sun4i_ps2_interrupt() 153 writel(rval, drvdata->reg_base + PS2_REG_LCTL); in sun4i_ps2_open() 160 writel(rval, drvdata->reg_base + PS2_REG_FCTL); in sun4i_ps2_open() 167 writel(rval, drvdata->reg_base + PS2_REG_CLKDR); in sun4i_ps2_open() 174 writel(rval, drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_open() 187 writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL); in sun4i_ps2_close() 199 writel(val, drvdata->reg_base + PS2_REG_DATA); in sun4i_ps2_write() [all …]
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/linux-4.4.14/arch/arm/mach-rockchip/ |
D | rockchip.c | 48 writel(0, reg_base + 0x30); in rockchip_timer_init() 49 writel(0xffffffff, reg_base + 0x20); in rockchip_timer_init() 50 writel(0xffffffff, reg_base + 0x24); in rockchip_timer_init() 51 writel(1, reg_base + 0x30); in rockchip_timer_init()
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/linux-4.4.14/drivers/net/ethernet/calxeda/ |
D | xgmac.c | 519 writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR); in xgmac_dma_flush_tx_fifo() 602 writel(value, ioaddr + XGMAC_CONTROL); in xgmac_mac_enable() 606 writel(value, ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_enable() 613 writel(value, ioaddr + XGMAC_DMA_CONTROL); in xgmac_mac_disable() 617 writel(value, ioaddr + XGMAC_CONTROL); in xgmac_mac_disable() 627 writel(data, ioaddr + XGMAC_ADDR_HIGH(num)); in xgmac_set_mac_addr() 629 writel(data, ioaddr + XGMAC_ADDR_LOW(num)); in xgmac_set_mac_addr() 631 writel(0, ioaddr + XGMAC_ADDR_HIGH(num)); in xgmac_set_mac_addr() 632 writel(0, ioaddr + XGMAC_ADDR_LOW(num)); in xgmac_set_mac_addr() 671 writel(flow, priv->base + XGMAC_FLOW_CTRL); in xgmac_set_flow_ctrl() [all …]
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/linux-4.4.14/drivers/usb/early/ |
D | ehci-dbgp.c | 181 writel(ctrl | DBGP_DONE, &ehci_debug->control); in dbgp_wait_until_complete() 206 writel(ctrl | DBGP_GO, &ehci_debug->control); in dbgp_wait_until_done() 252 writel(lo, &ehci_debug->data03); in dbgp_set_data() 253 writel(hi, &ehci_debug->data47); in dbgp_set_data() 291 writel(addr, &ehci_debug->address); in dbgp_bulk_write() 292 writel(pids, &ehci_debug->pids); in dbgp_bulk_write() 317 writel(addr, &ehci_debug->address); in dbgp_bulk_read() 318 writel(pids, &ehci_debug->pids); in dbgp_bulk_read() 358 writel(addr, &ehci_debug->address); in dbgp_control_msg() 359 writel(pids, &ehci_debug->pids); in dbgp_control_msg() [all …]
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/linux-4.4.14/arch/arm/mach-berlin/ |
D | platsmp.c | 41 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu() 43 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_perform_reset_cpu() 89 writel(boot_inst, vectors_base + RESET_VECT); in berlin_smp_prepare_cpus() 95 writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR); in berlin_smp_prepare_cpus() 116 writel(val, cpu_ctrl + CPU_RESET_NON_SC); in berlin_cpu_kill()
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/linux-4.4.14/drivers/iio/adc/ |
D | exynos_adc.c | 199 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_v1_init_hw() 211 writel(con, ADC_V1_CON(info->regs)); in exynos_adc_v1_exit_hw() 216 writel(1, ADC_V1_INTCLR(info->regs)); in exynos_adc_v1_clear_irq() 224 writel(addr, ADC_V1_MUX(info->regs)); in exynos_adc_v1_start_conv() 227 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_v1_start_conv() 250 writel(con1, ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv() 253 writel(addr, ADC_S3C2410_MUX(info->regs)); in exynos_adc_s3c2416_start_conv() 256 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_s3c2416_start_conv() 274 writel(addr, ADC_S3C2410_MUX(info->regs)); in exynos_adc_s3c2443_start_conv() 277 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); in exynos_adc_s3c2443_start_conv() [all …]
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/linux-4.4.14/drivers/pinctrl/ |
D | pinctrl-coh901.c | 237 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set() 239 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); in u300_gpio_set() 254 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_input() 281 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_direction_output() 360 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set() 364 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); in u300_gpio_config_set() 372 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set() 380 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set() 388 writel(val, U300_PIN_REG(offset, pcr)); in u300_gpio_config_set() 418 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); in u300_toggle_trigger() [all …]
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/linux-4.4.14/drivers/bus/ |
D | sunxi-rsb.c | 275 writel(RSB_INTS_LOAD_BSY | RSB_INTS_TRANS_ERR | RSB_INTS_TRANS_OVER, in _sunxi_rsb_run_xfer() 277 writel(RSB_CTRL_START_TRANS | RSB_CTRL_GLOBAL_INT_ENB, in _sunxi_rsb_run_xfer() 285 writel(RSB_CTRL_ABORT_TRANS, rsb->regs + RSB_CTRL); in _sunxi_rsb_run_xfer() 288 writel(readl(rsb->regs + RSB_INTS), rsb->regs + RSB_INTS); in _sunxi_rsb_run_xfer() 339 writel(addr, rsb->regs + RSB_ADDR); in sunxi_rsb_read() 340 writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR); in sunxi_rsb_read() 341 writel(cmd, rsb->regs + RSB_CMD); in sunxi_rsb_read() 381 writel(addr, rsb->regs + RSB_ADDR); in sunxi_rsb_write() 382 writel(RSB_DAR_RTA(rtaddr), rsb->regs + RSB_DAR); in sunxi_rsb_write() 383 writel(*buf, rsb->regs + RSB_DATA); in sunxi_rsb_write() [all …]
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/linux-4.4.14/arch/arm/mach-omap1/ |
D | time.c | 82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); in omap_mpu_set_autoreset() 89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); in omap_mpu_remove_autoreset() 101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); in omap_mpu_timer_start() 103 writel(load_val, &timer->load_tim); in omap_mpu_timer_start() 105 writel(timerflags, &timer->cntl); in omap_mpu_timer_start() 112 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); in omap_mpu_timer_stop()
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/linux-4.4.14/drivers/ide/ |
D | palm_bk3710.c | 94 writel(val32, base + BK3710_UDMASTB); in palm_bk3710_setudmamode() 99 writel(val32, base + BK3710_UDMATRP); in palm_bk3710_setudmamode() 104 writel(val32, base + BK3710_UDMAENV); in palm_bk3710_setudmamode() 132 writel(val32, base + BK3710_DMASTB); in palm_bk3710_setdmamode() 136 writel(val32, base + BK3710_DMARCVR); in palm_bk3710_setdmamode() 162 writel(val32, base + BK3710_DATSTB); in palm_bk3710_setpiomode() 166 writel(val32, base + BK3710_DATRCVR); in palm_bk3710_setpiomode() 184 writel(val32, base + BK3710_REGSTB); in palm_bk3710_setpiomode() 188 writel(val32, base + BK3710_REGRCVR); in palm_bk3710_setpiomode() 258 writel(0x001, base + BK3710_MISCCTL); in palm_bk3710_chipinit() [all …]
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