Searched refs:writel (Results 1 - 200 of 1520) sorted by relevance

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/linux-4.4.14/include/linux/
H A Dgoldfish.h9 writel((u32)(unsigned long)ptr, portl); gf_write_ptr()
11 writel((unsigned long)ptr >> 32, porth); gf_write_ptr()
19 writel((u32)addr, portl); gf_write_dma_addr()
21 writel(addr >> 32, porth); gf_write_dma_addr()
H A Dio-64-nonatomic-hi-lo.h20 writel(val >> 32, addr + 4); hi_lo_writeq()
21 writel(val, addr); hi_lo_writeq()
H A Dio-64-nonatomic-lo-hi.h20 writel(val, addr); lo_hi_writeq()
21 writel(val >> 32, addr + 4); lo_hi_writeq()
/linux-4.4.14/drivers/video/fbdev/
H A Dwmt_ge_rops.c67 writel(p->var.bits_per_pixel == 32 ? 3 : wmt_ge_fillrect()
69 writel(p->var.bits_per_pixel == 15 ? 1 : 0, regbase + GE_HIGHCOLOR_OFF); wmt_ge_fillrect()
70 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); wmt_ge_fillrect()
71 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); wmt_ge_fillrect()
72 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); wmt_ge_fillrect()
73 writel(rect->dx, regbase + GE_DESTAREAX_OFF); wmt_ge_fillrect()
74 writel(rect->dy, regbase + GE_DESTAREAY_OFF); wmt_ge_fillrect()
75 writel(rect->width - 1, regbase + GE_DESTAREAW_OFF); wmt_ge_fillrect()
76 writel(rect->height - 1, regbase + GE_DESTAREAH_OFF); wmt_ge_fillrect()
78 writel(pat, regbase + GE_PAT0C_OFF); wmt_ge_fillrect()
79 writel(1, regbase + GE_COMMAND_OFF); wmt_ge_fillrect()
80 writel(rect->rop == ROP_XOR ? 0x5a : 0xf0, regbase + GE_ROPCODE_OFF); wmt_ge_fillrect()
81 writel(1, regbase + GE_FIRE_OFF); wmt_ge_fillrect()
93 writel(p->var.bits_per_pixel > 16 ? 3 : wmt_ge_copyarea()
96 writel(p->fix.smem_start, regbase + GE_SRCBASE_OFF); wmt_ge_copyarea()
97 writel(p->var.xres_virtual - 1, regbase + GE_SRCDISPW_OFF); wmt_ge_copyarea()
98 writel(p->var.yres_virtual - 1, regbase + GE_SRCDISPH_OFF); wmt_ge_copyarea()
99 writel(area->sx, regbase + GE_SRCAREAX_OFF); wmt_ge_copyarea()
100 writel(area->sy, regbase + GE_SRCAREAY_OFF); wmt_ge_copyarea()
101 writel(area->width - 1, regbase + GE_SRCAREAW_OFF); wmt_ge_copyarea()
102 writel(area->height - 1, regbase + GE_SRCAREAH_OFF); wmt_ge_copyarea()
104 writel(p->fix.smem_start, regbase + GE_DESTBASE_OFF); wmt_ge_copyarea()
105 writel(p->var.xres_virtual - 1, regbase + GE_DESTDISPW_OFF); wmt_ge_copyarea()
106 writel(p->var.yres_virtual - 1, regbase + GE_DESTDISPH_OFF); wmt_ge_copyarea()
107 writel(area->dx, regbase + GE_DESTAREAX_OFF); wmt_ge_copyarea()
108 writel(area->dy, regbase + GE_DESTAREAY_OFF); wmt_ge_copyarea()
109 writel(area->width - 1, regbase + GE_DESTAREAW_OFF); wmt_ge_copyarea()
110 writel(area->height - 1, regbase + GE_DESTAREAH_OFF); wmt_ge_copyarea()
112 writel(0xcc, regbase + GE_ROPCODE_OFF); wmt_ge_copyarea()
113 writel(1, regbase + GE_COMMAND_OFF); wmt_ge_copyarea()
114 writel(1, regbase + GE_FIRE_OFF); wmt_ge_copyarea()
149 writel(1, regbase + GE_ENABLE_OFF); wmt_ge_rops_probe()
H A Dw100fb.c133 writel(param, remapped_regs + regs); w100fb_reg_write()
297 writel(W100_FB_BASE, remapped_regs + mmDST_OFFSET); w100_init_graphic_engine()
298 writel(par->xres, remapped_regs + mmDST_PITCH); w100_init_graphic_engine()
299 writel(W100_FB_BASE, remapped_regs + mmSRC_OFFSET); w100_init_graphic_engine()
300 writel(par->xres, remapped_regs + mmSRC_PITCH); w100_init_graphic_engine()
303 writel(0, remapped_regs + mmSC_TOP_LEFT); w100_init_graphic_engine()
304 writel((par->yres << 16) | par->xres, remapped_regs + mmSC_BOTTOM_RIGHT); w100_init_graphic_engine()
305 writel(0x1fff1fff, remapped_regs + mmSRC_SC_BOTTOM_RIGHT); w100_init_graphic_engine()
315 writel(dp_cntl.val, remapped_regs + mmDP_CNTL); w100_init_graphic_engine()
332 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); w100_init_graphic_engine()
341 writel(dp_datatype.val, remapped_regs + mmDP_DATATYPE); w100_init_graphic_engine()
347 writel(dp_mix.val, remapped_regs + mmDP_MIX); w100_init_graphic_engine()
367 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); w100fb_fillrect()
368 writel(rect->color, remapped_regs + mmDP_BRUSH_FRGD_CLR); w100fb_fillrect()
371 writel((rect->dy << 16) | (rect->dx & 0xffff), remapped_regs + mmDST_Y_X); w100fb_fillrect()
372 writel((rect->width << 16) | (rect->height & 0xffff), w100fb_fillrect()
395 writel(gmc.val, remapped_regs + mmDP_GUI_MASTER_CNTL); w100fb_copyarea()
398 writel((sy << 16) | (sx & 0xffff), remapped_regs + mmSRC_Y_X); w100fb_copyarea()
399 writel((dy << 16) | (dx & 0xffff), remapped_regs + mmDST_Y_X); w100fb_copyarea()
400 writel((w << 16) | (h & 0xffff), remapped_regs + mmDST_WIDTH_HEIGHT); w100fb_copyarea()
832 writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL); w100_update_disable()
843 writel((u32) (disp_db_buf_wr_cntl.val), remapped_regs + mmDISP_DB_BUF_CNTL); w100_update_enable()
861 writel(value, remapped_regs + mmGPIO_DATA); w100fb_gpio_write()
863 writel(value, remapped_regs + mmGPIO_DATA2); w100fb_gpio_write()
889 writel(0x31, remapped_regs + mmSCRATCH_UMSK); w100_hw_init()
892 writel(0x30, remapped_regs + mmSCRATCH_UMSK); w100_hw_init()
896 writel((u32)(cif_io.val), remapped_regs + mmCIF_IO); w100_hw_init()
902 writel((u32) (cif_write_dbg.val), remapped_regs + mmCIF_WRITE_DBG); w100_hw_init()
906 writel((u32) (cif_read_dbg.val), remapped_regs + mmCIF_READ_DBG); w100_hw_init()
914 writel((u32) (cif_cntl.val), remapped_regs + mmCIF_CNTL); w100_hw_init()
936 writel((u32) (cfgreg_base.val), remapped_regs + mmCFGREG_BASE); w100_hw_init()
940 writel((u32) (wrap_start_dir.val), remapped_regs + mmWRAP_START_DIR); w100_hw_init()
944 writel((u32) (wrap_top_dir.val), remapped_regs + mmWRAP_TOP_DIR); w100_hw_init()
946 writel((u32) 0x2440, remapped_regs + mmRBBM_CNTL); w100_hw_init()
952 writel(temp32, remapped_regs + mmDISP_DEBUG2); w100_hw_init()
956 writel(gpio->init_data1, remapped_regs + mmGPIO_DATA); w100_hw_init()
957 writel(gpio->init_data2, remapped_regs + mmGPIO_DATA2); w100_hw_init()
958 writel(gpio->gpio_dir1, remapped_regs + mmGPIO_CNTL1); w100_hw_init()
959 writel(gpio->gpio_oe1, remapped_regs + mmGPIO_CNTL2); w100_hw_init()
960 writel(gpio->gpio_dir2, remapped_regs + mmGPIO_CNTL3); w100_hw_init()
961 writel(gpio->gpio_oe2, remapped_regs + mmGPIO_CNTL4); w100_hw_init()
1046 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); w100_get_testcount()
1049 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); w100_get_testcount()
1053 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); w100_get_testcount()
1061 writel((u32) (clk_test_cntl.val), remapped_regs + mmCLK_TEST_CNTL); w100_get_testcount()
1088 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); w100_pll_adjust()
1094 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); w100_pll_adjust()
1134 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); w100_pll_calibration()
1140 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); w100_pll_calibration()
1144 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); w100_pll_calibration()
1162 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); w100_pll_set_clk()
1167 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); w100_pll_set_clk()
1173 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV); w100_pll_set_clk()
1176 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); w100_pll_set_clk()
1184 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); w100_pll_set_clk()
1213 writel((u32) (w100_pwr_state.clk_pin_cntl.val), remapped_regs + mmCLK_PIN_CNTL); w100_pwm_setup()
1233 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); w100_pwm_setup()
1238 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL); w100_pwm_setup()
1245 writel((u32) (w100_pwr_state.pll_ref_fb_div.val), remapped_regs + mmPLL_REF_FB_DIV); w100_pwm_setup()
1265 writel((u32) (w100_pwr_state.pll_cntl.val), remapped_regs + mmPLL_CNTL); w100_pwm_setup()
1276 writel((u32) (w100_pwr_state.pwrmgt_cntl.val), remapped_regs + mmPWRMGT_CNTL); w100_pwm_setup()
1295 writel((u32) (w100_pwr_state.sclk_cntl.val), remapped_regs + mmSCLK_CNTL); w100_init_clocks()
1314 writel(active_h_disp.val, remapped_regs + mmACTIVE_H_DISP); w100_init_lcd()
1319 writel(active_v_disp.val, remapped_regs + mmACTIVE_V_DISP); w100_init_lcd()
1324 writel(graphic_h_disp.val, remapped_regs + mmGRAPHIC_H_DISP); w100_init_lcd()
1329 writel(graphic_v_disp.val, remapped_regs + mmGRAPHIC_V_DISP); w100_init_lcd()
1334 writel(crtc_total.val, remapped_regs + mmCRTC_TOTAL); w100_init_lcd()
1336 writel(mode->crtc_ss, remapped_regs + mmCRTC_SS); w100_init_lcd()
1337 writel(mode->crtc_ls, remapped_regs + mmCRTC_LS); w100_init_lcd()
1338 writel(mode->crtc_gs, remapped_regs + mmCRTC_GS); w100_init_lcd()
1339 writel(mode->crtc_vpos_gs, remapped_regs + mmCRTC_VPOS_GS); w100_init_lcd()
1340 writel(mode->crtc_rev, remapped_regs + mmCRTC_REV); w100_init_lcd()
1341 writel(mode->crtc_dclk, remapped_regs + mmCRTC_DCLK); w100_init_lcd()
1342 writel(mode->crtc_gclk, remapped_regs + mmCRTC_GCLK); w100_init_lcd()
1343 writel(mode->crtc_goe, remapped_regs + mmCRTC_GOE); w100_init_lcd()
1344 writel(mode->crtc_ps1_active, remapped_regs + mmCRTC_PS1_ACTIVE); w100_init_lcd()
1346 writel(regs->lcd_format, remapped_regs + mmLCD_FORMAT); w100_init_lcd()
1347 writel(regs->lcdd_cntl1, remapped_regs + mmLCDD_CNTL1); w100_init_lcd()
1348 writel(regs->lcdd_cntl2, remapped_regs + mmLCDD_CNTL2); w100_init_lcd()
1349 writel(regs->genlcd_cntl1, remapped_regs + mmGENLCD_CNTL1); w100_init_lcd()
1350 writel(regs->genlcd_cntl2, remapped_regs + mmGENLCD_CNTL2); w100_init_lcd()
1351 writel(regs->genlcd_cntl3, remapped_regs + mmGENLCD_CNTL3); w100_init_lcd()
1353 writel(0x00000000, remapped_regs + mmCRTC_FRAME); w100_init_lcd()
1354 writel(0x00000000, remapped_regs + mmCRTC_FRAME_VPOS); w100_init_lcd()
1355 writel(0x00000000, remapped_regs + mmCRTC_DEFAULT_COUNT); w100_init_lcd()
1356 writel(0x0000FF00, remapped_regs + mmLCD_BACKGROUND_COLOR); w100_init_lcd()
1361 writel(temp32, remapped_regs + mmDISP_DEBUG2); w100_init_lcd()
1378 writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION); w100_setup_memory()
1384 writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION); w100_setup_memory()
1389 writel((u32) (intmem_location.val), remapped_regs + mmMC_FB_LOCATION); w100_setup_memory()
1394 writel((u32) (extmem_location.val), remapped_regs + mmMC_EXT_MEM_LOCATION); w100_setup_memory()
1396 writel(0x00007800, remapped_regs + mmMC_BIST_CTRL); w100_setup_memory()
1397 writel(mem->ext_cntl, remapped_regs + mmMEM_EXT_CNTL); w100_setup_memory()
1398 writel(0x00200021, remapped_regs + mmMEM_SDRAM_MODE_REG); w100_setup_memory()
1400 writel(0x80200021, remapped_regs + mmMEM_SDRAM_MODE_REG); w100_setup_memory()
1402 writel(mem->sdram_mode_reg, remapped_regs + mmMEM_SDRAM_MODE_REG); w100_setup_memory()
1404 writel(mem->ext_timing_cntl, remapped_regs + mmMEM_EXT_TIMING_CNTL); w100_setup_memory()
1405 writel(mem->io_cntl, remapped_regs + mmMEM_IO_CNTL); w100_setup_memory()
1407 writel(bm_mem->ext_mem_bw, remapped_regs + mmBM_EXT_MEM_BANDWIDTH); w100_setup_memory()
1408 writel(bm_mem->offset, remapped_regs + mmBM_OFFSET); w100_setup_memory()
1409 writel(bm_mem->ext_timing_ctl, remapped_regs + mmBM_MEM_EXT_TIMING_CNTL); w100_setup_memory()
1410 writel(bm_mem->ext_cntl, remapped_regs + mmBM_MEM_EXT_CNTL); w100_setup_memory()
1411 writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG); w100_setup_memory()
1412 writel(bm_mem->io_cntl, remapped_regs + mmBM_MEM_IO_CNTL); w100_setup_memory()
1413 writel(bm_mem->config, remapped_regs + mmBM_CONFIG); w100_setup_memory()
1498 writel((u32) (w100_pwr_state.pclk_cntl.val), remapped_regs + mmPCLK_CNTL); w100_set_dispregs()
1500 writel(graphic_ctrl.val, remapped_regs + mmGRAPHIC_CTRL); w100_set_dispregs()
1501 writel(W100_FB_BASE + ((offset * BITS_PER_PIXEL/8)&~0x03UL), remapped_regs + mmGRAPHIC_OFFSET); w100_set_dispregs()
1502 writel((par->xres*BITS_PER_PIXEL/8), remapped_regs + mmGRAPHIC_PITCH); w100_set_dispregs()
1534 writel(0x7FFF8000, remapped_regs + mmMC_EXT_MEM_LOCATION); w100_suspend()
1535 writel(0x00FF0000, remapped_regs + mmMC_PERF_MON_CNTL); w100_suspend()
1540 writel(val, remapped_regs + mmMEM_EXT_TIMING_CNTL); w100_suspend()
1545 writel(val, remapped_regs + mmMEM_EXT_CNTL); w100_suspend()
1553 writel(val, remapped_regs + mmMEM_EXT_CNTL); w100_suspend()
1558 writel(val, remapped_regs + mmMEM_EXT_CNTL); w100_suspend()
1560 writel(0x00000000, remapped_regs + mmSCLK_CNTL); w100_suspend()
1561 writel(0x000000BF, remapped_regs + mmCLK_PIN_CNTL); w100_suspend()
1562 writel(0x00000015, remapped_regs + mmPWRMGT_CNTL); w100_suspend()
1568 writel(val, remapped_regs + mmPLL_CNTL); w100_suspend()
1570 writel(0x00000000, remapped_regs + mmLCDD_CNTL1); w100_suspend()
1571 writel(0x00000000, remapped_regs + mmLCDD_CNTL2); w100_suspend()
1572 writel(0x00000000, remapped_regs + mmGENLCD_CNTL1); w100_suspend()
1573 writel(0x00000000, remapped_regs + mmGENLCD_CNTL2); w100_suspend()
1574 writel(0x00000000, remapped_regs + mmGENLCD_CNTL3); w100_suspend()
1579 writel(val, remapped_regs + mmMEM_EXT_CNTL); w100_suspend()
1581 writel(0x0000001d, remapped_regs + mmPWRMGT_CNTL); w100_suspend()
1593 writel((tmp >> 16) & 0x3ff, remapped_regs + mmDISP_INT_CNTL); w100_vsync()
1599 writel(tmp, remapped_regs + mmGEN_INT_CNTL); w100_vsync()
1602 writel(0x00000002, remapped_regs + mmGEN_INT_STATUS); w100_vsync()
1605 writel((tmp | 0x00000002), remapped_regs + mmGEN_INT_CNTL); w100_vsync()
1608 writel(0x00000002, remapped_regs + mmGEN_INT_STATUS); w100_vsync()
1618 writel(tmp, remapped_regs + mmGEN_INT_CNTL); w100_vsync()
1621 writel(0x00000002, remapped_regs + mmGEN_INT_STATUS); w100_vsync()
H A Dwm8505fb.c59 writel(0, fbi->regbase + i); wm8505fb_init_hw()
62 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR); wm8505fb_init_hw()
63 writel(fbi->fb.fix.smem_start, fbi->regbase + WMT_GOVR_FBADDR1); wm8505fb_init_hw()
70 writel(0x31c, fbi->regbase + WMT_GOVR_COLORSPACE); wm8505fb_init_hw()
71 writel(1, fbi->regbase + WMT_GOVR_COLORSPACE1); wm8505fb_init_hw()
74 writel(info->var.xres, fbi->regbase + WMT_GOVR_XRES); wm8505fb_init_hw()
75 writel(info->var.xres_virtual, fbi->regbase + WMT_GOVR_XRES_VIRTUAL); wm8505fb_init_hw()
78 writel(0xf, fbi->regbase + WMT_GOVR_FHI); wm8505fb_init_hw()
79 writel(4, fbi->regbase + WMT_GOVR_DVO_SET); wm8505fb_init_hw()
80 writel(1, fbi->regbase + WMT_GOVR_MIF_ENABLE); wm8505fb_init_hw()
81 writel(1, fbi->regbase + WMT_GOVR_REG_UPDATE); wm8505fb_init_hw()
100 writel(0, fbi->regbase + WMT_GOVR_TG); wm8505fb_set_timing()
102 writel(h_start, fbi->regbase + WMT_GOVR_TIMING_H_START); wm8505fb_set_timing()
103 writel(h_end, fbi->regbase + WMT_GOVR_TIMING_H_END); wm8505fb_set_timing()
104 writel(h_all, fbi->regbase + WMT_GOVR_TIMING_H_ALL); wm8505fb_set_timing()
105 writel(h_sync, fbi->regbase + WMT_GOVR_TIMING_H_SYNC); wm8505fb_set_timing()
107 writel(v_start, fbi->regbase + WMT_GOVR_TIMING_V_START); wm8505fb_set_timing()
108 writel(v_end, fbi->regbase + WMT_GOVR_TIMING_V_END); wm8505fb_set_timing()
109 writel(v_all, fbi->regbase + WMT_GOVR_TIMING_V_ALL); wm8505fb_set_timing()
110 writel(v_sync, fbi->regbase + WMT_GOVR_TIMING_V_SYNC); wm8505fb_set_timing()
112 writel(1, fbi->regbase + WMT_GOVR_TG); wm8505fb_set_timing()
153 writel(fbi->contrast<<16 | fbi->contrast<<8 | fbi->contrast, wm8505fb_set_par()
230 writel(var->xoffset, fbi->regbase + WMT_GOVR_XPAN); wm8505fb_pan_display()
231 writel(var->yoffset, fbi->regbase + WMT_GOVR_YPAN); wm8505fb_pan_display()
244 writel(0, fbi->regbase + WMT_GOVR_TIMING_V_SYNC); wm8505fb_blank()
393 writel(0, fbi->regbase); wm8505fb_remove()
H A Dfb-puv3.c164 writel(((u32 *)(info->pseudo_palette))[fg_color], UGE_FCOLOR); unifb_prim_fillrect()
165 writel(0, UGE_BCOLOR); unifb_prim_fillrect()
166 writel(src_pitch, UGE_PITCH); unifb_prim_fillrect()
167 writel(src_offset, UGE_SRCSTART); unifb_prim_fillrect()
168 writel(dst_offset, UGE_DSTSTART); unifb_prim_fillrect()
169 writel(awidth, UGE_WIDHEIGHT); unifb_prim_fillrect()
170 writel(top, UGE_CLIP0); unifb_prim_fillrect()
171 writel(bottom, UGE_CLIP1); unifb_prim_fillrect()
172 writel(alpha_r, UGE_ROPALPHA); unifb_prim_fillrect()
173 writel(src_x0, UGE_SRCXY); unifb_prim_fillrect()
174 writel(dst_x0, UGE_DSTXY); unifb_prim_fillrect()
175 writel(command, UGE_COMMAND); unifb_prim_fillrect()
271 writel(src_pitch, UGE_PITCH); unifb_prim_copyarea()
272 writel(src_offset, UGE_SRCSTART); unifb_prim_copyarea()
273 writel(dst_offset, UGE_DSTSTART); unifb_prim_copyarea()
274 writel(awidth, UGE_WIDHEIGHT); unifb_prim_copyarea()
275 writel(top, UGE_CLIP0); unifb_prim_copyarea()
276 writel(bottom, UGE_CLIP1); unifb_prim_copyarea()
277 writel(bg_color, UGE_BCOLOR); unifb_prim_copyarea()
278 writel(fg_color, UGE_FCOLOR); unifb_prim_copyarea()
279 writel(alpha_r, UGE_ROPALPHA); unifb_prim_copyarea()
280 writel(src_x0, UGE_SRCXY); unifb_prim_copyarea()
281 writel(dst_x0, UGE_DSTXY); unifb_prim_copyarea()
282 writel(command, UGE_COMMAND); unifb_prim_copyarea()
535 writel(info->fix.smem_start, UDE_FSA); unifb_set_par()
536 writel(info->var.yres, UDE_LS); unifb_set_par()
537 writel(get_line_length(info->var.xres, unifb_set_par()
540 writel((hTotal << 16) | (info->var.xres), UDE_HAT); unifb_set_par()
541 writel(((hTotal - 1) << 16) | (info->var.xres - 1), UDE_HBT); unifb_set_par()
542 writel(((hSyncEnd - 1) << 16) | (hSyncStart - 1), UDE_HST); unifb_set_par()
543 writel((vTotal << 16) | (info->var.yres), UDE_VAT); unifb_set_par()
544 writel(((vTotal - 1) << 16) | (info->var.yres - 1), UDE_VBT); unifb_set_par()
545 writel(((vSyncEnd - 1) << 16) | (vSyncStart - 1), UDE_VST); unifb_set_par()
546 writel(UDE_CFG_GDEN_ENABLE | UDE_CFG_TIMEUP_ENABLE unifb_set_par()
753 writel(unifb_regs[0], UDE_FSA); unifb_resume()
754 writel(unifb_regs[1], UDE_LS); unifb_resume()
755 writel(unifb_regs[2], UDE_PS); unifb_resume()
756 writel(unifb_regs[3], UDE_HAT); unifb_resume()
757 writel(unifb_regs[4], UDE_HBT); unifb_resume()
758 writel(unifb_regs[5], UDE_HST); unifb_resume()
759 writel(unifb_regs[6], UDE_VAT); unifb_resume()
760 writel(unifb_regs[7], UDE_VBT); unifb_resume()
761 writel(unifb_regs[8], UDE_VST); unifb_resume()
762 writel(unifb_regs[9], UDE_CFG); unifb_resume()
H A Doffb.c173 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); offb_setcolreg()
175 writel(((red) << 22) | ((green) << 12) | ((blue) << 2), offb_setcolreg()
177 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); offb_setcolreg()
179 writel(((red) << 22) | ((green) << 12) | ((blue) << 2), offb_setcolreg()
239 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); offb_blank()
241 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); offb_blank()
242 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); offb_blank()
244 writel(0, par->cmap_adr + AVIVO_DC_LUT_30_COLOR); offb_blank()
258 writel(0, par->cmap_adr + AVIVO_DC_LUTA_CONTROL); offb_set_par()
259 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_BLUE); offb_set_par()
260 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_GREEN); offb_set_par()
261 writel(0, par->cmap_adr + AVIVO_DC_LUTA_BLACK_OFFSET_RED); offb_set_par()
262 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_BLUE); offb_set_par()
263 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_GREEN); offb_set_par()
264 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTA_WHITE_OFFSET_RED); offb_set_par()
265 writel(0, par->cmap_adr + AVIVO_DC_LUTB_CONTROL); offb_set_par()
266 writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_BLUE); offb_set_par()
267 writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_GREEN); offb_set_par()
268 writel(0, par->cmap_adr + AVIVO_DC_LUTB_BLACK_OFFSET_RED); offb_set_par()
269 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_BLUE); offb_set_par()
270 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_GREEN); offb_set_par()
271 writel(0x0000ffff, par->cmap_adr + AVIVO_DC_LUTB_WHITE_OFFSET_RED); offb_set_par()
272 writel(1, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); offb_set_par()
273 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE); offb_set_par()
274 writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK); offb_set_par()
275 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_SELECT); offb_set_par()
276 writel(0, par->cmap_adr + AVIVO_DC_LUT_RW_MODE); offb_set_par()
277 writel(0x0000003f, par->cmap_adr + AVIVO_DC_LUT_WRITE_EN_MASK); offb_set_par()
H A Dpxa168fb.c291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); set_clock_divider()
326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); set_dma_control0()
348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); set_dma_control1()
361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); set_graphics_start()
386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); set_dumb_panel_control()
399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); set_dumb_screen_dimensions()
426 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); pxa168fb_set_par()
431 writel((var->yres << 16) | var->xres, pxa168fb_set_par()
451 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); pxa168fb_set_par()
452 writel((var->yres << 16) | var->xres, pxa168fb_set_par()
454 writel((var->yres << 16) | var->xres, pxa168fb_set_par()
463 writel((var->left_margin << 16) | var->right_margin, pxa168fb_set_par()
465 writel((var->upper_margin << 16) | var->lower_margin, pxa168fb_set_par()
472 writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL); pxa168fb_set_par()
511 writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT); pxa168fb_setcolreg()
512 writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL); pxa168fb_setcolreg()
543 writel(isr & (~GRA_FRAME_IRQ0_ENA_MASK), pxa168fb_handle_irq()
722 writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR); pxa168fb_probe()
723 writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL); pxa168fb_probe()
724 writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1); pxa168fb_probe()
725 writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN); pxa168fb_probe()
726 writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0); pxa168fb_probe()
727 writel(CFG_CSB_256x32(0x1)|CFG_CSB_256x24(0x1)|CFG_CSB_256x8(0x1), pxa168fb_probe()
752 writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA); pxa168fb_probe()
794 writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0); pxa168fb_remove()
800 writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA); pxa168fb_remove()
H A Ds3c-fb.c47 #undef writel macro
48 #define writel(v, r) do { \ macro
401 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant) vidosd_set_size()
416 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant)); vidosd_set_alpha()
432 writel(PRTCON_PROTECT, sfb->regs + PRTCON); shadow_protect_win()
435 writel(reg | SHADOWCON_WINx_PROTECT(win->index), shadow_protect_win()
440 writel(0, sfb->regs + PRTCON); shadow_protect_win()
443 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index), shadow_protect_win()
474 writel(vidcon0, sfb->regs + VIDCON0); s3c_fb_enable()
533 writel(0, regs + WINCON(win_no)); s3c_fb_set_par()
543 writel(info->fix.smem_start, buf + sfb->variant.buf_start); s3c_fb_set_par()
546 writel(data, buf + sfb->variant.buf_end); s3c_fb_set_par()
553 writel(data, regs + sfb->variant.buf_size + (win_no * 4)); s3c_fb_set_par()
559 writel(data, regs + VIDOSD_A(win_no, sfb->variant)); s3c_fb_set_par()
568 writel(data, regs + VIDOSD_B(win_no, sfb->variant)); s3c_fb_set_par()
583 writel(data, sfb->regs + SHADOWCON); s3c_fb_set_par()
660 writel(keycon0_data, keycon + WKEYCON0); s3c_fb_set_par()
661 writel(keycon1_data, keycon + WKEYCON1); s3c_fb_set_par()
664 writel(data, regs + sfb->variant.wincon + (win_no * 4)); s3c_fb_set_par()
665 writel(0x0, regs + sfb->variant.winmap + (win_no * 4)); s3c_fb_set_par()
675 writel(data, sfb->regs + BLENDCON); s3c_fb_set_par()
715 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON); s3c_fb_update_palette()
720 writel(value, palreg + (reg * 4)); s3c_fb_update_palette()
722 writel(palcon, sfb->regs + WPALCON); s3c_fb_update_palette()
820 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0), s3c_fb_blank()
827 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4)); s3c_fb_blank()
841 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4)); s3c_fb_blank()
906 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start); s3c_fb_pan_display()
907 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end); s3c_fb_pan_display()
936 writel(irq_ctrl_reg, regs + VIDINTCON0); s3c_fb_enable_irq()
956 writel(irq_ctrl_reg, regs + VIDINTCON0); s3c_fb_disable_irq()
973 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1); s3c_fb_irq()
1154 writel(data, sfb->regs + SHADOWCON); s3c_fb_release_win()
1316 writel(data, regs + VIDCON0); s3c_fb_set_rgb_timing()
1321 writel(data, regs + sfb->variant.vidtcon); s3c_fb_set_rgb_timing()
1326 writel(data, regs + sfb->variant.vidtcon + 4); s3c_fb_set_rgb_timing()
1332 writel(data, regs + sfb->variant.vidtcon + 8); s3c_fb_set_rgb_timing()
1347 writel(0, regs + sfb->variant.wincon + (win * 4)); s3c_fb_clear_win()
1348 writel(0, regs + VIDOSD_A(win, sfb->variant)); s3c_fb_clear_win()
1349 writel(0, regs + VIDOSD_B(win, sfb->variant)); s3c_fb_clear_win()
1350 writel(0, regs + VIDOSD_C(win, sfb->variant)); s3c_fb_clear_win()
1357 writel(reg, sfb->regs + SHADOWCON); s3c_fb_clear_win()
1452 writel(pd->vidcon1, sfb->regs + VIDCON1); s3c_fb_probe()
1459 writel(reg, sfb->regs + VIDCON1); s3c_fb_probe()
1472 writel(0xffffff, regs + WKEYCON0); s3c_fb_probe()
1473 writel(0xffffff, regs + WKEYCON1); s3c_fb_probe()
1588 writel(pd->vidcon1, sfb->regs + VIDCON1); s3c_fb_resume()
1595 writel(reg, sfb->regs + VIDCON1); s3c_fb_resume()
1610 writel(0xffffff, regs + WKEYCON0); s3c_fb_resume()
1611 writel(0xffffff, regs + WKEYCON1); s3c_fb_resume()
1658 writel(pd->vidcon1, sfb->regs + VIDCON1); s3c_fb_runtime_resume()
/linux-4.4.14/arch/arm/mach-pxa/
H A Dcm-x2xx-pci.c136 writel(0x848, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
137 writel(0, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
140 writel(0x840, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
141 writel(0, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
143 writel(0x20, IT8152_GPIO_GPDR); cmx2xx_pci_preinit()
146 writel(0x4000, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
151 writel(0x408C, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
152 writel(0x1022, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
154 writel(0x4080, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
155 writel(0x3844d060, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
157 writel(0x4090, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
158 writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | cmx2xx_pci_preinit()
162 writel(0x4018, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
163 writel(0xb0000000, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
166 writel(0x418C, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
167 writel(0x1022, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
169 writel(0x4180, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
170 writel(0x3844d060, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
172 writel(0x4190, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
173 writel(((readl(IT8152_PCI_CFG_DATA) & 0xffff) | cmx2xx_pci_preinit()
177 writel(0x4118, IT8152_PCI_CFG_ADDR); cmx2xx_pci_preinit()
178 writel(0xb0000000, IT8152_PCI_CFG_DATA); cmx2xx_pci_preinit()
H A Dpxa_cplds_irqs.c58 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); cplds_irq_mask_ack()
60 writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR); cplds_irq_mask_ack()
70 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); cplds_irq_unmask()
100 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); cplds_resume()
136 writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN); cplds_probe()
137 writel(0, fpga->base + FPGA_IRQ_SET_CLR); cplds_probe()
/linux-4.4.14/arch/unicore32/kernel/
H A Dtime.c29 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); puv3_ost0_interrupt()
30 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); puv3_ost0_interrupt()
41 writel(readl(OST_OIER) | OST_OIER_E0, OST_OIER); puv3_osmr0_set_next_event()
43 writel(next, OST_OSMR0); puv3_osmr0_set_next_event()
51 writel(readl(OST_OIER) & ~OST_OIER_E0, OST_OIER); puv3_osmr0_shutdown()
52 writel(readl(OST_OSSR) & ~OST_OSSR_M0, OST_OSSR); puv3_osmr0_shutdown()
87 writel(0, OST_OIER); /* disable any timer interrupts */ time_init()
88 writel(0, OST_OSSR); /* clear status on all timers */ time_init()
118 writel(0, OST_OSSR); puv3_timer_resume()
119 writel(osmr[0], OST_OSMR0); puv3_timer_resume()
120 writel(osmr[1], OST_OSMR1); puv3_timer_resume()
121 writel(osmr[2], OST_OSMR2); puv3_timer_resume()
122 writel(osmr[3], OST_OSMR3); puv3_timer_resume()
123 writel(oier, OST_OIER); puv3_timer_resume()
128 writel(readl(OST_OSMR0) - LATCH, OST_OSCR); puv3_timer_resume()
H A Dirq.c68 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); puv3_gpio_type()
69 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); puv3_gpio_type()
79 writel((1 << d->irq), GPIO_GEDR); puv3_low_gpio_ack()
84 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); puv3_low_gpio_mask()
89 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); puv3_low_gpio_unmask()
95 writel(readl(PM_PWER) | (1 << d->irq), PM_PWER); puv3_low_gpio_wake()
97 writel(readl(PM_PWER) & ~(1 << d->irq), PM_PWER); puv3_low_gpio_wake()
125 writel(mask, GPIO_GEDR); puv3_gpio_handler()
147 writel(mask, GPIO_GEDR); puv3_high_gpio_ack()
156 writel(readl(GPIO_GRER) & ~mask, GPIO_GRER); puv3_high_gpio_mask()
157 writel(readl(GPIO_GFER) & ~mask, GPIO_GFER); puv3_high_gpio_mask()
166 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); puv3_high_gpio_unmask()
167 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); puv3_high_gpio_unmask()
173 writel(readl(PM_PWER) | PM_PWER_GPIOHIGH, PM_PWER); puv3_high_gpio_wake()
175 writel(readl(PM_PWER) & ~PM_PWER_GPIOHIGH, PM_PWER); puv3_high_gpio_wake()
194 writel(readl(INTC_ICMR) & ~(1 << d->irq), INTC_ICMR); puv3_mask_irq()
199 writel(readl(INTC_ICMR) | (1 << d->irq), INTC_ICMR); puv3_unmask_irq()
209 writel(readl(PM_PWER) | PM_PWER_RTC, PM_PWER); puv3_set_wake()
211 writel(readl(PM_PWER) & ~PM_PWER_RTC, PM_PWER); puv3_set_wake()
250 writel(readl(INTC_ICMR) & ~(0x1ff), INTC_ICMR); puv3_irq_suspend()
255 writel(readl(PM_PWER) & GPIO_IRQ_rising_edge, GPIO_GRER); puv3_irq_suspend()
256 writel(readl(PM_PWER) & GPIO_IRQ_falling_edge, GPIO_GFER); puv3_irq_suspend()
261 writel(readl(GPIO_GEDR), GPIO_GEDR); puv3_irq_suspend()
271 writel(st->iccr, INTC_ICCR); puv3_irq_resume()
272 writel(st->iclr, INTC_ICLR); puv3_irq_resume()
274 writel(GPIO_IRQ_rising_edge & GPIO_IRQ_mask, GPIO_GRER); puv3_irq_resume()
275 writel(GPIO_IRQ_falling_edge & GPIO_IRQ_mask, GPIO_GFER); puv3_irq_resume()
277 writel(st->icmr, INTC_ICMR); puv3_irq_resume()
301 writel(0, INTC_ICMR); init_IRQ()
304 writel(0, INTC_ICLR); init_IRQ()
307 writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ), GPIO_GPIR); init_IRQ()
308 writel(0, GPIO_GFER); init_IRQ()
309 writel(0, GPIO_GRER); init_IRQ()
310 writel(0x0FFFFFFF, GPIO_GEDR); init_IRQ()
312 writel(1, INTC_ICCR); init_IRQ()
H A Dpci.c32 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); puv3_read_config()
51 writel(CONFIG_CMD(bus, devfn, where), PCICFG_ADDR); puv3_write_config()
54 writel((readl(PCICFG_DATA) & ~FMASK(8, (where&3)*8)) puv3_write_config()
58 writel((readl(PCICFG_DATA) & ~FMASK(16, (where&2)*8)) puv3_write_config()
62 writel(value, PCICFG_DATA); puv3_write_config()
77 writel(io_v2p(PKUNITY_PCIBRI_BASE), PCICFG_BRIBASE); pci_puv3_preinit()
79 writel(0, PCIBRI_AHBCTL0); pci_puv3_preinit()
80 writel(io_v2p(PKUNITY_PCIBRI_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR0); pci_puv3_preinit()
81 writel(0xFFFF0000, PCIBRI_AHBAMR0); pci_puv3_preinit()
82 writel(0, PCIBRI_AHBTAR0); pci_puv3_preinit()
84 writel(PCIBRI_CTLx_AT, PCIBRI_AHBCTL1); pci_puv3_preinit()
85 writel(io_v2p(PKUNITY_PCILIO_BASE) | PCIBRI_BARx_IO, PCIBRI_AHBBAR1); pci_puv3_preinit()
86 writel(0xFFFF0000, PCIBRI_AHBAMR1); pci_puv3_preinit()
87 writel(0x00000000, PCIBRI_AHBTAR1); pci_puv3_preinit()
89 writel(PCIBRI_CTLx_PREF, PCIBRI_AHBCTL2); pci_puv3_preinit()
90 writel(io_v2p(PKUNITY_PCIMEM_BASE) | PCIBRI_BARx_MEM, PCIBRI_AHBBAR2); pci_puv3_preinit()
91 writel(0xF8000000, PCIBRI_AHBAMR2); pci_puv3_preinit()
92 writel(0, PCIBRI_AHBTAR2); pci_puv3_preinit()
94 writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_BAR1); pci_puv3_preinit()
96 writel(PCIBRI_CTLx_AT | PCIBRI_CTLx_PREF, PCIBRI_PCICTL0); pci_puv3_preinit()
97 writel(io_v2p(PKUNITY_PCIAHB_BASE) | PCIBRI_BARx_MEM, PCIBRI_PCIBAR0); pci_puv3_preinit()
98 writel(0xF8000000, PCIBRI_PCIAMR0); pci_puv3_preinit()
99 writel(PKUNITY_SDRAM_BASE, PCIBRI_PCITAR0); pci_puv3_preinit()
101 writel(readl(PCIBRI_CMD) | PCIBRI_CMD_IO | PCIBRI_CMD_MEM, PCIBRI_CMD); pci_puv3_preinit()
H A Dgpio.c61 writel(GPIO_GPIO(offset), GPIO_GPSR); puv3_gpio_set()
63 writel(GPIO_GPIO(offset), GPIO_GPCR); puv3_gpio_set()
71 writel(readl(GPIO_GPDR) & ~GPIO_GPIO(offset), GPIO_GPDR); puv3_direction_input()
83 writel(readl(GPIO_GPDR) | GPIO_GPIO(offset), GPIO_GPDR); puv3_direction_output()
100 writel(GPIO_DIR, GPIO_GPDR); puv3_init_gpio()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb/
H A Dtp.c31 writel(val, ap->regs + A_TP_IN_CONFIG); tp_init()
32 writel(F_TP_OUT_CSPI_CPL | tp_init()
36 writel(V_IP_TTL(64) | tp_init()
46 writel(F_ENABLE_TX_DROP | F_ENABLE_TX_ERROR | tp_init()
77 writel(0xffffffff, t1_tp_intr_enable()
79 writel(tp_intr | FPGA_PCIX_INTERRUPT_TP, t1_tp_intr_enable()
85 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); t1_tp_intr_enable()
86 writel(tp_intr | F_PL_INTR_TP, t1_tp_intr_enable()
98 writel(0, tp->adapter->regs + FPGA_TP_ADDR_INTERRUPT_ENABLE); t1_tp_intr_disable()
99 writel(tp_intr & ~FPGA_PCIX_INTERRUPT_TP, t1_tp_intr_disable()
104 writel(0, tp->adapter->regs + A_TP_INT_ENABLE); t1_tp_intr_disable()
105 writel(tp_intr & ~F_PL_INTR_TP, t1_tp_intr_disable()
114 writel(0xffffffff, t1_tp_intr_clear()
116 writel(FPGA_PCIX_INTERRUPT_TP, tp->adapter->regs + A_PL_CAUSE); t1_tp_intr_clear()
120 writel(0xffffffff, tp->adapter->regs + A_TP_INT_CAUSE); t1_tp_intr_clear()
121 writel(F_PL_INTR_TP, tp->adapter->regs + A_PL_CAUSE); t1_tp_intr_clear()
135 writel(cause, tp->adapter->regs + A_TP_INT_CAUSE); t1_tp_intr_handler()
147 writel(val, tp->adapter->regs + A_TP_GLOBAL_CONFIG); set_csum_offload()
169 writel(F_TP_RESET, adapter->regs + A_TP_RESET); t1_tp_reset()
H A Despi.c65 writel(V_WRITE_DATA(wr_data) | tricn_write()
71 writel(0, adapter->regs + A_ESPI_GOSTAT); tricn_write()
92 writel(F_ESPI_RX_CORE_RST, adapter->regs + A_ESPI_RX_RESET); tricn_init()
111 writel(F_ESPI_RX_CORE_RST | F_ESPI_RX_LNK_RST, tricn_init()
129 writel(enable, espi->adapter->regs + A_ESPI_INTR_ENABLE); t1_espi_intr_enable()
130 writel(pl_intr | F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); t1_espi_intr_enable()
136 writel(0xffffffff, espi->adapter->regs + A_ESPI_INTR_STATUS); t1_espi_intr_clear()
137 writel(F_PL_INTR_ESPI, espi->adapter->regs + A_PL_CAUSE); t1_espi_intr_clear()
144 writel(0, espi->adapter->regs + A_ESPI_INTR_ENABLE); t1_espi_intr_disable()
145 writel(pl_intr & ~F_PL_INTR_ESPI, espi->adapter->regs + A_PL_ENABLE); t1_espi_intr_disable()
178 writel(status, espi->adapter->regs + A_ESPI_INTR_STATUS); t1_espi_intr_handler()
191 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); espi_setup_for_pm3393()
192 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN1); espi_setup_for_pm3393()
193 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); espi_setup_for_pm3393()
194 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN3); espi_setup_for_pm3393()
195 writel(0x100, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); espi_setup_for_pm3393()
196 writel(wmark, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); espi_setup_for_pm3393()
197 writel(3, adapter->regs + A_ESPI_CALENDAR_LENGTH); espi_setup_for_pm3393()
198 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); espi_setup_for_pm3393()
199 writel(V_RX_NPORTS(1) | V_TX_NPORTS(1), adapter->regs + A_PORT_CONFIG); espi_setup_for_pm3393()
204 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN0); espi_setup_for_vsc7321()
205 writel(0x1f401f4, adapter->regs + A_ESPI_SCH_TOKEN1); espi_setup_for_vsc7321()
206 writel(0x1f4, adapter->regs + A_ESPI_SCH_TOKEN2); espi_setup_for_vsc7321()
207 writel(0xa00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); espi_setup_for_vsc7321()
208 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); espi_setup_for_vsc7321()
209 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); espi_setup_for_vsc7321()
210 writel(V_RX_NPORTS(4) | V_TX_NPORTS(4), adapter->regs + A_PORT_CONFIG); espi_setup_for_vsc7321()
212 writel(0x08000008, adapter->regs + A_ESPI_TRAIN); espi_setup_for_vsc7321()
220 writel(1, adapter->regs + A_ESPI_CALENDAR_LENGTH); espi_setup_for_ixf1010()
223 writel(0xf00, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); espi_setup_for_ixf1010()
224 writel(0x3c0, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); espi_setup_for_ixf1010()
226 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); espi_setup_for_ixf1010()
227 writel(0x1ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); espi_setup_for_ixf1010()
230 writel(0x1fff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK); espi_setup_for_ixf1010()
231 writel(0x7ff, adapter->regs + A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK); espi_setup_for_ixf1010()
233 writel(V_RX_NPORTS(nports) | V_TX_NPORTS(nports), adapter->regs + A_PORT_CONFIG); espi_setup_for_ixf1010()
243 writel(0, adapter->regs + A_ESPI_TRAIN); t1_espi_init()
246 writel(V_OUT_OF_SYNC_COUNT(4) | t1_espi_init()
249 writel(nports == 4 ? 0x200040 : 0x1000080, t1_espi_init()
252 writel(0x800100, adapter->regs + A_ESPI_MAXBURST1_MAXBURST2); t1_espi_init()
264 writel(status_enable_extra | F_RXSTATUSENABLE, t1_espi_init()
278 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); t1_espi_init()
309 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL);
330 writel(((espi->misc_ctrl & ~MON_MASK) | sel), t1_espi_get_mon()
333 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); t1_espi_get_mon()
359 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); t1_espi_get_mon_t204()
363 writel(espi->misc_ctrl | V_MONITORED_PORT_NUM(i), t1_espi_get_mon_t204()
369 writel(espi->misc_ctrl, adapter->regs + A_ESPI_MISC_CONTROL); t1_espi_get_mon_t204()
/linux-4.4.14/drivers/media/platform/s5p-jpeg/
H A Djpeg-hw-exynos3250.c26 writel(1, regs + EXYNOS3250_SW_RESET); exynos3250_jpeg_reset()
38 writel(1, regs + EXYNOS3250_JPGDRI); exynos3250_jpeg_reset()
44 writel(0, regs + EXYNOS3250_JPGDRI); exynos3250_jpeg_reset()
49 writel(EXYNOS3250_POWER_ON, regs + EXYNOS3250_JPGCLKCON); exynos3250_jpeg_poweron()
54 writel(((EXYNOS3250_DMA_MO_COUNT << EXYNOS3250_WDMA_ISSUE_NUM_SHIFT) & exynos3250_jpeg_set_dma_num()
69 writel(reg | EXYNOS3250_HALF_EN, base + EXYNOS3250_JPGCMOD); exynos3250_jpeg_clk_set()
120 writel(reg, regs + EXYNOS3250_JPGCMOD); exynos3250_jpeg_input_raw_fmt()
132 writel(reg, regs + EXYNOS3250_JPGCMOD); exynos3250_jpeg_set_y16()
146 writel(reg, regs + EXYNOS3250_JPGMOD); exynos3250_jpeg_proc_mode()
168 writel(reg, regs + EXYNOS3250_JPGMOD); exynos3250_jpeg_subsampling_mode()
182 writel(reg, regs + EXYNOS3250_JPGDRI); exynos3250_jpeg_dri()
193 writel(reg, regs + EXYNOS3250_QHTBL); exynos3250_jpeg_qtbl()
205 writel(reg, regs + EXYNOS3250_QHTBL); exynos3250_jpeg_htbl_ac()
217 writel(reg, regs + EXYNOS3250_QHTBL); exynos3250_jpeg_htbl_dc()
225 writel(reg, regs + EXYNOS3250_JPGY); exynos3250_jpeg_set_y()
233 writel(reg, regs + EXYNOS3250_JPGX); exynos3250_jpeg_set_x()
260 writel(reg, regs + EXYNOS3250_JPGINTSE); exynos3250_jpeg_interrupts_enable()
268 writel(reg, regs + EXYNOS3250_ENC_STREAM_BOUND); exynos3250_jpeg_enc_stream_bound()
316 writel(reg, regs + EXYNOS3250_OUTFORM); exynos3250_jpeg_output_raw_fmt()
321 writel(addr, regs + EXYNOS3250_JPG_JPGADR); exynos3250_jpeg_jpgadr()
326 writel(img_addr->y, regs + EXYNOS3250_LUMA_BASE); exynos3250_jpeg_imgadr()
327 writel(img_addr->cb, regs + EXYNOS3250_CHROMA_BASE); exynos3250_jpeg_imgadr()
328 writel(img_addr->cr, regs + EXYNOS3250_CHROMA_CR_BASE); exynos3250_jpeg_imgadr()
361 writel(reg_luma, regs + EXYNOS3250_LUMA_STRIDE); exynos3250_jpeg_stride()
362 writel(reg_cb, regs + EXYNOS3250_CHROMA_STRIDE); exynos3250_jpeg_stride()
363 writel(reg_cr, regs + EXYNOS3250_CHROMA_CR_STRIDE); exynos3250_jpeg_stride()
376 writel(reg, regs + EXYNOS3250_LUMA_XY_OFFSET); exynos3250_jpeg_offset()
383 writel(reg, regs + EXYNOS3250_CHROMA_XY_OFFSET); exynos3250_jpeg_offset()
390 writel(reg, regs + EXYNOS3250_CHROMA_CR_XY_OFFSET); exynos3250_jpeg_offset()
396 writel(EXYNOS3250_JPEG_ENC_COEF1, exynos3250_jpeg_coef()
398 writel(EXYNOS3250_JPEG_ENC_COEF2, exynos3250_jpeg_coef()
400 writel(EXYNOS3250_JPEG_ENC_COEF3, exynos3250_jpeg_coef()
403 writel(EXYNOS3250_JPEG_DEC_COEF1, exynos3250_jpeg_coef()
405 writel(EXYNOS3250_JPEG_DEC_COEF2, exynos3250_jpeg_coef()
407 writel(EXYNOS3250_JPEG_DEC_COEF3, exynos3250_jpeg_coef()
414 writel(1, regs + EXYNOS3250_JSTART); exynos3250_jpeg_start()
419 writel(1, regs + EXYNOS3250_JRSTART); exynos3250_jpeg_rstart()
430 return writel(value, regs + EXYNOS3250_JPGINTST); exynos3250_jpeg_clear_int_status()
446 writel(size & EXYNOS3250_DEC_STREAM_MASK, exynos3250_jpeg_dec_stream_size()
469 writel(sratio & EXYNOS3250_DEC_SCALE_FACTOR_MASK, exynos3250_jpeg_dec_scaling_ratio()
477 writel(EXYNOS3250_TIMER_INT_STAT | time_value, exynos3250_jpeg_set_timer()
488 writel(EXYNOS3250_TIMER_INT_STAT, regs + EXYNOS3250_TIMER_ST); exynos3250_jpeg_clear_timer_status()
H A Djpeg-hw-exynos4.c24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
28 writel(reg | EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_sw_reset()
38 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | exynos4_jpeg_set_enc_dec_mode()
42 writel((reg & EXYNOS4_ENC_DEC_MODE_MASK) | exynos4_jpeg_set_enc_dec_mode()
129 writel(reg, base + EXYNOS4_IMG_FMT_REG); __exynos4_jpeg_set_img_fmt()
162 writel(reg, base + EXYNOS4_IMG_FMT_REG); __exynos4_jpeg_set_enc_out_fmt()
171 writel(reg | EXYNOS4_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); exynos4_jpeg_set_interrupt()
175 writel(reg | EXYNOS5433_INT_EN_ALL, base + EXYNOS4_INT_EN_REG); exynos4_jpeg_set_interrupt()
204 writel(reg | EXYNOS4_HUF_TBL_EN, exynos4_jpeg_set_huf_table_enable()
207 writel(reg & ~EXYNOS4_HUF_TBL_EN, exynos4_jpeg_set_huf_table_enable()
218 writel(reg | EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_sys_int_enable()
220 writel(reg & ~EXYNOS4_SYS_INT_EN, base + EXYNOS4_JPEG_CNTL_REG); exynos4_jpeg_set_sys_int_enable()
226 writel(address, base + EXYNOS4_OUT_MEM_BASE_REG); exynos4_jpeg_set_stream_buf_address()
232 writel(0x0, base + EXYNOS4_JPEG_IMG_SIZE_REG); /* clear */ exynos4_jpeg_set_stream_size()
233 writel(EXYNOS4_X_SIZE(x_value) | EXYNOS4_Y_SIZE(y_value), exynos4_jpeg_set_stream_size()
240 writel(exynos4_jpeg_addr->y, base + EXYNOS4_IMG_BA_PLANE_1_REG); exynos4_jpeg_set_frame_buf_address()
241 writel(exynos4_jpeg_addr->cb, base + EXYNOS4_IMG_BA_PLANE_2_REG); exynos4_jpeg_set_frame_buf_address()
242 writel(exynos4_jpeg_addr->cr, base + EXYNOS4_IMG_BA_PLANE_3_REG); exynos4_jpeg_set_frame_buf_address()
256 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_set_encode_tbl_select()
266 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_set_dec_components()
276 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_select_dec_q_tbl()
286 writel(reg, base + EXYNOS4_TBL_SEL_REG); exynos4_jpeg_select_dec_h_tbl()
292 writel(0xd2, base + EXYNOS4_HUFF_CNT_REG); exynos4_jpeg_set_encode_hoff_cnt()
294 writel(0x1a2, base + EXYNOS4_HUFF_CNT_REG); exynos4_jpeg_set_encode_hoff_cnt()
307 writel(size, base + EXYNOS4_BITSTREAM_SIZE_REG); exynos4_jpeg_set_dec_bitstream_size()
327 writel(size, base + EXYNOS4_INT_TIMER_COUNT_REG); exynos4_jpeg_set_timer_count()
H A Djpeg-hw-s5p.c24 writel(1, regs + S5P_JPG_SW_RESET); s5p_jpeg_reset()
35 writel(S5P_POWER_ON, regs + S5P_JPGCLKCON); s5p_jpeg_poweron()
51 writel(reg, regs + S5P_JPGCMOD); s5p_jpeg_input_raw_mode()
66 writel(reg, regs + S5P_JPGMOD); s5p_jpeg_proc_mode()
81 writel(reg, regs + S5P_JPGMOD); s5p_jpeg_subsampling_mode()
96 writel(reg, regs + S5P_JPGDRI_U); s5p_jpeg_dri()
101 writel(reg, regs + S5P_JPGDRI_L); s5p_jpeg_dri()
111 writel(reg, regs + S5P_JPG_QTBL); s5p_jpeg_qtbl()
122 writel(reg, regs + S5P_JPG_HTBL); s5p_jpeg_htbl_ac()
133 writel(reg, regs + S5P_JPG_HTBL); s5p_jpeg_htbl_dc()
143 writel(reg, regs + S5P_JPGY_U); s5p_jpeg_y()
148 writel(reg, regs + S5P_JPGY_L); s5p_jpeg_y()
158 writel(reg, regs + S5P_JPGX_U); s5p_jpeg_x()
163 writel(reg, regs + S5P_JPGX_L); s5p_jpeg_x()
174 writel(reg, regs + S5P_JPGINTSE); s5p_jpeg_rst_int_enable()
185 writel(reg, regs + S5P_JPGINTSE); s5p_jpeg_data_num_int_enable()
196 writel(reg, regs + S5P_JPGINTSE); s5p_jpeg_final_mcu_num_int_enable()
211 writel(reg, regs + S5P_JPG_TIMER_SE); s5p_jpeg_clear_timer_stat()
222 writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE); s5p_jpeg_enc_stream_int()
237 writel(reg, regs + S5P_JPG_ENC_STREAM_INTSE); s5p_jpeg_clear_enc_stream_stat()
252 writel(reg, regs + S5P_JPG_OUTFORM); s5p_jpeg_outform_raw()
257 writel(addr, regs + S5P_JPG_JPGADR); s5p_jpeg_jpgadr()
262 writel(addr, regs + S5P_JPG_IMGADR); s5p_jpeg_imgadr()
273 writel(reg, regs + S5P_JPG_COEF(i)); s5p_jpeg_coef()
278 writel(1, regs + S5P_JSTART); s5p_jpeg_start()
296 writel(S5P_INT_RELEASE, regs + S5P_JPGCOM); s5p_jpeg_clear_int()
/linux-4.4.14/drivers/gpu/drm/exynos/
H A Dexynos_dp_reg.c34 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_enable_video_mute()
38 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_enable_video_mute()
48 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_stop_video()
62 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP); exynos_dp_lane_swap()
70 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1); exynos_dp_init_analog_param()
73 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2); exynos_dp_init_analog_param()
76 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); exynos_dp_init_analog_param()
80 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); exynos_dp_init_analog_param()
84 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL); exynos_dp_init_analog_param()
90 writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL); exynos_dp_init_interrupt()
93 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); exynos_dp_init_interrupt()
94 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2); exynos_dp_init_interrupt()
95 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3); exynos_dp_init_interrupt()
96 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); exynos_dp_init_interrupt()
97 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_init_interrupt()
100 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); exynos_dp_init_interrupt()
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); exynos_dp_init_interrupt()
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); exynos_dp_init_interrupt()
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); exynos_dp_init_interrupt()
104 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK); exynos_dp_init_interrupt()
117 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_reset()
122 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_reset()
128 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_reset()
129 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_reset()
130 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_reset()
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_reset()
133 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL); exynos_dp_reset()
134 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL); exynos_dp_reset()
136 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L); exynos_dp_reset()
137 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H); exynos_dp_reset()
139 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL); exynos_dp_reset()
141 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST); exynos_dp_reset()
143 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD); exynos_dp_reset()
144 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN); exynos_dp_reset()
146 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH); exynos_dp_reset()
147 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); exynos_dp_reset()
149 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_reset()
154 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET); exynos_dp_swreset()
163 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1); exynos_dp_config_interrupt()
166 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2); exynos_dp_config_interrupt()
169 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3); exynos_dp_config_interrupt()
172 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4); exynos_dp_config_interrupt()
175 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); exynos_dp_config_interrupt()
196 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); exynos_dp_set_pll_power_down()
200 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL); exynos_dp_set_pll_power_down()
215 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
219 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
226 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
230 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
237 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
241 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
248 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
252 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
259 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
263 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
270 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
274 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
281 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
283 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD); exynos_dp_set_analog_power_down()
299 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); exynos_dp_init_analog_func()
303 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL); exynos_dp_init_analog_func()
323 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_init_analog_func()
334 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4); exynos_dp_clear_hotplug_interrupts()
337 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_clear_hotplug_interrupts()
351 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_init_hpd()
388 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_reset_aux()
397 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_init_aux()
404 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL); exynos_dp_init_aux()
408 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL); exynos_dp_init_aux()
413 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2); exynos_dp_init_aux()
438 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_enable_sw_function()
450 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); exynos_dp_start_aux_transaction()
465 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_start_aux_transaction()
470 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA); exynos_dp_start_aux_transaction()
496 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_write_byte_to_dpcd()
500 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_write_byte_to_dpcd()
502 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_write_byte_to_dpcd()
504 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_write_byte_to_dpcd()
508 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0); exynos_dp_write_byte_to_dpcd()
516 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_write_byte_to_dpcd()
541 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_byte_from_dpcd()
545 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_read_byte_from_dpcd()
547 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_read_byte_from_dpcd()
549 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_read_byte_from_dpcd()
557 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_read_byte_from_dpcd()
589 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_write_bytes_to_dpcd()
602 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_write_bytes_to_dpcd()
604 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_write_bytes_to_dpcd()
606 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_write_bytes_to_dpcd()
611 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0 exynos_dp_write_bytes_to_dpcd()
622 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_write_bytes_to_dpcd()
653 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_bytes_from_dpcd()
667 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_read_bytes_from_dpcd()
669 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_read_bytes_from_dpcd()
671 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_read_bytes_from_dpcd()
680 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_read_bytes_from_dpcd()
714 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0); exynos_dp_select_i2c_device()
715 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8); exynos_dp_select_i2c_device()
716 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16); exynos_dp_select_i2c_device()
719 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0); exynos_dp_select_i2c_device()
728 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_select_i2c_device()
750 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_byte_from_i2c()
764 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1); exynos_dp_read_byte_from_i2c()
798 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL); exynos_dp_read_bytes_from_i2c()
803 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); exynos_dp_read_bytes_from_i2c()
824 writel(reg, dp->reg_base + exynos_dp_read_bytes_from_i2c()
861 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET); exynos_dp_set_link_bandwidth()
877 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET); exynos_dp_set_lane_count()
895 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_enable_enhanced_mode()
899 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_enable_enhanced_mode()
911 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
915 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
919 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
923 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
929 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_set_training_pattern()
943 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); exynos_dp_set_lane0_pre_emphasis()
953 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); exynos_dp_set_lane1_pre_emphasis()
963 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); exynos_dp_set_lane2_pre_emphasis()
973 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); exynos_dp_set_lane3_pre_emphasis()
982 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); exynos_dp_set_lane0_link_training()
991 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); exynos_dp_set_lane1_link_training()
1000 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); exynos_dp_set_lane2_link_training()
1009 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); exynos_dp_set_lane3_link_training()
1050 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); exynos_dp_reset_macro()
1056 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); exynos_dp_reset_macro()
1064 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1); exynos_dp_init_video()
1067 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_init_video()
1070 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_init_video()
1073 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_init_video()
1076 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); exynos_dp_init_video()
1087 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2); exynos_dp_set_video_color_format()
1096 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3); exynos_dp_set_video_color_format()
1104 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1); exynos_dp_is_slave_video_stream_clock_on()
1114 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2); exynos_dp_is_slave_video_stream_clock_on()
1137 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_set_video_cr_mn()
1139 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0); exynos_dp_set_video_cr_mn()
1141 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1); exynos_dp_set_video_cr_mn()
1143 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2); exynos_dp_set_video_cr_mn()
1146 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0); exynos_dp_set_video_cr_mn()
1148 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1); exynos_dp_set_video_cr_mn()
1150 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2); exynos_dp_set_video_cr_mn()
1154 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4); exynos_dp_set_video_cr_mn()
1156 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0); exynos_dp_set_video_cr_mn()
1157 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1); exynos_dp_set_video_cr_mn()
1158 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2); exynos_dp_set_video_cr_mn()
1169 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_set_video_timing_mode()
1173 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_set_video_timing_mode()
1185 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_enable_video_master()
1190 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_enable_video_master()
1200 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1); exynos_dp_start_video()
1208 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3); exynos_dp_is_video_stream_on()
1226 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1); exynos_dp_config_video_slave_mode()
1231 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1236 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1241 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10); exynos_dp_config_video_slave_mode()
1244 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); exynos_dp_config_video_slave_mode()
1253 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_enable_scrambling()
1262 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET); exynos_dp_disable_scrambling()
H A Dexynos5433_drm_decon.c78 writel(val, ctx->addr + reg); decon_set_bits()
96 writel(val, ctx->addr + DECON_VIDINTCON0); decon_enable_vblank()
110 writel(0, ctx->addr + DECON_VIDINTCON0); decon_disable_vblank()
120 writel(val, ctx->addr + DECON_TRIGCON); decon_setup_trigger()
143 writel(val, ctx->addr + DECON_CMU); decon_commit()
151 writel(val, ctx->addr + DECON_VIDOUTCON0); decon_commit()
155 writel(val, ctx->addr + DECON_VIDTCON2); decon_commit()
162 writel(val, ctx->addr + DECON_VIDTCON00); decon_commit()
166 writel(val, ctx->addr + DECON_VIDTCON01); decon_commit()
172 writel(val, ctx->addr + DECON_VIDTCON10); decon_commit()
176 writel(val, ctx->addr + DECON_VIDTCON11); decon_commit()
234 writel(val, ctx->addr + DECON_WINCONx(win)); decon_win_set_pixfmt()
273 writel(val, ctx->addr + DECON_VIDOSDxA(win)); decon_update_plane()
277 writel(val, ctx->addr + DECON_VIDOSDxB(win)); decon_update_plane()
281 writel(val, ctx->addr + DECON_VIDOSDxC(win)); decon_update_plane()
285 writel(val, ctx->addr + DECON_VIDOSDxD(win)); decon_update_plane()
287 writel(plane->dma_addr[0], ctx->addr + DECON_VIDW0xADD0B0(win)); decon_update_plane()
290 writel(val, ctx->addr + DECON_VIDW0xADD1B0(win)); decon_update_plane()
298 writel(val, ctx->addr + DECON_VIDW0xADD2(win)); decon_update_plane()
347 writel(0, ctx->addr + DECON_VIDCON0); decon_swreset()
356 writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0); decon_swreset()
368 writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0); decon_swreset()
371 writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1); decon_swreset()
372 writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN, decon_swreset()
577 writel(val, ctx->addr + DECON_VIDINTCON1); decon_irq_handler()
H A Dexynos7_drm_decon.c116 writel(val, ctx->regs + WINCON(win)); decon_clear_channels()
188 writel(val, ctx->regs + VIDTCON0); decon_commit()
191 writel(val, ctx->regs + VIDTCON1); decon_commit()
200 writel(val, ctx->regs + VIDTCON2); decon_commit()
203 writel(val, ctx->regs + VIDTCON3); decon_commit()
209 writel(val, ctx->regs + VIDTCON4); decon_commit()
211 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD); decon_commit()
218 writel(val, ctx->regs + VIDCON0); decon_commit()
223 writel(val, ctx->regs + VCLKCON1); decon_commit()
224 writel(val, ctx->regs + VCLKCON2); decon_commit()
229 writel(val, ctx->regs + DECON_UPDATE); decon_commit()
251 writel(val, ctx->regs + VIDINTCON0); decon_enable_vblank()
272 writel(val, ctx->regs + VIDINTCON0); decon_disable_vblank()
350 writel(val, ctx->regs + WINCON(win)); decon_win_set_pixfmt()
362 writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); decon_win_set_colkey()
363 writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); decon_win_set_colkey()
384 writel(val, ctx->regs + SHADOWCON); decon_shadow_protect_win()
427 writel(val, ctx->regs + VIDW_BUF_START(win)); decon_update_plane()
432 writel(state->fb->width + padding, ctx->regs + VIDW_WHOLE_X(win)); decon_update_plane()
433 writel(state->fb->height, ctx->regs + VIDW_WHOLE_Y(win)); decon_update_plane()
436 writel(plane->src_x, ctx->regs + VIDW_OFFSET_X(win)); decon_update_plane()
437 writel(plane->src_y, ctx->regs + VIDW_OFFSET_Y(win)); decon_update_plane()
455 writel(val, ctx->regs + VIDOSD_A(win)); decon_update_plane()
466 writel(val, ctx->regs + VIDOSD_B(win)); decon_update_plane()
476 writel(alpha, ctx->regs + VIDOSD_C(win)); decon_update_plane()
482 writel(alpha, ctx->regs + VIDOSD_D(win)); decon_update_plane()
494 writel(val, ctx->regs + WINCON(win)); decon_update_plane()
501 writel(val, ctx->regs + DECON_UPDATE); decon_update_plane()
520 writel(val, ctx->regs + WINCON(win)); decon_disable_plane()
524 writel(val, ctx->regs + DECON_UPDATE); decon_disable_plane()
542 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0); decon_init()
547 writel(val, ctx->regs + VIDOUTCON0); decon_init()
549 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0); decon_init()
552 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0)); decon_init()
650 writel(clear_bit, ctx->regs + VIDINTCON1); decon_irq_handler()
/linux-4.4.14/drivers/video/fbdev/via/
H A Daccel.c48 writel(gemode, engine + VIA_REG_GEMODE); viafb_set_bpp()
105 writel(tmp, engine + 0x08); hw_bitblt_1()
114 writel(tmp, engine + 0x0C); hw_bitblt_1()
122 writel(tmp, engine + 0x10); hw_bitblt_1()
125 writel(fg_color, engine + 0x18); hw_bitblt_1()
128 writel(bg_color, engine + 0x1C); hw_bitblt_1()
138 writel(tmp, engine + 0x30); hw_bitblt_1()
147 writel(tmp, engine + 0x34); hw_bitblt_1()
159 writel(tmp, engine + 0x38); hw_bitblt_1()
172 writel(ge_cmd, engine); hw_bitblt_1()
181 writel(src_mem[i], engine + VIA_MMIO_BLTBASE); hw_bitblt_1()
240 writel(tmp, engine + 0x08); hw_bitblt_2()
248 writel(tmp, engine + 0x0C); hw_bitblt_2()
256 writel(tmp, engine + 0x10); hw_bitblt_2()
264 writel(tmp, engine + 0x14); hw_bitblt_2()
274 writel(tmp, engine + 0x18); hw_bitblt_2()
283 writel(tmp, engine + 0x1C); hw_bitblt_2()
287 writel(fg_color, engine + 0x58); hw_bitblt_2()
289 writel(fg_color, engine + 0x4C); hw_bitblt_2()
290 writel(bg_color, engine + 0x50); hw_bitblt_2()
304 writel(ge_cmd, engine); hw_bitblt_2()
313 writel(src_mem[i], engine + VIA_MMIO_BLTBASE); hw_bitblt_2()
398 writel(0x0, engine + i); viafb_reset_engine()
407 writel(0x00100000, engine + VIA_REG_CR_TRANSET); viafb_reset_engine()
408 writel(0x680A0000, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
409 writel(0x02000000, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
413 writel(0x00100000, engine + VIA_REG_TRANSET); viafb_reset_engine()
414 writel(0x00000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
415 writel(0x00333004, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
416 writel(0x60000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
417 writel(0x61000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
418 writel(0x62000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
419 writel(0x63000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
420 writel(0x64000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
421 writel(0x7D000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
423 writel(0xFE020000, engine + VIA_REG_TRANSET); viafb_reset_engine()
424 writel(0x00000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
449 writel(0x00100000, engine + VIA_REG_CR_TRANSET); viafb_reset_engine()
450 writel(vq_high, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
451 writel(vq_start_low, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
452 writel(vq_end_low, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
453 writel(vq_len, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
454 writel(0x74301001, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
455 writel(0x00000000, engine + VIA_REG_CR_TRANSPACE); viafb_reset_engine()
458 writel(0x00FE0000, engine + VIA_REG_TRANSET); viafb_reset_engine()
459 writel(0x080003FE, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
460 writel(0x0A00027C, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
461 writel(0x0B000260, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
462 writel(0x0C000274, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
463 writel(0x0D000264, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
464 writel(0x0E000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
465 writel(0x0F000020, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
466 writel(0x1000027E, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
467 writel(0x110002FE, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
468 writel(0x200F0060, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
470 writel(0x00000006, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
471 writel(0x40008C0F, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
472 writel(0x44000000, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
473 writel(0x45080C04, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
474 writel(0x46800408, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
476 writel(vq_high, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
477 writel(vq_start_low, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
478 writel(vq_end_low, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
479 writel(vq_len, engine + VIA_REG_TRANSPACE); viafb_reset_engine()
484 writel(viapar->shared->cursor_vram_addr, engine + VIA_REG_CURSOR_MODE); viafb_reset_engine()
485 writel(0x0, engine + VIA_REG_CURSOR_POS); viafb_reset_engine()
486 writel(0x0, engine + VIA_REG_CURSOR_ORG); viafb_reset_engine()
487 writel(0x0, engine + VIA_REG_CURSOR_BG); viafb_reset_engine()
488 writel(0x0, engine + VIA_REG_CURSOR_FG); viafb_reset_engine()
514 writel(temp, viapar->shared->vdev->engine_mmio + VIA_REG_CURSOR_MODE); viafb_show_hw_cursor()
/linux-4.4.14/arch/arm/mach-netx/
H A Dtime.c40 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); timer_shutdown()
55 writel(0, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); netx_set_oneshot()
56 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); netx_set_oneshot()
67 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKEVENT)); netx_set_periodic()
68 writel(tmode, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKEVENT)); netx_set_periodic()
76 writel(0 - evt, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKEVENT)); netx_set_next_event()
99 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); netx_timer_interrupt()
118 writel(0, NETX_GPIO_COUNTER_CTRL(0)); netx_timer_init()
121 writel(0, NETX_GPIO_COUNTER_CURRENT(0)); netx_timer_init()
123 writel(NETX_LATCH, NETX_GPIO_COUNTER_MAX(0)); netx_timer_init()
126 writel(COUNTER_BIT(0), NETX_GPIO_IRQ); netx_timer_init()
131 writel(COUNTER_BIT(0), NETX_GPIO_IRQ_ENABLE); netx_timer_init()
132 writel(NETX_GPIO_COUNTER_CTRL_IRQ_EN | NETX_GPIO_COUNTER_CTRL_RUN, netx_timer_init()
138 writel(0, NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE)); netx_timer_init()
139 writel(0, NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE)); netx_timer_init()
140 writel(0xffffffff, NETX_GPIO_COUNTER_MAX(TIMER_CLOCKSOURCE)); netx_timer_init()
142 writel(NETX_GPIO_COUNTER_CTRL_RUN, netx_timer_init()
H A Dgeneric.c116 writel(val, NETX_DPMAS_IF_CONF1); netx_hif_irq_type()
127 writel((1 << 24) << irq, NETX_DPMAS_INT_STAT); netx_hif_ack_irq()
131 writel(val, NETX_DPMAS_INT_EN); netx_hif_ack_irq()
144 writel(val, NETX_DPMAS_INT_EN); netx_hif_mask_irq()
156 writel(val, NETX_DPMAS_INT_EN); netx_hif_unmask_irq()
179 writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); netx_init_irq()
192 writel(NETX_SYSTEM_RES_CR_FIRMW_RES_EN | NETX_SYSTEM_RES_CR_FIRMW_RES, netx_restart()
H A Dxc.c55 writel(RPU_HOLD_PC, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS); xc_stop()
56 writel(TPU_HOLD_PC, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS); xc_stop()
57 writel(XPU_HOLD_PC, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS); xc_stop()
63 writel(0, x->xmac_base + NETX_XMAC_RPU_HOLD_PC_OFS); xc_start()
64 writel(0, x->xmac_base + NETX_XMAC_TPU_HOLD_PC_OFS); xc_start()
65 writel(0, x->xpec_base + NETX_XPEC_XPU_HOLD_PC_OFS); xc_start()
79 writel(0, x->xpec_base + NETX_XPEC_PC_OFS); xc_reset()
110 writel(val, (void __iomem *)io_p2v(adr)); xc_patch()
H A Dnxeb500hmi.c78 writel(val, NETX_SYSTEM_IOC_ACCESS_KEY); nxeb500hmi_clcd_setup()
80 writel(3, NETX_SYSTEM_IOC_CR); nxeb500hmi_clcd_setup()
83 writel(9, NETX_GPIO_CFG(14)); nxeb500hmi_clcd_setup()
86 writel(val | 1, NETX_PIO_OUTPIO); nxeb500hmi_clcd_setup()
89 writel(val | 1, NETX_PIO_OEPIO); nxeb500hmi_clcd_setup()
/linux-4.4.14/drivers/scsi/bfa/
H A Dbfa_ioc_ct.c73 writel(1, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_firmware_lock()
75 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); bfa_ioc_ct_firmware_lock()
76 writel(0, ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_firmware_lock()
95 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); bfa_ioc_ct_firmware_lock()
104 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_firmware_lock()
106 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); bfa_ioc_ct_firmware_lock()
124 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_firmware_unlock()
128 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); bfa_ioc_ct_firmware_unlock()
138 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); bfa_ioc_ct_notify_fail()
139 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); bfa_ioc_ct_notify_fail()
144 writel(~0U, ioc->ioc_regs.err_set); bfa_ioc_ct_notify_fail()
371 writel(r32, rb + FNC_PERS_REG); bfa_ioc_ct_isr_mode_set()
381 writel(1, ioc->ioc_regs.lpu_read_stat); bfa_ioc_ct2_lpu_read_stat()
396 writel(0, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_ownership_reset()
398 writel(1, ioc->ioc_regs.ioc_usage_sem_reg); bfa_ioc_ct_ownership_reset()
400 writel(0, ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_ownership_reset()
407 writel(1, ioc->ioc_regs.ioc_sem_reg); bfa_ioc_ct_ownership_reset()
424 writel(0, ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_start()
425 writel(1, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_sync_start()
426 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); bfa_ioc_ct_sync_start()
427 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_ct_sync_start()
443 writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_join()
453 writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_leave()
461 writel((r32 | bfa_ioc_ct_sync_pos(ioc)), bfa_ioc_ct_sync_ack()
488 writel(bfa_ioc_ct_clear_sync_ackd(r32), bfa_ioc_ct_sync_complete()
490 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate); bfa_ioc_ct_sync_complete()
491 writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_ct_sync_complete()
501 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_complete()
576 writel(r32 & __MSIX_VT_OFST_, bfa_ioc_ct2_poweron()
581 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | bfa_ioc_ct2_poweron()
584 writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc), bfa_ioc_ct2_poweron()
604 writel(0, (rb + OP_MODE)); bfa_ioc_ct_pll_init()
605 writel(__APP_EMS_CMLCKSEL | __APP_EMS_REFCKBUFEN2 | bfa_ioc_ct_pll_init()
608 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); bfa_ioc_ct_pll_init()
609 writel(__APP_EMS_REFCKBUFEN1, (rb + ETH_MAC_SER_REG)); bfa_ioc_ct_pll_init()
611 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); bfa_ioc_ct_pll_init()
612 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); bfa_ioc_ct_pll_init()
613 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); bfa_ioc_ct_pll_init()
614 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); bfa_ioc_ct_pll_init()
615 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); bfa_ioc_ct_pll_init()
616 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); bfa_ioc_ct_pll_init()
617 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); bfa_ioc_ct_pll_init()
618 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); bfa_ioc_ct_pll_init()
619 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET, bfa_ioc_ct_pll_init()
621 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET, bfa_ioc_ct_pll_init()
623 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET | bfa_ioc_ct_pll_init()
625 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET | bfa_ioc_ct_pll_init()
629 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); bfa_ioc_ct_pll_init()
630 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); bfa_ioc_ct_pll_init()
631 writel(pll_sclk | __APP_PLL_SCLK_ENABLE, rb + APP_PLL_SCLK_CTL_REG); bfa_ioc_ct_pll_init()
632 writel(pll_fclk | __APP_PLL_LCLK_ENABLE, rb + APP_PLL_LCLK_CTL_REG); bfa_ioc_ct_pll_init()
635 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); bfa_ioc_ct_pll_init()
636 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); bfa_ioc_ct_pll_init()
640 writel(r32, (rb + PSS_CTL_REG)); bfa_ioc_ct_pll_init()
643 writel(0, (rb + PMM_1T_RESET_REG_P0)); bfa_ioc_ct_pll_init()
644 writel(0, (rb + PMM_1T_RESET_REG_P1)); bfa_ioc_ct_pll_init()
647 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); bfa_ioc_ct_pll_init()
650 writel(0, (rb + MBIST_CTL_REG)); bfa_ioc_ct_pll_init()
666 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); bfa_ioc_ct2_sclk_init()
674 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); bfa_ioc_ct2_sclk_init()
680 writel(r32 | __ETH_CLK_ENABLE_PORT0, (rb + CT2_CHIP_MISC_PRG)); bfa_ioc_ct2_sclk_init()
683 writel(r32 | __ETH_CLK_ENABLE_PORT1, (rb + CT2_PCIE_MISC_REG)); bfa_ioc_ct2_sclk_init()
691 writel(r32 | 0x1061731b, (rb + CT2_APP_PLL_SCLK_CTL_REG)); bfa_ioc_ct2_sclk_init()
711 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); bfa_ioc_ct2_lclk_init()
717 writel(r32, (rb + CT2_CHIP_MISC_PRG)); bfa_ioc_ct2_lclk_init()
723 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); bfa_ioc_ct2_lclk_init()
731 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); bfa_ioc_ct2_lclk_init()
746 writel(r32, (rb + PSS_CTL_REG)); bfa_ioc_ct2_mem_init()
749 writel(__EDRAM_BISTR_START, (rb + CT2_MBIST_CTL_REG)); bfa_ioc_ct2_mem_init()
751 writel(0, (rb + CT2_MBIST_CTL_REG)); bfa_ioc_ct2_mem_init()
758 writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET), bfa_ioc_ct2_mac_reset()
760 writel((__CSI_MAC_RESET | __CSI_MAC_AHB_RESET), bfa_ioc_ct2_mac_reset()
770 writel(r32 & ~1, (rb + PSS_GPIO_OUT_REG)); bfa_ioc_ct2_enable_flash()
772 writel(r32 | 1, (rb + PSS_GPIO_OE_REG)); bfa_ioc_ct2_enable_flash()
798 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_SET_REG); bfa_ioc_ct2_nfc_halt()
813 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); bfa_ioc_ct2_nfc_resume()
835 writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET, bfa_ioc_ct2_clk_reset()
839 writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET, bfa_ioc_ct2_clk_reset()
851 writel(r32, (rb + PSS_CTL_REG)); bfa_ioc_ct2_nfc_clk_reset()
853 writel(__RESET_AND_START_SCLK_LCLK_PLLS, rb + CT2_CSI_FW_CTL_SET_REG); bfa_ioc_ct2_nfc_clk_reset()
940 writel((r32 & 0xfbffffff), (rb + CT2_CHIP_MISC_PRG)); bfa_ioc_ct2_pll_init()
947 writel(1, (rb + CT2_LPU0_HOSTFN_MBOX0_MSK)); bfa_ioc_ct2_pll_init()
948 writel(1, (rb + CT2_LPU1_HOSTFN_MBOX0_MSK)); bfa_ioc_ct2_pll_init()
955 writel(1, (rb + CT2_LPU0_HOSTFN_CMD_STAT)); bfa_ioc_ct2_pll_init()
960 writel(1, (rb + CT2_LPU1_HOSTFN_CMD_STAT)); bfa_ioc_ct2_pll_init()
967 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC0_STATE_REG)); bfa_ioc_ct2_pll_init()
968 writel(BFI_IOC_UNINIT, (rb + CT2_BFA_IOC1_STATE_REG)); bfa_ioc_ct2_pll_init()
977 writel(fwstate, ioc->ioc_regs.ioc_fwstate); bfa_ioc_ct_set_cur_ioc_fwstate()
990 writel(fwstate, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_ct_set_alt_ioc_fwstate()
H A Dbfa_ioc_cb.c121 writel(~0U, ioc->ioc_regs.err_set); bfa_ioc_cb_notify_fail()
234 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); bfa_ioc_cb_sync_start()
235 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_cb_sync_start()
255 writel(1, ioc->ioc_regs.ioc_sem_reg); bfa_ioc_cb_ownership_reset()
267 writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate); bfa_ioc_cb_sync_join()
276 writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate); bfa_ioc_cb_sync_leave()
285 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), bfa_ioc_cb_set_cur_ioc_fwstate()
302 writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)), bfa_ioc_cb_set_alt_ioc_fwstate()
378 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG)); bfa_ioc_cb_pll_init()
381 writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG)); bfa_ioc_cb_pll_init()
382 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); bfa_ioc_cb_pll_init()
383 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); bfa_ioc_cb_pll_init()
384 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); bfa_ioc_cb_pll_init()
385 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); bfa_ioc_cb_pll_init()
386 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); bfa_ioc_cb_pll_init()
387 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); bfa_ioc_cb_pll_init()
388 writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); bfa_ioc_cb_pll_init()
389 writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET, bfa_ioc_cb_pll_init()
391 writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); bfa_ioc_cb_pll_init()
392 writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET, bfa_ioc_cb_pll_init()
395 writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG); bfa_ioc_cb_pll_init()
396 writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG); bfa_ioc_cb_pll_init()
397 writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET, bfa_ioc_cb_pll_init()
399 writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET, bfa_ioc_cb_pll_init()
402 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); bfa_ioc_cb_pll_init()
403 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); bfa_ioc_cb_pll_init()
404 writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG)); bfa_ioc_cb_pll_init()
405 writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG)); bfa_ioc_cb_pll_init()
/linux-4.4.14/arch/arm/mach-gemini/
H A Dtime.c78 writel(cr + cycles, TIMER_MATCH1(TIMER1_BASE)); gemini_timer_set_next_event()
96 writel(cr, TIMER_CR); gemini_timer_shutdown()
99 writel(0, TIMER_COUNT(TIMER1_BASE)); gemini_timer_shutdown()
100 writel(0, TIMER_LOAD(TIMER1_BASE)); gemini_timer_shutdown()
106 writel(cr, TIMER_INTR_MASK); gemini_timer_shutdown()
111 writel(cr, TIMER_CR); gemini_timer_shutdown()
124 writel(cr, TIMER_CR); gemini_timer_set_periodic()
128 writel(cr, TIMER_COUNT(TIMER1_BASE)); gemini_timer_set_periodic()
129 writel(cr, TIMER_LOAD(TIMER1_BASE)); gemini_timer_set_periodic()
135 writel(cr, TIMER_INTR_MASK); gemini_timer_set_periodic()
141 writel(cr, TIMER_CR); gemini_timer_set_periodic()
210 writel(TIMER_INT_ALL_MASK, TIMER_INTR_MASK); gemini_timer_init()
211 writel(0, TIMER_INTR_STATE); gemini_timer_init()
212 writel(TIMER_DEFAULT_FLAGS, TIMER_CR); gemini_timer_init()
218 writel(0, TIMER_COUNT(TIMER3_BASE)); gemini_timer_init()
219 writel(0, TIMER_LOAD(TIMER3_BASE)); gemini_timer_init()
220 writel(0, TIMER_MATCH1(TIMER3_BASE)); gemini_timer_init()
221 writel(0, TIMER_MATCH2(TIMER3_BASE)); gemini_timer_init()
230 writel(0, TIMER_COUNT(TIMER1_BASE)); gemini_timer_init()
231 writel(0, TIMER_LOAD(TIMER1_BASE)); gemini_timer_init()
232 writel(0, TIMER_MATCH1(TIMER1_BASE)); gemini_timer_init()
233 writel(0, TIMER_MATCH2(TIMER1_BASE)); gemini_timer_init()
/linux-4.4.14/sound/soc/ux500/
H A Dux500_msp_i2s.c144 writel(temp_reg, msp->registers + MSP_TCF); set_prot_desc_tx()
172 writel(temp_reg, msp->registers + MSP_RCF); set_prot_desc_rx()
211 writel(temp_reg, msp->registers + MSP_GCR); configure_protocol()
214 writel(temp_reg, msp->registers + MSP_GCR); configure_protocol()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); setup_bitclk()
261 writel(temp_reg, msp->registers + MSP_SRG); setup_bitclk()
268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); setup_bitclk()
298 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? configure_multichannel()
301 writel(mcfg->tx_channel_0_enable, configure_multichannel()
303 writel(mcfg->tx_channel_1_enable, configure_multichannel()
305 writel(mcfg->tx_channel_2_enable, configure_multichannel()
307 writel(mcfg->tx_channel_3_enable, configure_multichannel()
319 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? configure_multichannel()
322 writel(mcfg->rx_channel_0_enable, configure_multichannel()
324 writel(mcfg->rx_channel_1_enable, configure_multichannel()
326 writel(mcfg->rx_channel_2_enable, configure_multichannel()
328 writel(mcfg->rx_channel_3_enable, configure_multichannel()
338 writel(reg_val_MCR | configure_multichannel()
342 writel(mcfg->comparison_mask, configure_multichannel()
344 writel(mcfg->comparison_value, configure_multichannel()
388 writel(reg_val_DMACR, msp->registers + MSP_DMACR); enable_msp()
390 writel(config->iodelay, msp->registers + MSP_IODLY); enable_msp()
394 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); enable_msp()
405 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); flush_fifo_rx()
413 writel(reg_val_GCR, msp->registers + MSP_GCR); flush_fifo_rx()
422 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); flush_fifo_tx()
423 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); flush_fifo_tx()
430 writel(0x0, msp->registers + MSP_ITCR); flush_fifo_tx()
431 writel(reg_val_GCR, msp->registers + MSP_GCR); flush_fifo_tx()
485 writel(new_reg, msp->registers + MSP_GCR); ux500_msp_i2s_open()
509 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); disable_msp_rx()
511 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); disable_msp_rx()
513 writel(reg_val_IMSC & disable_msp_rx()
525 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); disable_msp_tx()
527 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); disable_msp_tx()
529 writel(reg_val_IMSC & disable_msp_tx()
547 writel(reg_val_GCR | LOOPBACK_MASK, disable_msp()
554 writel((readl(msp->registers + MSP_GCR) & disable_msp()
561 writel((readl(msp->registers + MSP_GCR) & disable_msp()
594 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); ux500_msp_i2s_trigger()
623 writel((readl(msp->registers + MSP_GCR) & ux500_msp_i2s_close()
627 writel(0, msp->registers + MSP_GCR); ux500_msp_i2s_close()
628 writel(0, msp->registers + MSP_TCF); ux500_msp_i2s_close()
629 writel(0, msp->registers + MSP_RCF); ux500_msp_i2s_close()
630 writel(0, msp->registers + MSP_DMACR); ux500_msp_i2s_close()
631 writel(0, msp->registers + MSP_SRG); ux500_msp_i2s_close()
632 writel(0, msp->registers + MSP_MCR); ux500_msp_i2s_close()
633 writel(0, msp->registers + MSP_RCM); ux500_msp_i2s_close()
634 writel(0, msp->registers + MSP_RCV); ux500_msp_i2s_close()
635 writel(0, msp->registers + MSP_TCE0); ux500_msp_i2s_close()
636 writel(0, msp->registers + MSP_TCE1); ux500_msp_i2s_close()
637 writel(0, msp->registers + MSP_TCE2); ux500_msp_i2s_close()
638 writel(0, msp->registers + MSP_TCE3); ux500_msp_i2s_close()
639 writel(0, msp->registers + MSP_RCE0); ux500_msp_i2s_close()
640 writel(0, msp->registers + MSP_RCE1); ux500_msp_i2s_close()
641 writel(0, msp->registers + MSP_RCE2); ux500_msp_i2s_close()
642 writel(0, msp->registers + MSP_RCE3); ux500_msp_i2s_close()
/linux-4.4.14/drivers/net/ethernet/brocade/bna/
H A Dbfa_ioc_ct.c139 writel(1, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_firmware_lock()
141 writel(0, ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_firmware_lock()
165 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_firmware_lock()
190 writel(usecnt, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_firmware_unlock()
199 writel(__FW_INIT_HALT_P, ioc->ioc_regs.ll_halt); bfa_ioc_ct_notify_fail()
200 writel(__FW_INIT_HALT_P, ioc->ioc_regs.alt_ll_halt); bfa_ioc_ct_notify_fail()
427 writel(r32, rb + FNC_PERS_REG); bfa_ioc_ct_isr_mode_set()
437 writel(1, ioc->ioc_regs.lpu_read_stat); bfa_ioc_ct2_lpu_read_stat()
460 writel(r32 & __MSIX_VT_OFST_, bfa_nw_ioc_ct2_poweron()
465 writel(__MSIX_VT_NUMVT_(HOSTFN_MSIX_DEFAULT - 1) | bfa_nw_ioc_ct2_poweron()
468 writel(HOSTFN_MSIX_DEFAULT * bfa_ioc_pcifn(ioc), bfa_nw_ioc_ct2_poweron()
477 writel(0, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_ownership_reset()
504 writel(0, ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_start()
505 writel(1, ioc->ioc_regs.ioc_usage_reg); bfa_ioc_ct_sync_start()
506 writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate); bfa_ioc_ct_sync_start()
507 writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_ct_sync_start()
520 writel((r32 | sync_pos), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_join()
530 writel((r32 & ~sync_msk), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_leave()
538 writel(r32 | bfa_ioc_ct_sync_pos(ioc), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_ack()
564 writel(bfa_ioc_ct_clear_sync_ackd(r32), bfa_ioc_ct_sync_complete()
566 writel(BFI_IOC_FAIL, ioc->ioc_regs.ioc_fwstate); bfa_ioc_ct_sync_complete()
567 writel(BFI_IOC_FAIL, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_ct_sync_complete()
577 writel((r32 | sync_ackd), ioc->ioc_regs.ioc_fail_sync); bfa_ioc_ct_sync_complete()
586 writel(fwstate, ioc->ioc_regs.ioc_fwstate); bfa_ioc_ct_set_cur_ioc_fwstate()
599 writel(fwstate, ioc->ioc_regs.alt_ioc_fwstate); bfa_ioc_ct_set_alt_ioc_fwstate()
624 writel(0, (rb + OP_MODE)); bfa_ioc_ct_pll_init()
625 writel(__APP_EMS_CMLCKSEL | bfa_ioc_ct_pll_init()
630 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); bfa_ioc_ct_pll_init()
631 writel(__APP_EMS_REFCKBUFEN1, bfa_ioc_ct_pll_init()
634 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); bfa_ioc_ct_pll_init()
635 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); bfa_ioc_ct_pll_init()
636 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); bfa_ioc_ct_pll_init()
637 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); bfa_ioc_ct_pll_init()
638 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); bfa_ioc_ct_pll_init()
639 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); bfa_ioc_ct_pll_init()
640 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); bfa_ioc_ct_pll_init()
641 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); bfa_ioc_ct_pll_init()
642 writel(pll_sclk | bfa_ioc_ct_pll_init()
645 writel(pll_fclk | bfa_ioc_ct_pll_init()
648 writel(pll_sclk | bfa_ioc_ct_pll_init()
651 writel(pll_fclk | bfa_ioc_ct_pll_init()
656 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); bfa_ioc_ct_pll_init()
657 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); bfa_ioc_ct_pll_init()
658 writel(pll_sclk | bfa_ioc_ct_pll_init()
661 writel(pll_fclk | bfa_ioc_ct_pll_init()
666 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); bfa_ioc_ct_pll_init()
667 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); bfa_ioc_ct_pll_init()
671 writel(r32, (rb + PSS_CTL_REG)); bfa_ioc_ct_pll_init()
674 writel(0, (rb + PMM_1T_RESET_REG_P0)); bfa_ioc_ct_pll_init()
675 writel(0, (rb + PMM_1T_RESET_REG_P1)); bfa_ioc_ct_pll_init()
678 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); bfa_ioc_ct_pll_init()
681 writel(0, (rb + MBIST_CTL_REG)); bfa_ioc_ct_pll_init()
697 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); bfa_ioc_ct2_sclk_init()
705 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); bfa_ioc_ct2_sclk_init()
711 writel(r32 | __ETH_CLK_ENABLE_PORT0, bfa_ioc_ct2_sclk_init()
715 writel(r32 | __ETH_CLK_ENABLE_PORT1, bfa_ioc_ct2_sclk_init()
724 writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG); bfa_ioc_ct2_sclk_init()
749 writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); bfa_ioc_ct2_lclk_init()
755 writel(r32, (rb + CT2_CHIP_MISC_PRG)); bfa_ioc_ct2_lclk_init()
761 writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); bfa_ioc_ct2_lclk_init()
769 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); bfa_ioc_ct2_lclk_init()
784 writel(r32, rb + PSS_CTL_REG); bfa_ioc_ct2_mem_init()
787 writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG); bfa_ioc_ct2_mem_init()
789 writel(0, rb + CT2_MBIST_CTL_REG); bfa_ioc_ct2_mem_init()
804 writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET, bfa_ioc_ct2_mac_reset()
811 writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET, bfa_ioc_ct2_mac_reset()
815 writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET, bfa_ioc_ct2_mac_reset()
817 writel(__CSI_MAC_RESET | __CSI_MAC_AHB_RESET, bfa_ioc_ct2_mac_reset()
843 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); bfa_ioc_ct2_nfc_resume()
867 writel(__RESET_AND_START_SCLK_LCLK_PLLS, bfa_ioc_ct2_pll_init()
888 writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG)); bfa_ioc_ct2_pll_init()
902 writel(r32 & ~__APP_PLL_SCLK_LOGIC_SOFT_RESET, bfa_ioc_ct2_pll_init()
905 writel(r32 & ~__APP_PLL_LCLK_LOGIC_SOFT_RESET, bfa_ioc_ct2_pll_init()
912 writel(r32 & ~1, rb + PSS_GPIO_OUT_REG); bfa_ioc_ct2_pll_init()
914 writel(r32 | 1, rb + PSS_GPIO_OE_REG); bfa_ioc_ct2_pll_init()
921 writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK); bfa_ioc_ct2_pll_init()
922 writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK); bfa_ioc_ct2_pll_init()
929 writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT); bfa_ioc_ct2_pll_init()
934 writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT); bfa_ioc_ct2_pll_init()
941 writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG); bfa_ioc_ct2_pll_init()
942 writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG); bfa_ioc_ct2_pll_init()
/linux-4.4.14/drivers/irqchip/
H A Dirq-sun4i.c47 writel(BIT(0), sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); sun4i_irq_ack()
58 writel(val & ~(1 << irq_off), sun4i_irq_mask()
70 writel(val | (1 << irq_off), sun4i_irq_unmask()
105 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0)); sun4i_of_init()
106 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1)); sun4i_of_init()
107 writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2)); sun4i_of_init()
110 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0)); sun4i_of_init()
111 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1)); sun4i_of_init()
112 writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2)); sun4i_of_init()
115 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0)); sun4i_of_init()
116 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1)); sun4i_of_init()
117 writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2)); sun4i_of_init()
120 writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG); sun4i_of_init()
123 writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG); sun4i_of_init()
H A Dirq-armada-370-xp.c97 writel(hwirq, main_int_base + armada_370_xp_irq_mask()
100 writel(hwirq, per_cpu_int_base + armada_370_xp_irq_mask()
109 writel(hwirq, main_int_base + armada_370_xp_irq_unmask()
112 writel(hwirq, per_cpu_int_base + armada_370_xp_irq_unmask()
242 writel(reg, per_cpu_int_base + armada_370_xp_msi_init()
246 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); armada_370_xp_msi_init()
275 writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); armada_xp_set_affinity()
298 writel(hw, per_cpu_int_base + armada_370_xp_mpic_irq_map()
301 writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS); armada_370_xp_mpic_irq_map()
328 writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS); armada_xp_mpic_smp_cpu_init()
331 writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS); armada_xp_mpic_smp_cpu_init()
334 writel(IPI_DOORBELL_MASK, per_cpu_int_base + armada_xp_mpic_smp_cpu_init()
338 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); armada_xp_mpic_smp_cpu_init()
346 writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid), armada_xp_mpic_perf_init()
368 writel((map << 8) | irq, main_int_base + armada_mpic_send_doorbell()
419 writel(~msimask, per_cpu_int_base + armada_370_xp_handle_msi_irq()
509 writel(~ipimask, per_cpu_int_base + armada_370_xp_handle_irq()
548 writel(irq, per_cpu_int_base + armada_370_xp_mpic_resume()
551 writel(irq, main_int_base + armada_370_xp_mpic_resume()
560 writel(doorbell_mask_reg, armada_370_xp_mpic_resume()
563 writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); armada_370_xp_mpic_resume()
565 writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS); armada_370_xp_mpic_resume()
602 writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS); armada_370_xp_mpic_of_init()
H A Dirq-vic.c105 writel(VIC_VECT_CNTL_ENABLE | i, reg); vic_init2()
108 writel(32, base + VIC_PL190_DEF_VECT_ADDR); vic_init2()
121 writel(vic->int_select, base + VIC_INT_SELECT); resume_one_vic()
122 writel(vic->protect, base + VIC_PROTECT); resume_one_vic()
125 writel(vic->int_enable, base + VIC_INT_ENABLE); resume_one_vic()
126 writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR); resume_one_vic()
130 writel(vic->soft_int, base + VIC_INT_SOFT); resume_one_vic()
131 writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR); resume_one_vic()
156 writel(vic->resume_irqs, base + VIC_INT_ENABLE); suspend_one_vic()
157 writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR); suspend_one_vic()
320 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); vic_ack_irq()
322 writel(1 << irq, base + VIC_INT_SOFT_CLEAR); vic_ack_irq()
329 writel(1 << irq, base + VIC_INT_ENABLE_CLEAR); vic_mask_irq()
336 writel(1 << irq, base + VIC_INT_ENABLE); vic_unmask_irq()
387 writel(0, base + VIC_INT_SELECT); vic_disable()
388 writel(0, base + VIC_INT_ENABLE); vic_disable()
389 writel(~0, base + VIC_INT_ENABLE_CLEAR); vic_disable()
390 writel(0, base + VIC_ITCR); vic_disable()
391 writel(~0, base + VIC_INT_SOFT_CLEAR); vic_disable()
398 writel(0, base + VIC_PL190_VECT_ADDR); vic_clear_interrupts()
403 writel(value, base + VIC_PL190_VECT_ADDR); vic_clear_interrupts()
435 writel(0, reg); vic_init_st()
438 writel(32, base + VIC_PL190_DEF_VECT_ADDR); vic_init_st()
H A Dirq-moxart.c106 writel(0, intc.base + IRQ_MASK_REG); moxart_of_intc_init()
107 writel(0xffffffff, intc.base + IRQ_CLEAR_REG); moxart_of_intc_init()
109 writel(intc.interrupt_mask, intc.base + IRQ_MODE_REG); moxart_of_intc_init()
110 writel(intc.interrupt_mask, intc.base + IRQ_LEVEL_REG); moxart_of_intc_init()
/linux-4.4.14/drivers/gpu/drm/sti/
H A Dsti_vid.c65 writel(val, vid->regs + VID_CTL); sti_vid_commit()
72 writel((ydo << 16) | xdo, vid->regs + VID_VPO); sti_vid_commit()
73 writel((yds << 16) | xds, vid->regs + VID_VPS); sti_vid_commit()
83 writel(val, vid->regs + VID_CTL); sti_vid_disable()
89 writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL); sti_vid_init()
92 writel(VID_ALP_OPAQUE, vid->regs + VID_ALP); sti_vid_init()
95 writel(VID_MPR0_BT709, vid->regs + VID_MPR0); sti_vid_init()
96 writel(VID_MPR1_BT709, vid->regs + VID_MPR1); sti_vid_init()
97 writel(VID_MPR2_BT709, vid->regs + VID_MPR2); sti_vid_init()
98 writel(VID_MPR3_BT709, vid->regs + VID_MPR3); sti_vid_init()
101 writel(VID_BC_DFLT, vid->regs + VID_BC); sti_vid_init()
102 writel(VID_TINT_DFLT, vid->regs + VID_TINT); sti_vid_init()
103 writel(VID_CSAT_DFLT, vid->regs + VID_CSAT); sti_vid_init()
H A Dsti_vtg.c120 writel(1, vtg->regs + VTG_DRST_AUTOC); vtg_reset()
143 writel(video_top_field_start, regs + VTG_VID_TFO); vtg_set_output_window()
144 writel(video_top_field_stop, regs + VTG_VID_TFS); vtg_set_output_window()
145 writel(video_bottom_field_start, regs + VTG_VID_BFO); vtg_set_output_window()
146 writel(video_bottom_field_stop, regs + VTG_VID_BFS); vtg_set_output_window()
158 writel(mode->htotal, vtg->regs + VTG_CLKLN); vtg_set_mode()
161 writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN); vtg_set_mode()
169 writel(tmp, vtg->regs + VTG_H_HD_1); vtg_set_mode()
173 writel(tmp, vtg->regs + VTG_TOP_V_VD_1); vtg_set_mode()
174 writel(tmp, vtg->regs + VTG_BOT_V_VD_1); vtg_set_mode()
178 writel(tmp, vtg->regs + VTG_TOP_V_HD_1); vtg_set_mode()
179 writel(tmp, vtg->regs + VTG_BOT_V_HD_1); vtg_set_mode()
183 writel(tmp, vtg->regs + VTG_H_HD_2); vtg_set_mode()
187 writel(tmp, vtg->regs + VTG_TOP_V_VD_2); vtg_set_mode()
188 writel(tmp, vtg->regs + VTG_BOT_V_VD_2); vtg_set_mode()
189 writel(0, vtg->regs + VTG_TOP_V_HD_2); vtg_set_mode()
190 writel(0, vtg->regs + VTG_BOT_V_HD_2); vtg_set_mode()
195 writel(tmp, vtg->regs + VTG_H_HD_3); vtg_set_mode()
199 writel(tmp, vtg->regs + VTG_TOP_V_VD_3); vtg_set_mode()
200 writel(tmp, vtg->regs + VTG_BOT_V_VD_3); vtg_set_mode()
204 writel(tmp, vtg->regs + VTG_TOP_V_HD_3); vtg_set_mode()
205 writel(tmp, vtg->regs + VTG_BOT_V_HD_3); vtg_set_mode()
209 writel(tmp, vtg->regs + VTG_H_HD_4); vtg_set_mode()
213 writel(tmp, vtg->regs + VTG_TOP_V_VD_4); vtg_set_mode()
214 writel(tmp, vtg->regs + VTG_BOT_V_VD_4); vtg_set_mode()
215 writel(0, vtg->regs + VTG_TOP_V_HD_4); vtg_set_mode()
216 writel(0, vtg->regs + VTG_BOT_V_HD_4); vtg_set_mode()
219 writel(type, vtg->regs + VTG_MODE); vtg_set_mode()
225 writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR); vtg_enable_irq()
226 writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR); vtg_enable_irq()
227 writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET); vtg_enable_irq()
319 writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR); vtg_irq()
H A Dsti_vtac.c95 writel(VTAC_FIFO_CONFIG_VAL, vtac->regs + VTAC_RX_FIFO_CONFIG); sti_vtac_rx_set_config()
101 writel(config, vtac->regs + VTAC_CONFIG); sti_vtac_rx_set_config()
115 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8522); sti_vtac_tx_set_config()
117 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); sti_vtac_tx_set_config()
120 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); sti_vtac_tx_set_config()
123 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); sti_vtac_tx_set_config()
126 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); sti_vtac_tx_set_config()
129 writel(phy_config, vtac->phy_regs + VTAC_SYS_CFG8521); sti_vtac_tx_set_config()
136 writel(config, vtac->regs + VTAC_CONFIG); sti_vtac_tx_set_config()
/linux-4.4.14/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_mtl.c43 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); sxgbe_mtl_init()
53 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); sxgbe_mtl_init()
59 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); sxgbe_mtl_dma_dm_rxqueue()
60 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); sxgbe_mtl_dma_dm_rxqueue()
61 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); sxgbe_mtl_dma_dm_rxqueue()
73 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); sxgbe_mtl_set_txfifosize()
85 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_set_rxfifosize()
94 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); sxgbe_mtl_enable_txqueue()
103 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); sxgbe_mtl_disable_txqueue()
115 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fc_active()
124 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fc_enable()
136 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fc_deactive()
146 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fep_enable()
156 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fep_disable()
166 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fup_enable()
176 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_mtl_fup_disable()
208 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); sxgbe_set_tx_mtl_mode()
230 writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); sxgbe_set_rx_mtl_mode()
H A Dsxgbe_dma.c41 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); sxgbe_dma_init()
57 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); sxgbe_dma_channel_init()
61 writel(reg_val, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); sxgbe_dma_channel_init()
65 writel(reg_val, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cha_num)); sxgbe_dma_channel_init()
69 writel(upper_32_bits(dma_tx), sxgbe_dma_channel_init()
71 writel(lower_32_bits(dma_tx), sxgbe_dma_channel_init()
74 writel(upper_32_bits(dma_rx), sxgbe_dma_channel_init()
76 writel(lower_32_bits(dma_rx), sxgbe_dma_channel_init()
84 writel(lower_32_bits(dma_addr), sxgbe_dma_channel_init()
88 writel(lower_32_bits(dma_addr), sxgbe_dma_channel_init()
91 writel(t_rsize - 1, ioaddr + SXGBE_DMA_CHA_TXDESC_RINGLEN_REG(cha_num)); sxgbe_dma_channel_init()
92 writel(r_rsize - 1, ioaddr + SXGBE_DMA_CHA_RXDESC_RINGLEN_REG(cha_num)); sxgbe_dma_channel_init()
95 writel(SXGBE_DMA_ENA_INT, sxgbe_dma_channel_init()
105 writel(tx_config, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); sxgbe_enable_dma_transmission()
111 writel(SXGBE_DMA_ENA_INT, sxgbe_enable_dma_irq()
118 writel(0, ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(dma_cnum)); sxgbe_disable_dma_irq()
129 writel(tx_ctl_reg, sxgbe_dma_start_tx()
140 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); sxgbe_dma_start_tx_queue()
149 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(dma_cnum)); sxgbe_dma_stop_tx_queue()
160 writel(tx_ctl_reg, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); sxgbe_dma_stop_tx()
172 writel(rx_ctl_reg, sxgbe_dma_start_rx()
185 writel(rx_ctl_reg, ioaddr + SXGBE_DMA_CHA_RXCTL_REG(cnum)); sxgbe_dma_stop_rx()
256 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); sxgbe_tx_dma_int_status()
322 writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no)); sxgbe_rx_dma_int_status()
333 writel(riwt, SXGBE_FOR_EACH_QUEUE()
344 writel(ctrl, ioaddr + SXGBE_DMA_CHA_TXCTL_REG(chan_num)); sxgbe_enable_tso()
H A Dsxgbe_core.c34 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); sxgbe_core_init()
43 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_core_init()
99 writel(high_word, ioaddr + SXGBE_CORE_ADD_HIGHOFFSET(reg_n)); sxgbe_core_set_umac_addr()
100 writel(low_word, ioaddr + SXGBE_CORE_ADD_LOWOFFSET(reg_n)); sxgbe_core_set_umac_addr()
129 writel(tx_config, ioaddr + SXGBE_CORE_TX_CONFIG_REG); sxgbe_enable_tx()
141 writel(rx_config, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_enable_rx()
165 writel(tx_cfg, ioaddr + SXGBE_CORE_TX_CONFIG_REG); sxgbe_core_set_speed()
175 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); sxgbe_core_enable_rxqueue()
185 writel(reg_val, ioaddr + SXGBE_CORE_RX_CTL0_REG); sxgbe_core_disable_rxqueue()
199 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_set_eee_mode()
208 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_reset_eee_mode()
223 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); sxgbe_set_eee_pls()
238 writel(value, ioaddr + SXGBE_CORE_LPI_TIMER_CTRL); sxgbe_set_eee_timer()
247 writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_enable_rx_csum()
256 writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG); sxgbe_disable_rx_csum()
/linux-4.4.14/drivers/clocksource/
H A Dzevio-timer.c72 writel(delta, timer->timer1 + IO_CURRENT_VAL); zevio_timer_set_event()
73 writel(CNTL_RUN_TIMER | CNTL_DEC | CNTL_MATCH(TIMER_MATCH), zevio_timer_set_event()
85 writel(0, timer->interrupt_regs + IO_INTR_MSK); zevio_timer_shutdown()
86 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); zevio_timer_shutdown()
88 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); zevio_timer_shutdown()
98 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_MSK); zevio_timer_set_oneshot()
99 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); zevio_timer_set_oneshot()
112 writel(TIMER_INTR_MSK, timer->interrupt_regs + IO_INTR_ACK); zevio_timer_interrupt()
113 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); zevio_timer_interrupt()
169 writel(CNTL_STOP_TIMER, timer->timer1 + IO_CONTROL); zevio_timer_add()
170 writel(0, timer->timer1 + IO_DIVIDER); zevio_timer_add()
173 writel(0, timer->interrupt_regs + IO_INTR_MSK); zevio_timer_add()
174 writel(TIMER_INTR_ALL, timer->interrupt_regs + IO_INTR_ACK); zevio_timer_add()
177 writel(0, timer->base + IO_MATCH(TIMER_MATCH)); zevio_timer_add()
191 writel(CNTL_STOP_TIMER, timer->timer2 + IO_CONTROL); zevio_timer_add()
192 writel(0, timer->timer2 + IO_CURRENT_VAL); zevio_timer_add()
193 writel(0, timer->timer2 + IO_DIVIDER); zevio_timer_add()
194 writel(CNTL_RUN_TIMER | CNTL_FOREVER | CNTL_INC, zevio_timer_add()
H A Dmoxart_timer.c63 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_shutdown()
69 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_set_oneshot()
70 writel(~0, base + TIMER1_BASE + REG_LOAD); moxart_set_oneshot()
76 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); moxart_set_periodic()
77 writel(TIMER1_ENABLE, base + TIMER_CR); moxart_set_periodic()
86 writel(TIMER1_DISABLE, base + TIMER_CR); moxart_clkevt_next_event()
89 writel(u, base + TIMER1_BASE + REG_MATCH1); moxart_clkevt_next_event()
91 writel(TIMER1_ENABLE, base + TIMER_CR); moxart_clkevt_next_event()
153 writel(~0, base + TIMER2_BASE + REG_LOAD); moxart_timer_init()
154 writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); moxart_timer_init()
H A Dtimer-integrator-ap.c50 writel(0xffff, base + TIMER_LOAD); integrator_clocksource_init()
51 writel(ctrl, base + TIMER_CTRL); integrator_clocksource_init()
71 writel(1, clkevt_base + TIMER_INTCLR); integrator_timer_interrupt()
83 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_shutdown()
93 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_set_oneshot()
102 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_set_periodic()
105 writel(timer_reload, clkevt_base + TIMER_LOAD); clkevt_set_periodic()
107 writel(ctrl, clkevt_base + TIMER_CTRL); clkevt_set_periodic()
115 writel(ctrl & ~TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); clkevt_set_next_event()
116 writel(next, clkevt_base + TIMER_LOAD); clkevt_set_next_event()
117 writel(ctrl | TIMER_CTRL_ENABLE, clkevt_base + TIMER_CTRL); clkevt_set_next_event()
157 writel(ctrl, clkevt_base + TIMER_CTRL); integrator_clockevent_init()
188 writel(0, base + TIMER_CTRL); integrator_ap_timer_init_of()
H A Dtimer-u300.c193 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, u300_shutdown()
196 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, u300_shutdown()
214 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, u300_set_oneshot()
217 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, u300_set_oneshot()
223 writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC); u300_set_oneshot()
225 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, u300_set_oneshot()
228 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, u300_set_oneshot()
231 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, u300_set_oneshot()
242 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, u300_set_periodic()
245 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, u300_set_periodic()
251 writel(cevdata->ticks_per_jiffy, u300_set_periodic()
257 writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS, u300_set_periodic()
260 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, u300_set_periodic()
263 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, u300_set_periodic()
281 writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE, u300_set_next_event()
284 writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE, u300_set_next_event()
287 writel(U300_TIMER_APP_RGPT1_TIMER_RESET, u300_set_next_event()
290 writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC); u300_set_next_event()
295 writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT, u300_set_next_event()
298 writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE, u300_set_next_event()
301 writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE, u300_set_next_event()
327 writel(U300_TIMER_APP_GPT1IA_IRQ_ACK, u300_timer_interrupt()
397 writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE, u300_timer_init_of()
399 writel(U300_TIMER_APP_ROST_TIMER_RESET, u300_timer_init_of()
401 writel(U300_TIMER_APP_DOST_TIMER_DISABLE, u300_timer_init_of()
403 writel(U300_TIMER_APP_RDDT_TIMER_RESET, u300_timer_init_of()
405 writel(U300_TIMER_APP_DDDT_TIMER_DISABLE, u300_timer_init_of()
409 writel(U300_TIMER_APP_RGPT1_TIMER_RESET, u300_timer_init_of()
416 writel(U300_TIMER_APP_RGPT2_TIMER_RESET, u300_timer_init_of()
419 writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC); u300_timer_init_of()
421 writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS, u300_timer_init_of()
424 writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE, u300_timer_init_of()
427 writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE, u300_timer_init_of()
H A Dnomadik-mtu.c95 writel(1 << 1, mtu_base + MTU_IMSC); nmdk_clkevt_next()
96 writel(evt, mtu_base + MTU_LR(1)); nmdk_clkevt_next()
98 writel(MTU_CRn_ONESHOT | clk_prescale | nmdk_clkevt_next()
109 writel(nmdk_cycle, mtu_base + MTU_LR(1)); nmdk_clkevt_reset()
110 writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); nmdk_clkevt_reset()
112 writel(MTU_CRn_PERIODIC | clk_prescale | nmdk_clkevt_reset()
115 writel(1 << 1, mtu_base + MTU_IMSC); nmdk_clkevt_reset()
124 writel(0, mtu_base + MTU_IMSC); nmdk_clkevt_shutdown()
126 writel(0, mtu_base + MTU_CR(1)); nmdk_clkevt_shutdown()
128 writel(0xffffffff, mtu_base + MTU_LR(1)); nmdk_clkevt_shutdown()
148 writel(0, mtu_base + MTU_CR(0)); nmdk_clksrc_reset()
151 writel(nmdk_cycle, mtu_base + MTU_LR(0)); nmdk_clksrc_reset()
152 writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); nmdk_clksrc_reset()
154 writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, nmdk_clksrc_reset()
184 writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ nmdk_timer_interrupt()
H A Dtimer-sp804.c77 writel(0, base + TIMER_CTRL); sp804_timer_disable()
102 writel(0, base + TIMER_CTRL); __sp804_clocksource_and_sched_clock_init()
103 writel(0xffffffff, base + TIMER_LOAD); __sp804_clocksource_and_sched_clock_init()
104 writel(0xffffffff, base + TIMER_VALUE); __sp804_clocksource_and_sched_clock_init()
105 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC, __sp804_clocksource_and_sched_clock_init()
129 writel(1, clkevt_base + TIMER_INTCLR); sp804_timer_interrupt()
138 writel(0, clkevt_base + TIMER_CTRL); timer_shutdown()
153 writel(clkevt_reload, clkevt_base + TIMER_LOAD); sp804_set_periodic()
154 writel(ctrl, clkevt_base + TIMER_CTRL); sp804_set_periodic()
164 writel(next, clkevt_base + TIMER_LOAD); sp804_set_next_event()
165 writel(ctrl, clkevt_base + TIMER_CTRL); sp804_set_next_event()
212 writel(0, base + TIMER_CTRL); __sp804_clockevents_init()
232 writel(0, base + TIMER_CTRL); sp804_of_init()
233 writel(0, base + TIMER_2_BASE + TIMER_CTRL); sp804_of_init()
290 writel(0, base + TIMER_CTRL); integrator_cp_of_init()
H A Dvt8500_timer.c60 writel(3, regbase + TIMER_CTRL_VAL); vt8500_timer_read()
83 writel((unsigned long)alarm, regbase + TIMER_MATCH_VAL); vt8500_timer_set_next_event()
88 writel(1, regbase + TIMER_IER_VAL); vt8500_timer_set_next_event()
95 writel(readl(regbase + TIMER_CTRL_VAL) | 1, regbase + TIMER_CTRL_VAL); vt8500_shutdown()
96 writel(0, regbase + TIMER_IER_VAL); vt8500_shutdown()
112 writel(0xf, regbase + TIMER_STATUS_VAL); vt8500_timer_interrupt()
142 writel(1, regbase + TIMER_CTRL_VAL); vt8500_timer_init()
143 writel(0xf, regbase + TIMER_STATUS_VAL); vt8500_timer_init()
144 writel(~0, regbase + TIMER_MATCH_VAL); vt8500_timer_init()
H A Dtime-armada-370-xp.c93 writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set, local_timer_ctrl_clrset()
112 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); armada_370_xp_clkevt_next_event()
117 writel(delta, local_base + TIMER0_VAL_OFF); armada_370_xp_clkevt_next_event()
136 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); armada_370_xp_clkevt_shutdown()
145 writel(ticks_per_jiffy - 1, local_base + TIMER0_RELOAD_OFF); armada_370_xp_clkevt_set_periodic()
146 writel(ticks_per_jiffy - 1, local_base + TIMER0_VAL_OFF); armada_370_xp_clkevt_set_periodic()
164 writel(TIMER0_CLR_MASK, local_base + LCL_TIMER_EVENTS_STATUS); armada_370_xp_timer_interrupt()
243 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); armada_370_xp_timer_resume()
244 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); armada_370_xp_timer_resume()
245 writel(timer0_ctrl_reg, timer_base + TIMER_CTRL_OFF); armada_370_xp_timer_resume()
246 writel(timer0_local_ctrl_reg, local_base + TIMER_CTRL_OFF); armada_370_xp_timer_resume()
294 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); armada_370_xp_timer_common_init()
295 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); armada_370_xp_timer_common_init()
H A Dsun4i_timer.c62 writel(val & ~TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(timer)); sun4i_clkevt_time_stop()
68 writel(delay, timer_base + TIMER_INTVAL_REG(timer)); sun4i_clkevt_time_setup()
80 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, sun4i_clkevt_time_start()
131 writel(0x1, timer_base + TIMER_IRQ_ST_REG); sun4i_timer_interrupt()
171 writel(~0, timer_base + TIMER_INTVAL_REG(1)); sun4i_timer_init()
172 writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | sun4i_timer_init()
190 writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), sun4i_timer_init()
208 writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); sun4i_timer_init()
H A Dmtk_timer.c81 writel(val & ~TIMER_CTRL_ENABLE, evt->gpt_base + mtk_clkevt_time_stop()
88 writel(delay, evt->gpt_base + TIMER_CMP_REG(timer)); mtk_clkevt_time_setup()
97 writel(GPT_IRQ_ACK(timer), evt->gpt_base + GPT_IRQ_ACK_REG); mtk_clkevt_time_start()
109 writel(val | TIMER_CTRL_ENABLE | TIMER_CTRL_CLEAR, mtk_clkevt_time_start()
146 writel(GPT_IRQ_ACK(GPT_CLK_EVT), evt->gpt_base + GPT_IRQ_ACK_REG); mtk_timer_interrupt()
155 writel(TIMER_CTRL_CLEAR | TIMER_CTRL_DISABLE, mtk_timer_setup()
158 writel(TIMER_CLK_SRC(TIMER_CLK_SRC_SYS13M) | TIMER_CLK_DIV1, mtk_timer_setup()
161 writel(0x0, evt->gpt_base + TIMER_CMP_REG(timer)); mtk_timer_setup()
163 writel(TIMER_CTRL_OP(option) | TIMER_CTRL_ENABLE, mtk_timer_setup()
172 writel(0x0, evt->gpt_base + GPT_IRQ_EN_REG); mtk_timer_enable_irq()
175 writel(0x3f, evt->gpt_base + GPT_IRQ_ACK_REG); mtk_timer_enable_irq()
178 writel(val | GPT_IRQ_ENABLE(timer), mtk_timer_enable_irq()
H A Dmeson6_timer.c50 writel(val & ~TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); meson6_clkevt_time_stop()
55 writel(delay, timer_base + TIMER_ISA_VAL(timer)); meson6_clkevt_time_setup()
67 writel(val | TIMER_ENABLE_BIT(timer), timer_base + TIMER_ISA_MUX); meson6_clkevt_time_start()
146 writel(val, timer_base + TIMER_ISA_MUX); meson6_timer_init()
155 writel(val, timer_base + TIMER_ISA_MUX); meson6_timer_init()
H A Dtime-orion.c56 writel(delta, timer_base + TIMER1_VAL); orion_clkevt_next_event()
74 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD); orion_clkevt_set_periodic()
75 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL); orion_clkevt_set_periodic()
128 writel(~0, timer_base + TIMER0_VAL); orion_timer_init()
129 writel(~0, timer_base + TIMER0_RELOAD); orion_timer_init()
H A Darm_global_timer.c102 writel(ctrl, gt_base + GT_CONTROL); gt_compare_set()
103 writel(lower_32_bits(counter), gt_base + GT_COMP0); gt_compare_set()
104 writel(upper_32_bits(counter), gt_base + GT_COMP1); gt_compare_set()
107 writel(delta, gt_base + GT_AUTO_INC); gt_compare_set()
112 writel(ctrl, gt_base + GT_CONTROL); gt_compare_set()
122 writel(ctrl, gt_base + GT_CONTROL); gt_clockevent_shutdown()
215 writel(0, gt_base + GT_CONTROL); gt_clocksource_init()
216 writel(0, gt_base + GT_COUNTER0); gt_clocksource_init()
217 writel(0, gt_base + GT_COUNTER1); gt_clocksource_init()
219 writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); gt_clocksource_init()
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A Dsetup-usb-phy.c29 writel(readl(S3C64XX_OTHERS) | S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); s3c_usb_otgphy_init()
52 writel(phyclk | S3C_PHYCLK_CLK_FORCE, S3C_PHYCLK); s3c_usb_otgphy_init()
55 writel((readl(S3C_PHYPWR) & ~S3C_PHYPWR_NORMAL_MASK), S3C_PHYPWR); s3c_usb_otgphy_init()
59 writel(S3C_RSTCON_PHY | S3C_RSTCON_HCLK | S3C_RSTCON_PHYCLK, s3c_usb_otgphy_init()
62 writel(0, S3C_RSTCON); s3c_usb_otgphy_init()
69 writel((readl(S3C_PHYPWR) | S3C_PHYPWR_ANALOG_POWERDOWN | s3c_usb_otgphy_exit()
72 writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK, S3C64XX_OTHERS); s3c_usb_otgphy_exit()
/linux-4.4.14/drivers/media/platform/exynos-gsc/
H A Dgsc-regs.c20 writel(GSC_SW_RESET_SRESET, dev->regs + GSC_SW_RESET); gsc_hw_set_sw_reset()
47 writel(cfg, dev->regs + GSC_IRQ); gsc_hw_set_frm_done_irq_mask()
59 writel(cfg, dev->regs + GSC_IRQ); gsc_hw_set_gsc_irq_enable()
71 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_Y_MASK); gsc_hw_set_input_buf_masking()
72 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CB_MASK); gsc_hw_set_input_buf_masking()
73 writel(cfg, dev->regs + GSC_IN_BASE_ADDR_CR_MASK); gsc_hw_set_input_buf_masking()
85 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_Y_MASK); gsc_hw_set_output_buf_masking()
86 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CB_MASK); gsc_hw_set_output_buf_masking()
87 writel(cfg, dev->regs + GSC_OUT_BASE_ADDR_CR_MASK); gsc_hw_set_output_buf_masking()
95 writel(addr->y, dev->regs + GSC_IN_BASE_ADDR_Y(index)); gsc_hw_set_input_addr()
96 writel(addr->cb, dev->regs + GSC_IN_BASE_ADDR_CB(index)); gsc_hw_set_input_addr()
97 writel(addr->cr, dev->regs + GSC_IN_BASE_ADDR_CR(index)); gsc_hw_set_input_addr()
106 writel(addr->y, dev->regs + GSC_OUT_BASE_ADDR_Y(index)); gsc_hw_set_output_addr()
107 writel(addr->cb, dev->regs + GSC_OUT_BASE_ADDR_CB(index)); gsc_hw_set_output_addr()
108 writel(addr->cr, dev->regs + GSC_OUT_BASE_ADDR_CR(index)); gsc_hw_set_output_addr()
121 writel(cfg, dev->regs + GSC_IN_CON); gsc_hw_set_input_path()
133 writel(cfg, dev->regs + GSC_SRCIMG_OFFSET); gsc_hw_set_in_size()
138 writel(cfg, dev->regs + GSC_SRCIMG_SIZE); gsc_hw_set_in_size()
143 writel(cfg, dev->regs + GSC_CROPPED_SIZE); gsc_hw_set_in_size()
163 writel(cfg, dev->regs + GSC_IN_CON); gsc_hw_set_in_image_rgb()
177 writel(cfg, dev->regs + GSC_IN_CON); gsc_hw_set_in_image_format()
219 writel(cfg, dev->regs + GSC_IN_CON); gsc_hw_set_in_image_format()
234 writel(cfg, dev->regs + GSC_OUT_CON); gsc_hw_set_output_path()
247 writel(cfg, dev->regs + GSC_DSTIMG_OFFSET); gsc_hw_set_out_size()
251 writel(cfg, dev->regs + GSC_DSTIMG_SIZE); gsc_hw_set_out_size()
263 writel(cfg, dev->regs + GSC_SCALED_SIZE); gsc_hw_set_out_size()
283 writel(cfg, dev->regs + GSC_OUT_CON); gsc_hw_set_out_image_rgb()
297 writel(cfg, dev->regs + GSC_OUT_CON); gsc_hw_set_out_image_format()
343 writel(cfg, dev->regs + GSC_OUT_CON); gsc_hw_set_out_image_format()
355 writel(cfg, dev->regs + GSC_PRE_SCALE_RATIO); gsc_hw_set_prescaler()
365 writel(cfg, dev->regs + GSC_MAIN_H_RATIO); gsc_hw_set_mainscaler()
368 writel(cfg, dev->regs + GSC_MAIN_V_RATIO); gsc_hw_set_mainscaler()
401 writel(cfg, dev->regs + GSC_IN_CON); gsc_hw_set_rotation()
419 writel(cfg, dev->regs + GSC_OUT_CON); gsc_hw_set_global_alpha()
429 writel(cfg, dev->regs + GSC_ENABLE); gsc_hw_set_sfr_update()
/linux-4.4.14/drivers/video/fbdev/exynos/
H A Dexynos_mipi_dsi_lowlevel.c40 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_func_reset()
51 writel(reg, dsim->reg_base + EXYNOS_DSIM_SWRST); exynos_mipi_dsi_sw_reset()
62 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_sw_reset_release()
90 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTMSK); exynos_mipi_dsi_set_interrupt_mask()
100 writel(reg & ~(cfg), dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
104 writel(reg, dsim->reg_base + EXYNOS_DSIM_FIFOCTRL); exynos_mipi_dsi_init_fifo_pointer()
113 writel(DSIM_AFC_CTL(value), dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_set_phy_tunning()
128 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_stand_by()
139 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_disp_resol()
145 writel(reg, dsim->reg_base + EXYNOS_DSIM_MDRESOL); exynos_mipi_dsi_set_main_disp_resol()
161 writel(reg, dsim->reg_base + EXYNOS_DSIM_MVPORCH); exynos_mipi_dsi_set_main_disp_vporch()
174 writel(reg, dsim->reg_base + EXYNOS_DSIM_MHPORCH); exynos_mipi_dsi_set_main_disp_hporch()
188 writel(reg, dsim->reg_base + EXYNOS_DSIM_MSYNC); exynos_mipi_dsi_set_main_disp_sync_area()
199 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
204 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
207 writel(reg, dsim->reg_base + EXYNOS_DSIM_SDRESOL); exynos_mipi_dsi_set_sub_disp_resol()
226 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_init_config()
250 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_display_config()
265 writel(reg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_enable_lane()
277 writel(cfg, dsim->reg_base + EXYNOS_DSIM_CONFIG); exynos_mipi_dsi_set_data_lane_number()
292 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR); exynos_mipi_dsi_enable_afc()
303 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_pll_bypass()
313 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_set_pll_pms()
324 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_pll_freq_band()
337 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_pll_freq()
343 writel(lock_time, dsim->reg_base + EXYNOS_DSIM_PLLTMR); exynos_mipi_dsi_pll_stable_time()
353 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_enable_pll()
364 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_set_byte_clock_src()
375 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_byte_clock()
388 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_set_esc_clk_prs()
402 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_esc_clk_on_lane()
413 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_force_dphy_stop_state()
442 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_stop_state_counter()
453 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); exynos_mipi_dsi_set_bta_timeout()
464 writel(reg, dsim->reg_base + EXYNOS_DSIM_TIMEOUT); exynos_mipi_dsi_set_lpdr_timeout()
477 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_cpu_transfer_mode()
490 writel(reg, dsim->reg_base + EXYNOS_DSIM_ESCMODE); exynos_mipi_dsi_set_lcdc_transfer_mode()
501 writel(reg, dsim->reg_base + EXYNOS_DSIM_CLKCTRL); exynos_mipi_dsi_enable_hs_clock()
512 writel(reg, dsim->reg_base + EXYNOS_DSIM_PHYACCHR1); exynos_mipi_dsi_dp_dn_swap()
523 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_hs_zero_ctrl()
533 writel(reg, dsim->reg_base + EXYNOS_DSIM_PLLCTRL); exynos_mipi_dsi_prep_ctrl()
548 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_clear_interrupt()
561 writel(reg, dsim->reg_base + EXYNOS_DSIM_INTSRC); exynos_mipi_dsi_set_interrupt()
583 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); exynos_mipi_dsi_wr_tx_header()
591 writel(reg, dsim->reg_base + EXYNOS_DSIM_PKTHDR); exynos_mipi_dsi_rd_tx_header()
610 writel(reg | INTSRC_FRAME_DONE, dsim->reg_base + _exynos_mipi_dsi_clear_frame_done()
617 writel(tx_data, dsim->reg_base + EXYNOS_DSIM_PAYLOAD); exynos_mipi_dsi_wr_tx_data()
/linux-4.4.14/arch/m68k/include/asm/
H A Dio.h13 #define writel_relaxed(b, addr) writel(b, addr)
/linux-4.4.14/arch/arm/plat-orion/
H A Dtime.c86 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); orion_clkevt_next_event()
90 writel(u, bridge_base + BRIDGE_MASK_OFF); orion_clkevt_next_event()
95 writel(delta, timer_base + TIMER1_VAL_OFF); orion_clkevt_next_event()
102 writel(u, timer_base + TIMER_CTRL_OFF); orion_clkevt_next_event()
118 writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF); orion_clkevt_shutdown()
122 writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); orion_clkevt_shutdown()
125 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); orion_clkevt_shutdown()
140 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF); orion_clkevt_set_periodic()
141 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF); orion_clkevt_set_periodic()
145 writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF); orion_clkevt_set_periodic()
149 writel(u | TIMER1_EN | TIMER1_RELOAD_EN, timer_base + TIMER_CTRL_OFF); orion_clkevt_set_periodic()
173 writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF); orion_timer_interrupt()
214 writel(0xffffffff, timer_base + TIMER0_VAL_OFF); orion_time_init()
215 writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); orion_time_init()
217 writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF); orion_time_init()
219 writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF); orion_time_init()
H A Dpcie.c89 writel(stat, base + PCIE_STAT_OFF); orion_pcie_set_local_bus_nr()
105 writel(reg, base + PCIE_DEBUG_CTRL); orion_pcie_reset()
115 writel(reg, base + PCIE_DEBUG_CTRL); orion_pcie_reset()
135 writel(0, base + PCIE_BAR_CTRL_OFF(i)); orion_pcie_setup_wins()
136 writel(0, base + PCIE_BAR_LO_OFF(i)); orion_pcie_setup_wins()
137 writel(0, base + PCIE_BAR_HI_OFF(i)); orion_pcie_setup_wins()
141 writel(0, base + PCIE_WIN04_CTRL_OFF(i)); orion_pcie_setup_wins()
142 writel(0, base + PCIE_WIN04_BASE_OFF(i)); orion_pcie_setup_wins()
143 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); orion_pcie_setup_wins()
146 writel(0, base + PCIE_WIN5_CTRL_OFF); orion_pcie_setup_wins()
147 writel(0, base + PCIE_WIN5_BASE_OFF); orion_pcie_setup_wins()
148 writel(0, base + PCIE_WIN5_REMAP_OFF); orion_pcie_setup_wins()
157 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i)); orion_pcie_setup_wins()
158 writel(0, base + PCIE_WIN04_REMAP_OFF(i)); orion_pcie_setup_wins()
159 writel(((cs->size - 1) & 0xffff0000) | orion_pcie_setup_wins()
176 writel(dram->cs[0].base, base + PCIE_BAR_LO_OFF(1)); orion_pcie_setup_wins()
177 writel(0, base + PCIE_BAR_HI_OFF(1)); orion_pcie_setup_wins()
178 writel(((size - 1) & 0xffff0000) | 1, base + PCIE_BAR_CTRL_OFF(1)); orion_pcie_setup_wins()
205 writel(mask, base + PCIE_MASK_OFF); orion_pcie_setup()
211 writel(PCIE_CONF_BUS(bus->number) | orion_pcie_rd_conf()
230 writel(PCIE_CONF_BUS(bus->number) | orion_pcie_rd_conf_tlp()
271 writel(PCIE_CONF_BUS(bus->number) | orion_pcie_wr_conf()
278 writel(val, base + PCIE_CONF_DATA_OFF); orion_pcie_wr_conf()
/linux-4.4.14/drivers/usb/host/
H A Dxhci-rcar.c67 writel(temp, hcd->regs + RCAR_USB3_INT_ENA); xhci_rcar_start()
69 writel(RCAR_USB3_LCLK_ENA_VAL, hcd->regs + RCAR_USB3_LCLK); xhci_rcar_start()
71 writel(RCAR_USB3_CONF1_VAL, hcd->regs + RCAR_USB3_CONF1); xhci_rcar_start()
72 writel(RCAR_USB3_CONF2_VAL, hcd->regs + RCAR_USB3_CONF2); xhci_rcar_start()
73 writel(RCAR_USB3_CONF3_VAL, hcd->regs + RCAR_USB3_CONF3); xhci_rcar_start()
75 writel(RCAR_USB3_RX_POL_VAL, hcd->regs + RCAR_USB3_RX_POL); xhci_rcar_start()
76 writel(RCAR_USB3_TX_POL_VAL, hcd->regs + RCAR_USB3_TX_POL); xhci_rcar_start()
95 writel(temp, regs + RCAR_USB3_DL_CTRL); xhci_rcar_download_firmware()
103 writel(data, regs + RCAR_USB3_FW_DATA0); xhci_rcar_download_firmware()
106 writel(temp, regs + RCAR_USB3_DL_CTRL); xhci_rcar_download_firmware()
122 writel(temp, regs + RCAR_USB3_DL_CTRL); xhci_rcar_download_firmware()
H A Dxhci-mvebu.c28 writel(0, base + USB3_WIN_CTRL(win)); xhci_mvebu_mbus_config()
29 writel(0, base + USB3_WIN_BASE(win)); xhci_mvebu_mbus_config()
36 writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) | xhci_mvebu_mbus_config()
40 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); xhci_mvebu_mbus_config()
/linux-4.4.14/arch/arm/mach-orion5x/
H A Dtsx09-common.c36 writel(0x83, UART1_REG(LCR)); qnap_tsx09_power_off()
37 writel(divisor & 0xff, UART1_REG(DLL)); qnap_tsx09_power_off()
38 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); qnap_tsx09_power_off()
39 writel(0x03, UART1_REG(LCR)); qnap_tsx09_power_off()
40 writel(0x00, UART1_REG(IER)); qnap_tsx09_power_off()
41 writel(0x00, UART1_REG(FCR)); qnap_tsx09_power_off()
42 writel(0x00, UART1_REG(MCR)); qnap_tsx09_power_off()
45 writel('A', UART1_REG(TX)); qnap_tsx09_power_off()
/linux-4.4.14/drivers/spi/
H A Dspi-sirf.c307 writel(readl(sspi->base + sspi->regs->usp_mode1) & sirfsoc_usp_hwinit()
309 writel(readl(sspi->base + sspi->regs->usp_mode1) | sirfsoc_usp_hwinit()
337 writel(data, sspi->base + sspi->regs->txfifo_data); spi_sirfsoc_tx_word_u8()
366 writel(data, sspi->base + sspi->regs->txfifo_data); spi_sirfsoc_tx_word_u16()
396 writel(data, sspi->base + sspi->regs->txfifo_data); spi_sirfsoc_tx_word_u32()
409 writel(0x0, sspi->base + sspi->regs->int_en); spi_sirfsoc_irq()
410 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_irq()
422 writel(0x0, sspi->base + sspi->regs->int_en); spi_sirfsoc_irq()
425 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_irq()
428 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_irq()
441 writel(0x0, sspi->base + sspi->regs->int_en); spi_sirfsoc_irq()
444 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_irq()
447 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_irq()
468 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_cmd_transfer()
469 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_cmd_transfer()
477 writel(cmd, sspi->base + sspi->regs->spi_cmd); spi_sirfsoc_cmd_transfer()
478 writel(SIRFSOC_SPI_FRM_END_INT_EN, spi_sirfsoc_cmd_transfer()
480 writel(SIRFSOC_SPI_CMD_TX_EN, spi_sirfsoc_cmd_transfer()
497 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
498 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
501 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_dma_transfer()
503 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_dma_transfer()
505 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_dma_transfer()
508 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
509 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
510 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_dma_transfer()
513 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
514 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
515 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_dma_transfer()
518 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_dma_transfer()
523 writel(readl(sspi->base + sspi->regs->spi_ctrl) | spi_sirfsoc_dma_transfer()
527 writel(sspi->left_tx_word - 1, spi_sirfsoc_dma_transfer()
529 writel(sspi->left_tx_word - 1, spi_sirfsoc_dma_transfer()
535 writel(sspi->left_tx_word * sspi->word_width, spi_sirfsoc_dma_transfer()
537 writel(sspi->left_tx_word * sspi->word_width, spi_sirfsoc_dma_transfer()
543 writel(readl(sspi->base + sspi->regs->spi_ctrl), spi_sirfsoc_dma_transfer()
545 writel(0, sspi->base + sspi->regs->tx_dma_io_len); spi_sirfsoc_dma_transfer()
546 writel(0, sspi->base + sspi->regs->rx_dma_io_len); spi_sirfsoc_dma_transfer()
570 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, spi_sirfsoc_dma_transfer()
574 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_dma_transfer()
576 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_dma_transfer()
593 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
599 writel(0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_dma_transfer()
600 writel(0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_dma_transfer()
602 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
605 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_dma_transfer()
617 writel(SIRFSOC_SPI_FIFO_RESET, spi_sirfsoc_pio_transfer()
619 writel(SIRFSOC_SPI_FIFO_RESET, spi_sirfsoc_pio_transfer()
623 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
624 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
625 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_pio_transfer()
626 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_pio_transfer()
628 writel(min((sspi->left_tx_word * sspi->word_width), spi_sirfsoc_pio_transfer()
631 writel(min((sspi->left_rx_word * sspi->word_width), spi_sirfsoc_pio_transfer()
636 writel(0x0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
637 writel(0x0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
638 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); spi_sirfsoc_pio_transfer()
639 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_pio_transfer()
641 writel(min((sspi->left_tx_word * sspi->word_width), spi_sirfsoc_pio_transfer()
644 writel(min((sspi->left_rx_word * sspi->word_width), spi_sirfsoc_pio_transfer()
649 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_pio_transfer()
651 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_pio_transfer()
653 writel(0, sspi->base + sspi->regs->int_en); spi_sirfsoc_pio_transfer()
654 writel(readl(sspi->base + sspi->regs->int_st), spi_sirfsoc_pio_transfer()
656 writel(readl(sspi->base + sspi->regs->spi_ctrl) | spi_sirfsoc_pio_transfer()
661 writel(min(sspi->left_tx_word, data_units) - 1, spi_sirfsoc_pio_transfer()
663 writel(min(sspi->left_rx_word, data_units) - 1, spi_sirfsoc_pio_transfer()
671 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | spi_sirfsoc_pio_transfer()
676 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, spi_sirfsoc_pio_transfer()
680 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_pio_transfer()
682 writel(SIRFSOC_SPI_FIFO_START, spi_sirfsoc_pio_transfer()
690 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_pio_transfer()
699 writel(0, sspi->base + sspi->regs->tx_rx_en); spi_sirfsoc_pio_transfer()
700 writel(0, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_pio_transfer()
701 writel(0, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_pio_transfer()
754 writel(regval, sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_chipselect()
774 writel(regval, spi_sirfsoc_chipselect()
835 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) << spi_sirfsoc_config_mode()
842 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) << spi_sirfsoc_config_mode()
856 writel(regval, sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_config_mode()
863 writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); spi_sirfsoc_config_mode()
920 writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); spi_sirfsoc_setup_transfer()
921 writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); spi_sirfsoc_setup_transfer()
945 writel(tx_frm_ctl | (((usp_mode2 >> 10) & spi_sirfsoc_setup_transfer()
949 writel(rx_frm_ctl | (((usp_mode2 >> 12) & spi_sirfsoc_setup_transfer()
953 writel(readl(sspi->base + sspi->regs->usp_mode2) | spi_sirfsoc_setup_transfer()
963 writel(regval, sspi->base + sspi->regs->spi_ctrl); spi_sirfsoc_setup_transfer()
969 writel(readl(sspi->base + sspi->regs->spi_ctrl) | spi_sirfsoc_setup_transfer()
975 writel(readl(sspi->base + sspi->regs->spi_ctrl) & spi_sirfsoc_setup_transfer()
982 writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); spi_sirfsoc_setup_transfer()
983 writel(SIRFSOC_SPI_RX_DMA_FLUSH, spi_sirfsoc_setup_transfer()
987 writel(SIRFSOC_SPI_IO_MODE_SEL, spi_sirfsoc_setup_transfer()
989 writel(SIRFSOC_SPI_IO_MODE_SEL, spi_sirfsoc_setup_transfer()
1214 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_resume()
1215 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_resume()
1216 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); spi_sirfsoc_resume()
1217 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op); spi_sirfsoc_resume()
H A Dspi-altera.c76 writel(1 << spi->chip_select, altera_spi_chipsel()
79 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
84 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
85 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL); altera_spi_chipsel()
92 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
96 writel(1 << spi->chip_select, altera_spi_chipsel()
99 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_chipsel()
132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_txrx()
135 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA); altera_spi_txrx()
140 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_txrx()
145 writel(hw_txbyte(hw, hw->count), altera_spi_txrx()
193 writel(hw_txbyte(hw, hw->count), hw->base + ALTERA_SPI_TXDATA); altera_spi_irq()
235 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); altera_spi_probe()
236 writel(0, hw->base + ALTERA_SPI_STATUS); /* clear status reg */ altera_spi_probe()
H A Dspi-mxs.c98 writel(BM_SSP_CTRL0_LOCK_CS, mxs_spi_setup_transfer()
101 writel(BF_SSP_CTRL1_SSP_MODE(BV_SSP_CTRL1_SSP_MODE__SPI) | mxs_spi_setup_transfer()
107 writel(0x0, ssp->base + HW_SSP_CMD0); mxs_spi_setup_transfer()
108 writel(0x0, ssp->base + HW_SSP_CMD1); mxs_spi_setup_transfer()
313 writel(BM_SSP_CTRL0_IGNORE_CRC, mxs_spi_txrx_pio()
318 writel(BM_SSP_CTRL0_IGNORE_CRC, mxs_spi_txrx_pio()
322 writel(BM_SSP_CTRL0_XFER_COUNT, mxs_spi_txrx_pio()
324 writel(1, mxs_spi_txrx_pio()
327 writel(1, ssp->base + HW_SSP_XFER_SIZE); mxs_spi_txrx_pio()
331 writel(BM_SSP_CTRL0_READ, mxs_spi_txrx_pio()
334 writel(BM_SSP_CTRL0_READ, mxs_spi_txrx_pio()
337 writel(BM_SSP_CTRL0_RUN, mxs_spi_txrx_pio()
344 writel(*buf, ssp->base + HW_SSP_DATA(ssp)); mxs_spi_txrx_pio()
346 writel(BM_SSP_CTRL0_DATA_XFER, mxs_spi_txrx_pio()
379 writel(BM_SSP_CTRL0_WAIT_FOR_CMD | BM_SSP_CTRL0_WAIT_FOR_IRQ, mxs_spi_transfer_one()
381 writel(mxs_spi_cs_to_reg(m->spi->chip_select), mxs_spi_transfer_one()
404 writel(BM_SSP_CTRL1_DMA_ENABLE, mxs_spi_transfer_one()
417 writel(BM_SSP_CTRL1_DMA_ENABLE, mxs_spi_transfer_one()
/linux-4.4.14/drivers/media/platform/s5p-mfc/
H A Ds5p_mfc_opr_v6.c38 #undef writel macro
39 #define writel(v, r) \ macro
416 writel(strm_size, mfc_regs->d_stream_data_size); s5p_mfc_set_dec_stream_buffer_v6()
417 writel(buf_addr, mfc_regs->d_cpb_buffer_addr); s5p_mfc_set_dec_stream_buffer_v6()
418 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size); s5p_mfc_set_dec_stream_buffer_v6()
419 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset); s5p_mfc_set_dec_stream_buffer_v6()
443 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb); s5p_mfc_set_dec_frame_buffer_v6()
444 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size); s5p_mfc_set_dec_frame_buffer_v6()
445 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size); s5p_mfc_set_dec_frame_buffer_v6()
447 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr); s5p_mfc_set_dec_frame_buffer_v6()
448 writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size); s5p_mfc_set_dec_frame_buffer_v6()
451 writel(ctx->img_width, s5p_mfc_set_dec_frame_buffer_v6()
453 writel(ctx->img_width, s5p_mfc_set_dec_frame_buffer_v6()
462 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size); s5p_mfc_set_dec_frame_buffer_v6()
463 writel(ctx->mv_count, mfc_regs->d_num_mv); s5p_mfc_set_dec_frame_buffer_v6()
476 writel(ctx->dst_bufs[i].cookie.raw.luma, s5p_mfc_set_dec_frame_buffer_v6()
480 writel(ctx->dst_bufs[i].cookie.raw.chroma, s5p_mfc_set_dec_frame_buffer_v6()
494 writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4); s5p_mfc_set_dec_frame_buffer_v6()
507 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_set_dec_frame_buffer_v6()
522 writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */ s5p_mfc_set_enc_stream_buffer_v6()
523 writel(size, mfc_regs->e_stream_buffer_size); s5p_mfc_set_enc_stream_buffer_v6()
537 writel(y_addr, mfc_regs->e_source_first_plane_addr); s5p_mfc_set_enc_frame_buffer_v6()
538 writel(c_addr, mfc_regs->e_source_second_plane_addr); s5p_mfc_set_enc_frame_buffer_v6()
577 writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); s5p_mfc_set_enc_ref_buffer_v6()
579 writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i)); s5p_mfc_set_enc_ref_buffer_v6()
581 writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i)); s5p_mfc_set_enc_ref_buffer_v6()
587 writel(buf_addr1, mfc_regs->e_scratch_buffer_addr); s5p_mfc_set_enc_ref_buffer_v6()
588 writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size); s5p_mfc_set_enc_ref_buffer_v6()
592 writel(buf_addr1, mfc_regs->e_tmv_buffer0); s5p_mfc_set_enc_ref_buffer_v6()
594 writel(buf_addr1, mfc_regs->e_tmv_buffer1); s5p_mfc_set_enc_ref_buffer_v6()
605 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_set_enc_ref_buffer_v6()
621 writel(ctx->slice_mode, mfc_regs->e_mslice_mode); s5p_mfc_set_slice_mode()
623 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb); s5p_mfc_set_slice_mode()
626 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits); s5p_mfc_set_slice_mode()
628 writel(0x0, mfc_regs->e_mslice_size_mb); s5p_mfc_set_slice_mode()
629 writel(0x0, mfc_regs->e_mslice_size_bits); s5p_mfc_set_slice_mode()
645 writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */ s5p_mfc_set_enc_params()
647 writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */ s5p_mfc_set_enc_params()
650 writel(ctx->img_width, mfc_regs->e_cropped_frame_width); s5p_mfc_set_enc_params()
652 writel(ctx->img_height, mfc_regs->e_cropped_frame_height); s5p_mfc_set_enc_params()
654 writel(0x0, mfc_regs->e_frame_crop_offset); s5p_mfc_set_enc_params()
659 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params()
667 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
671 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
675 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
681 writel(p->intra_refresh_mb, mfc_regs->e_ir_size); s5p_mfc_set_enc_params()
687 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
692 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
699 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
701 writel(0x0, mfc_regs->pixel_format); s5p_mfc_set_enc_params()
706 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
708 writel(0x1, mfc_regs->pixel_format); s5p_mfc_set_enc_params()
713 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
715 writel(0x0, mfc_regs->pixel_format); s5p_mfc_set_enc_params()
722 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
725 writel(0x0, mfc_regs->e_padding_ctrl); s5p_mfc_set_enc_params()
736 writel(reg, mfc_regs->e_padding_ctrl); s5p_mfc_set_enc_params()
743 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params()
747 writel(p->rc_bitrate, s5p_mfc_set_enc_params()
750 writel(1, mfc_regs->e_rc_bit_rate); s5p_mfc_set_enc_params()
755 writel(1, mfc_regs->e_rc_mode); s5p_mfc_set_enc_params()
757 writel(2, mfc_regs->e_rc_mode); s5p_mfc_set_enc_params()
768 writel(reg, mfc_regs->e_enc_options); s5p_mfc_set_enc_params()
773 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params()
777 writel(reg, mfc_regs->e_mv_hor_range); s5p_mfc_set_enc_params()
780 writel(reg, mfc_regs->e_mv_ver_range); s5p_mfc_set_enc_params()
782 writel(0x0, mfc_regs->e_frame_insertion); s5p_mfc_set_enc_params()
783 writel(0x0, mfc_regs->e_roi_buffer_addr); s5p_mfc_set_enc_params()
784 writel(0x0, mfc_regs->e_param_change); s5p_mfc_set_enc_params()
785 writel(0x0, mfc_regs->e_rc_roi_ctrl); s5p_mfc_set_enc_params()
786 writel(0x0, mfc_regs->e_picture_tag); s5p_mfc_set_enc_params()
788 writel(0x0, mfc_regs->e_bit_count_enable); s5p_mfc_set_enc_params()
789 writel(0x0, mfc_regs->e_max_bit_count); s5p_mfc_set_enc_params()
790 writel(0x0, mfc_regs->e_min_bit_count); s5p_mfc_set_enc_params()
792 writel(0x0, mfc_regs->e_metadata_buffer_addr); s5p_mfc_set_enc_params()
793 writel(0x0, mfc_regs->e_metadata_buffer_size); s5p_mfc_set_enc_params()
817 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params_h264()
825 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_h264()
832 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h264()
837 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h264()
845 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_h264()
848 writel(0x0, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_h264()
854 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_h264()
862 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_h264()
868 writel(p_h264->cpb_size & 0xFFFF, s5p_mfc_set_enc_params_h264()
872 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); s5p_mfc_set_enc_params_h264()
878 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
882 writel(ctx->img_height >> 1, s5p_mfc_set_enc_params_h264()
885 writel(ctx->img_height >> 1, s5p_mfc_set_enc_params_h264()
893 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
903 writel(reg, mfc_regs->e_h264_lf_alpha_offset); s5p_mfc_set_enc_params_h264()
913 writel(reg, mfc_regs->e_h264_lf_beta_offset); s5p_mfc_set_enc_params_h264()
919 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
925 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
931 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
934 writel(0x0, mfc_regs->e_mb_rc_config); s5p_mfc_set_enc_params_h264()
945 writel(reg, mfc_regs->e_mb_rc_config); s5p_mfc_set_enc_params_h264()
952 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
954 writel(0x0, mfc_regs->e_aspect_ratio); s5p_mfc_set_enc_params_h264()
955 writel(0x0, mfc_regs->e_extended_sar); s5p_mfc_set_enc_params_h264()
960 writel(reg, mfc_regs->e_aspect_ratio); s5p_mfc_set_enc_params_h264()
966 writel(reg, mfc_regs->e_extended_sar); s5p_mfc_set_enc_params_h264()
975 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
978 writel(0x0, mfc_regs->e_h264_i_period); s5p_mfc_set_enc_params_h264()
982 writel(reg, mfc_regs->e_h264_i_period); s5p_mfc_set_enc_params_h264()
988 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
993 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
999 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
1005 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
1010 writel(reg, mfc_regs->e_h264_num_t_layer); s5p_mfc_set_enc_params_h264()
1014 writel(p_h264->hier_qp_layer_qp[i], s5p_mfc_set_enc_params_h264()
1020 writel(reg, mfc_regs->e_h264_num_t_layer); s5p_mfc_set_enc_params_h264()
1026 writel(reg, mfc_regs->e_h264_options); s5p_mfc_set_enc_params_h264()
1033 writel(reg, mfc_regs->e_h264_frame_packing_sei_info); s5p_mfc_set_enc_params_h264()
1042 writel(p_h264->fmo_run_len[i] - 1, s5p_mfc_set_enc_params_h264()
1054 writel(p_h264->fmo_chg_dir & 0x1, s5p_mfc_set_enc_params_h264()
1057 writel(p_h264->fmo_chg_rate, s5p_mfc_set_enc_params_h264()
1068 writel(p_h264->fmo_map_type, s5p_mfc_set_enc_params_h264()
1070 writel(p_h264->fmo_slice_grp - 1, s5p_mfc_set_enc_params_h264()
1073 writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1); s5p_mfc_set_enc_params_h264()
1097 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params_mpeg4()
1105 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_mpeg4()
1112 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_mpeg4()
1117 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_mpeg4()
1125 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_mpeg4()
1128 writel(0x0, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_mpeg4()
1134 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_mpeg4()
1142 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_mpeg4()
1148 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); s5p_mfc_set_enc_params_mpeg4()
1151 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); s5p_mfc_set_enc_params_mpeg4()
1155 writel(0x0, mfc_regs->e_mpeg4_options); s5p_mfc_set_enc_params_mpeg4()
1156 writel(0x0, mfc_regs->e_mpeg4_hec_period); s5p_mfc_set_enc_params_mpeg4()
1179 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_h263()
1186 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h263()
1191 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_h263()
1199 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_h263()
1202 writel(0x0, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_h263()
1208 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_h263()
1216 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_h263()
1222 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); s5p_mfc_set_enc_params_h263()
1225 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); s5p_mfc_set_enc_params_h263()
1250 writel(reg, mfc_regs->e_gop_config); s5p_mfc_set_enc_params_vp8()
1254 writel(reg, mfc_regs->e_picture_profile); s5p_mfc_set_enc_params_vp8()
1261 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_vp8()
1268 writel(reg, mfc_regs->e_rc_frame_rate); s5p_mfc_set_enc_params_vp8()
1274 writel(reg, mfc_regs->e_rc_config); s5p_mfc_set_enc_params_vp8()
1277 writel(0x0, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_vp8()
1282 writel(reg, mfc_regs->e_fixed_picture_qp); s5p_mfc_set_enc_params_vp8()
1289 writel(reg, mfc_regs->e_rc_qp_bound); s5p_mfc_set_enc_params_vp8()
1294 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size); s5p_mfc_set_enc_params_vp8()
1297 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay); s5p_mfc_set_enc_params_vp8()
1319 writel(reg, mfc_regs->e_vp8_options); s5p_mfc_set_enc_params_vp8()
1347 writel(ctx->display_delay, mfc_regs->d_display_delay); s5p_mfc_init_decode_v6()
1351 writel(reg, mfc_regs->d_dec_options); s5p_mfc_init_decode_v6()
1366 writel(reg, mfc_regs->d_init_buffer_options); s5p_mfc_init_decode_v6()
1368 writel(reg, mfc_regs->d_dec_options); s5p_mfc_init_decode_v6()
1372 writel(0x1, mfc_regs->pixel_format); s5p_mfc_init_decode_v6()
1374 writel(0x0, mfc_regs->pixel_format); s5p_mfc_init_decode_v6()
1378 writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable); s5p_mfc_init_decode_v6()
1380 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_init_decode_v6()
1395 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_set_flush()
1408 writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower); s5p_mfc_decode_one_frame_v6()
1409 writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable); s5p_mfc_decode_one_frame_v6()
1411 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_decode_one_frame_v6()
1453 writel(ctx->img_width, mfc_regs->e_source_first_plane_stride); s5p_mfc_init_encode_v6()
1454 writel(ctx->img_width, mfc_regs->e_source_second_plane_stride); s5p_mfc_init_encode_v6()
1457 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_init_encode_v6()
1474 writel(p_h264->aso_slice_order[i], s5p_mfc_h264_set_aso_slice_order_v6()
1502 writel(ctx->inst_no, mfc_regs->instance_id); s5p_mfc_encode_one_frame_v6()
1867 writel(0, mfc_regs->risc2host_command); s5p_mfc_clear_int_flags_v6()
1868 writel(0, mfc_regs->risc2host_int); s5p_mfc_clear_int_flags_v6()
1875 writel(data, (void __iomem *)((unsigned long)ofs)); s5p_mfc_write_info_v6()
/linux-4.4.14/drivers/isdn/hisax/
H A Dtelespci.c51 writel(WRITE_ADDR_ISAC | off, adr + 0x200); readisac()
55 writel(READ_DATA_ISAC, adr + 0x200); readisac()
68 writel(WRITE_ADDR_ISAC | off, adr + 0x200); writeisac()
72 writel(WRITE_DATA_ISAC | data, adr + 0x200); writeisac()
83 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); readhscx()
87 writel(READ_DATA_HSCX, adr + 0x200); readhscx()
99 writel(WRITE_ADDR_HSCX | ((hscx ? 0x40 : 0) + off), adr + 0x200); writehscx()
103 writel(WRITE_DATA_HSCX | data, adr + 0x200); writehscx()
117 writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200); read_fifo_isac()
119 writel(READ_DATA_ISAC, adr + 0x200); read_fifo_isac()
135 writel(WRITE_ADDR_ISAC | 0x1E, adr + 0x200); write_fifo_isac()
137 writel(WRITE_DATA_ISAC | data[i], adr + 0x200); write_fifo_isac()
152 writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200); read_fifo_hscx()
154 writel(READ_DATA_HSCX, adr + 0x200); read_fifo_hscx()
170 writel(WRITE_ADDR_HSCX | (hscx ? 0x5F : 0x1F), adr + 0x200); write_fifo_hscx()
172 writel(WRITE_DATA_HSCX | data[i], adr + 0x200); write_fifo_hscx()
246 writel(0x70000000, cs->hw.teles0.membase + 0x3C); telespci_interrupt()
317 writel(0x00000000, cs->hw.teles0.membase + 0x28); setup_telespci()
318 writel(0x01000000, cs->hw.teles0.membase + 0x28); setup_telespci()
319 writel(0x01000000, cs->hw.teles0.membase + 0x28); setup_telespci()
320 writel(0x7BFFFFFF, cs->hw.teles0.membase + 0x2C); setup_telespci()
321 writel(0x70000000, cs->hw.teles0.membase + 0x3C); setup_telespci()
322 writel(0x61000000, cs->hw.teles0.membase + 0x40); setup_telespci()
323 /* writel(0x00800000, cs->hw.teles0.membase + 0x200); */ setup_telespci()
/linux-4.4.14/drivers/media/platform/exynos4-is/
H A Dfimc-lite-reg.c30 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_reset()
40 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_reset()
47 writel(cfg, dev->regs + FLITE_REG_CISTATUS); flite_hw_clear_pending_irq()
61 writel(cfg, dev->regs + FLITE_REG_CISTATUS2); flite_hw_clear_last_capture_end()
83 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_set_interrupt_mask()
90 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); flite_hw_capture_start()
97 writel(cfg, dev->regs + FLITE_REG_CIIMGCPT); flite_hw_capture_stop()
111 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_set_test_pattern()
150 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_set_source_format()
157 writel(cfg, dev->regs + FLITE_REG_CISRCSIZE); flite_hw_set_source_format()
170 writel(cfg, dev->regs + FLITE_REG_CIWDOFST); flite_hw_set_window_offset()
176 writel(cfg, dev->regs + FLITE_REG_CIWDOFST2); flite_hw_set_window_offset()
187 writel(cfg, dev->regs + FLITE_REG_CIGENERAL); flite_hw_set_camera_port()
215 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_set_camera_bus()
229 writel(cfg, dev->regs + FLITE_REG_CIODMAFMT); flite_hw_set_pack12()
247 writel(cfg | pixcode[i][1], dev->regs + FLITE_REG_CIODMAFMT); flite_hw_set_out_order()
258 writel(cfg, dev->regs + FLITE_REG_CIOCAN); flite_hw_set_dma_window()
264 writel(cfg, dev->regs + FLITE_REG_CIOOFF); flite_hw_set_dma_window()
278 writel(buf->paddr, dev->regs + FLITE_REG_CIOSA); flite_hw_set_dma_buffer()
280 writel(buf->paddr, dev->regs + FLITE_REG_CIOSAN(index - 1)); flite_hw_set_dma_buffer()
284 writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ); flite_hw_set_dma_buffer()
296 writel(cfg, dev->regs + FLITE_REG_CIFCNTSEQ); flite_hw_mask_dma_buffer()
307 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_set_output_dma()
312 writel(cfg, dev->regs + FLITE_REG_CIGCTRL); flite_hw_set_output_dma()
H A Dfimc-reg.c28 writel(cfg, dev->regs + FIMC_REG_CISRCFMT); fimc_hw_reset()
33 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); fimc_hw_reset()
38 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); fimc_hw_reset()
97 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); fimc_hw_set_rotation()
103 writel(flip, dev->regs + FIMC_REG_MSCTRL); fimc_hw_set_rotation()
142 writel(cfg, dev->regs + FIMC_REG_CITRGFMT); fimc_hw_set_target_format()
147 writel(cfg, dev->regs + FIMC_REG_CITAREA); fimc_hw_set_target_format()
157 writel(cfg, dev->regs + FIMC_REG_ORGOSIZE); fimc_hw_set_out_dma_size()
165 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); fimc_hw_set_out_dma_size()
179 writel(cfg, dev->regs + FIMC_REG_CIOYOFF); fimc_hw_set_out_dma()
182 writel(cfg, dev->regs + FIMC_REG_CIOCBOFF); fimc_hw_set_out_dma()
185 writel(cfg, dev->regs + FIMC_REG_CIOCROFF); fimc_hw_set_out_dma()
211 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); fimc_hw_set_out_dma()
221 writel(cfg, dev->regs + FIMC_REG_ORGISIZE); fimc_hw_en_autoload()
231 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); fimc_hw_en_lastirq()
244 writel(cfg, dev->regs + FIMC_REG_CISCPRERATIO); fimc_hw_set_prescaler()
247 writel(cfg, dev->regs + FIMC_REG_CISCPREDST); fimc_hw_set_prescaler()
311 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); fimc_hw_set_scaler()
333 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); fimc_hw_set_mainscaler()
341 writel(cfg, dev->regs + FIMC_REG_CIEXTEN); fimc_hw_set_mainscaler()
345 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); fimc_hw_set_mainscaler()
363 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); fimc_hw_enable_capture()
371 writel(cfg, dev->regs + FIMC_REG_CIIMGCPT); fimc_hw_disable_capture()
388 writel(cfg, dev->regs + FIMC_REG_CIIMGEFF); fimc_hw_set_effect()
403 writel(cfg, dev->regs + FIMC_REG_CIOCTRL); fimc_hw_set_rgb_alpha()
419 writel(cfg_o, dev->regs + FIMC_REG_ORGISIZE); fimc_hw_set_in_dma_size()
420 writel(cfg_r, dev->regs + FIMC_REG_CIREAL_ISIZE); fimc_hw_set_in_dma_size()
432 writel(cfg, dev->regs + FIMC_REG_CIIYOFF); fimc_hw_set_in_dma()
435 writel(cfg, dev->regs + FIMC_REG_CIICBOFF); fimc_hw_set_in_dma()
438 writel(cfg, dev->regs + FIMC_REG_CIICROFF); fimc_hw_set_in_dma()
490 writel(cfg, dev->regs + FIMC_REG_MSCTRL); fimc_hw_set_in_dma()
502 writel(cfg, dev->regs + FIMC_REG_CIDMAPARAM); fimc_hw_set_in_dma()
518 writel(cfg, dev->regs + FIMC_REG_MSCTRL); fimc_hw_set_input_path()
529 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); fimc_hw_set_output_path()
536 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); fimc_hw_set_input_addr()
538 writel(paddr->y, dev->regs + FIMC_REG_CIIYSA(0)); fimc_hw_set_input_addr()
539 writel(paddr->cb, dev->regs + FIMC_REG_CIICBSA(0)); fimc_hw_set_input_addr()
540 writel(paddr->cr, dev->regs + FIMC_REG_CIICRSA(0)); fimc_hw_set_input_addr()
543 writel(cfg, dev->regs + FIMC_REG_CIREAL_ISIZE); fimc_hw_set_input_addr()
551 writel(paddr->y, dev->regs + FIMC_REG_CIOYSA(i)); fimc_hw_set_output_addr()
552 writel(paddr->cb, dev->regs + FIMC_REG_CIOCBSA(i)); fimc_hw_set_output_addr()
553 writel(paddr->cr, dev->regs + FIMC_REG_CIOCRSA(i)); fimc_hw_set_output_addr()
583 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); fimc_hw_set_camera_polarity()
645 writel(cfg, fimc->regs + FIMC_REG_CISRCFMT); fimc_hw_set_camera_source()
659 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST); fimc_hw_set_camera_offset()
665 writel(cfg, fimc->regs + FIMC_REG_CIWDOFST2); fimc_hw_set_camera_offset()
708 writel(tmp, fimc->regs + FIMC_REG_CSIIMGFMT); fimc_hw_set_camera_type()
729 writel(cfg, fimc->regs + FIMC_REG_CIGCTRL); fimc_hw_set_camera_type()
738 writel(cfg, dev->regs + FIMC_REG_CIGCTRL); fimc_hw_clear_irq()
748 writel(cfg, dev->regs + FIMC_REG_CISCCTRL); fimc_hw_enable_scaler()
758 writel(cfg, dev->regs + FIMC_REG_MSCTRL); fimc_hw_activate_input_dma()
/linux-4.4.14/drivers/net/hippi/
H A Drrunner.c189 writel(readl(&rrpriv->regs->HostCtrl) | NO_SWAP, rr_init_one()
231 writel(HALT_NIC, &rr->regs->HostCtrl); rr_remove_one()
272 writel(*(u32*)(cmd), &regs->CmdRing[idx]); rr_issue_cmd()
300 writel(0x01000000, &regs->TX_state); rr_reset()
301 writel(0xff800000, &regs->RX_state); rr_reset()
302 writel(0, &regs->AssistState); rr_reset()
303 writel(CLEAR_INTA, &regs->LocalCtrl); rr_reset()
304 writel(0x01, &regs->BrkPt); rr_reset()
305 writel(0, &regs->Timer); rr_reset()
306 writel(0, &regs->TimerRef); rr_reset()
307 writel(RESET_DMA, &regs->DmaReadState); rr_reset()
308 writel(RESET_DMA, &regs->DmaWriteState); rr_reset()
309 writel(0, &regs->DmaWriteHostHi); rr_reset()
310 writel(0, &regs->DmaWriteHostLo); rr_reset()
311 writel(0, &regs->DmaReadHostHi); rr_reset()
312 writel(0, &regs->DmaReadHostLo); rr_reset()
313 writel(0, &regs->DmaReadLen); rr_reset()
314 writel(0, &regs->DmaWriteLen); rr_reset()
315 writel(0, &regs->DmaWriteLcl); rr_reset()
316 writel(0, &regs->DmaWriteIPchecksum); rr_reset()
317 writel(0, &regs->DmaReadLcl); rr_reset()
318 writel(0, &regs->DmaReadIPchecksum); rr_reset()
319 writel(0, &regs->PciState); rr_reset()
321 writel(SWAP_DATA | PTR64BIT | PTR_WD_SWAP, &regs->Mode); rr_reset()
323 writel(SWAP_DATA | PTR64BIT | PTR_WD_NOSWAP, &regs->Mode); rr_reset()
325 writel(SWAP_DATA | PTR32BIT | PTR_WD_NOSWAP, &regs->Mode); rr_reset()
332 writel(0xdf000, &regs->RxBase); rr_reset()
333 writel(0xdf000, &regs->RxPrd); rr_reset()
334 writel(0xdf000, &regs->RxCon); rr_reset()
335 writel(0xce000, &regs->TxBase); rr_reset()
336 writel(0xce000, &regs->TxPrd); rr_reset()
337 writel(0xce000, &regs->TxCon); rr_reset()
338 writel(0, &regs->RxIndPro); rr_reset()
339 writel(0, &regs->RxIndCon); rr_reset()
340 writel(0, &regs->RxIndRef); rr_reset()
341 writel(0, &regs->TxIndPro); rr_reset()
342 writel(0, &regs->TxIndCon); rr_reset()
343 writel(0, &regs->TxIndRef); rr_reset()
344 writel(0xcc000, &regs->pad10[0]); rr_reset()
345 writel(0, &regs->DrCmndPro); rr_reset()
346 writel(0, &regs->DrCmndCon); rr_reset()
347 writel(0, &regs->DwCmndPro); rr_reset()
348 writel(0, &regs->DwCmndCon); rr_reset()
349 writel(0, &regs->DwCmndRef); rr_reset()
350 writel(0, &regs->DrDataPro); rr_reset()
351 writel(0, &regs->DrDataCon); rr_reset()
352 writel(0, &regs->DrDataRef); rr_reset()
353 writel(0, &regs->DwDataPro); rr_reset()
354 writel(0, &regs->DwDataCon); rr_reset()
355 writel(0, &regs->DwDataRef); rr_reset()
358 writel(0xffffffff, &regs->MbEvent); rr_reset()
359 writel(0, &regs->Event); rr_reset()
361 writel(0, &regs->TxPi); rr_reset()
362 writel(0, &regs->IpRxPi); rr_reset()
364 writel(0, &regs->EvtCon); rr_reset()
365 writel(0, &regs->EvtPrd); rr_reset()
370 writel(0, &regs->CmdRing[i]); rr_reset()
375 writel(RBURST_64|WBURST_64, &regs->PciState); rr_reset()
386 writel(start_pc + 0x800, &regs->Pc); rr_reset()
390 writel(start_pc, &regs->Pc); rr_reset()
409 writel(0, &regs->ExtIo); rr_read_eeprom()
411 writel(0, &regs->LocalCtrl); rr_read_eeprom()
413 writel(host | HALT_NIC, &regs->HostCtrl); rr_read_eeprom()
417 writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase); rr_read_eeprom()
423 writel(host, &regs->HostCtrl); rr_read_eeprom()
424 writel(misc, &regs->LocalCtrl); rr_read_eeprom()
425 writel(io, &regs->ExtIo); rr_read_eeprom()
461 writel(0, &regs->ExtIo); write_eeprom()
463 writel(ENABLE_EEPROM_WRITE, &regs->LocalCtrl); write_eeprom()
467 writel((EEPROM_BASE + ((offset+i) << 3)), &regs->WinBase); write_eeprom()
475 writel(data, &regs->WinData); write_eeprom()
496 writel(misc, &regs->LocalCtrl); write_eeprom()
497 writel(io, &regs->ExtIo); write_eeprom()
571 writel(hostctrl | HALT_NIC | RR_CLEAR_INT, &regs->HostCtrl); rr_init1()
597 writel(0, &regs->CmdRing[i]); rr_init1()
624 writel(0x5000, &regs->ConRetry); rr_init1()
625 writel(0x100, &regs->ConRetryTmr); rr_init1()
626 writel(0x500000, &regs->ConTmout); rr_init1()
627 writel(0x60, &regs->IntrTmr); rr_init1()
628 writel(0x500000, &regs->TxDataMvTimeout); rr_init1()
629 writel(0x200000, &regs->RxDataMvTimeout); rr_init1()
630 writel(0x80, &regs->WriteDmaThresh); rr_init1()
631 writel(0x80, &regs->ReadDmaThresh); rr_init1()
637 writel(hostctrl, &regs->HostCtrl); rr_init1()
742 writel(RX_RING_ENTRIES - 1, &regs->IpRxPi); rr_handle_event()
762 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
769 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
793 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
805 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
812 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
819 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
826 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
880 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
887 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
894 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_handle_event()
1011 writel(index, &regs->IpRxPi); rx_int()
1099 writel(eidx, &regs->EvtCon); rr_interrupt()
1167 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, rr_timer()
1216 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl); rr_open()
1244 writel(readl(&regs->HostCtrl)|HALT_NIC|RR_CLEAR_INT, &regs->HostCtrl); rr_open()
1351 writel(tmp, &regs->HostCtrl); rr_close()
1359 writel(0, &regs->TxPi); rr_close()
1360 writel(0, &regs->IpRxPi); rr_close()
1362 writel(0, &regs->EvtCon); rr_close()
1363 writel(0, &regs->EvtPrd); rr_close()
1366 writel(0, &regs->CmdRing[i]); rr_close()
1447 writel(txctrl->pi, &regs->TxPi); rr_start_xmit()
1489 writel(0, &regs->LocalCtrl); rr_load_firmware()
1491 writel(0, &regs->EvtPrd); rr_load_firmware()
1492 writel(0, &regs->RxPrd); rr_load_firmware()
1493 writel(0, &regs->TxPrd); rr_load_firmware()
1501 writel(0, &regs->ExtIo); rr_load_firmware()
1505 writel(i * 4, &regs->WinBase); rr_load_firmware()
1507 writel(0, &regs->WinData); rr_load_firmware()
1510 writel(io, &regs->ExtIo); rr_load_firmware()
1556 writel(sptr, &regs->WinBase); rr_load_firmware()
1558 writel(tmp, &regs->WinData); rr_load_firmware()
1566 writel(localctrl, &regs->LocalCtrl); rr_load_firmware()
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_hwtstamp.c33 writel(data, ioaddr + PTP_TCR); stmmac_config_hw_tstamping()
51 writel(data, ioaddr + PTP_SSIR); stmmac_config_sub_second_increment()
59 writel(sec, ioaddr + PTP_STSUR); stmmac_init_systime()
60 writel(nsec, ioaddr + PTP_STNSUR); stmmac_init_systime()
64 writel(value, ioaddr + PTP_TCR); stmmac_init_systime()
84 writel(addend, ioaddr + PTP_TAR); stmmac_config_addend()
88 writel(value, ioaddr + PTP_TCR); stmmac_config_addend()
109 writel(sec, ioaddr + PTP_STSUR); stmmac_adjust_systime()
110 writel(((add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec), stmmac_adjust_systime()
115 writel(value, ioaddr + PTP_TCR); stmmac_adjust_systime()
H A Ddwmac100_core.c40 writel((value | MAC_CORE_INIT), ioaddr + MAC_CONTROL); dwmac100_core_init()
43 writel(ETH_P_8021Q, ioaddr + MAC_VLAN1); dwmac100_core_init()
112 writel(0xffffffff, ioaddr + MAC_HASH_HIGH); dwmac100_set_filter()
113 writel(0xffffffff, ioaddr + MAC_HASH_LOW); dwmac100_set_filter()
140 writel(mc_filter[0], ioaddr + MAC_HASH_LOW);
141 writel(mc_filter[1], ioaddr + MAC_HASH_HIGH);
144 writel(value, ioaddr + MAC_CONTROL);
155 writel(flow, ioaddr + MAC_FLOW_CTRL); dwmac100_flow_ctrl()
H A Ddwmac_lib.c32 writel(1, ioaddr + DMA_XMT_POLL_DEMAND); dwmac_enable_dma_transmission()
37 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); dwmac_enable_dma_irq()
42 writel(0, ioaddr + DMA_INTR_ENA); dwmac_disable_dma_irq()
49 writel(value, ioaddr + DMA_CONTROL); dwmac_dma_start_tx()
56 writel(value, ioaddr + DMA_CONTROL); dwmac_dma_stop_tx()
63 writel(value, ioaddr + DMA_CONTROL); dwmac_dma_start_rx()
70 writel(value, ioaddr + DMA_CONTROL); dwmac_dma_stop_rx()
209 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS); dwmac_dma_interrupt()
217 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); dwmac_dma_flush_tx_fifo()
232 writel(data | GMAC_HI_REG_AE, ioaddr + high); stmmac_set_mac_addr()
234 writel(data, ioaddr + low); stmmac_set_mac_addr()
247 writel(value, ioaddr + MAC_CTRL_REG); stmmac_set_mac()
H A Ddwmac1000_core.c45 writel(value, ioaddr + GMAC_CONTROL); dwmac1000_core_init()
48 writel(0x207, ioaddr + GMAC_INT_MASK); dwmac1000_core_init()
52 writel(0x0, ioaddr + GMAC_VLAN_TAG); dwmac1000_core_init()
66 writel(value, ioaddr + GMAC_CONTROL); dwmac1000_rx_ipc_enable()
111 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW); dwmac1000_set_mchash()
112 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH); dwmac1000_set_mchash()
127 writel(mcfilterbits[regs], dwmac1000_set_mchash()
196 writel(value, ioaddr + GMAC_FRAME_FILTER);
224 writel(flow, ioaddr + GMAC_FLOW_CTRL); dwmac1000_flow_ctrl()
241 writel(pmt, ioaddr + GMAC_PMT); dwmac1000_pmt()
323 writel(value, ioaddr + LPI_CTRL_STATUS); dwmac1000_set_eee_mode()
333 writel(value, ioaddr + LPI_CTRL_STATUS); dwmac1000_reset_eee_mode()
348 writel(value, ioaddr + LPI_CTRL_STATUS); dwmac1000_set_eee_pls()
363 writel(value, ioaddr + LPI_TIMER_CTRL); dwmac1000_set_eee_timer()
375 writel(value, ioaddr + GMAC_AN_CTRL); dwmac1000_ctrl_ane()
H A Ddwmac100_dma.c43 writel(value, ioaddr + DMA_BUS_MODE); dwmac100_dma_init()
54 writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), dwmac100_dma_init()
58 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA); dwmac100_dma_init()
63 writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR); dwmac100_dma_init()
64 writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR); dwmac100_dma_init()
86 writel(csr6, ioaddr + DMA_CONTROL); dwmac100_dma_operation_mode()
/linux-4.4.14/drivers/gpio/
H A Dgpio-sta2x11.c82 writel(bit, &regs->dats); gsta_gpio_set()
84 writel(bit, &regs->datc); gsta_gpio_set()
103 writel(bit, &regs->dirs); gsta_gpio_direction_output()
106 writel(bit, &regs->dats); gsta_gpio_direction_output()
108 writel(bit, &regs->datc); gsta_gpio_direction_output()
118 writel(bit, &regs->dirc); gsta_gpio_direction_input()
186 writel(val | bit, &regs->afsela); gsta_set_config()
195 writel(bit, &regs->dirs); gsta_set_config()
196 writel(bit, &regs->datc); gsta_set_config()
199 writel(bit, &regs->dirs); gsta_set_config()
200 writel(bit, &regs->dats); gsta_set_config()
203 writel(bit, &regs->dirc); gsta_set_config()
205 writel(val, &regs->pdis); gsta_set_config()
208 writel(bit, &regs->dirc); gsta_set_config()
210 writel(val, &regs->pdis); gsta_set_config()
211 writel(bit, &regs->dats); gsta_set_config()
214 writel(bit, &regs->dirc); gsta_set_config()
216 writel(val, &regs->pdis); gsta_set_config()
217 writel(bit, &regs->datc); gsta_set_config()
245 writel(val, &regs->rimsc); gsta_irq_disable()
249 writel(val, &regs->fimsc); gsta_irq_disable()
271 writel(val | bit, &regs->rimsc); gsta_irq_enable()
273 writel(val & ~bit, &regs->rimsc); gsta_irq_enable()
276 writel(val | bit, &regs->fimsc); gsta_irq_enable()
278 writel(val & ~bit, &regs->fimsc); gsta_irq_enable()
316 writel(1 << nr, &regs->ic); gsta_gpio_handler()
384 writel(0, &chip->regs[i]->rimsc); gsta_probe()
385 writel(0, &chip->regs[i]->fimsc); gsta_probe()
386 writel(~0, &chip->regs[i]->ic); gsta_probe()
H A Dgpio-mb86s7x.c67 writel(val, gchip->base + PFR(gpio)); mb86s70_gpio_request()
84 writel(val, gchip->base + PFR(gpio)); mb86s70_gpio_free()
99 writel(val, gchip->base + DDR(gpio)); mb86s70_gpio_direction_input()
120 writel(val, gchip->base + PDR(gpio)); mb86s70_gpio_direction_output()
124 writel(val, gchip->base + DDR(gpio)); mb86s70_gpio_direction_output()
151 writel(val, gchip->base + PDR(gpio)); mb86s70_gpio_set()
/linux-4.4.14/drivers/video/fbdev/geode/
H A Ddisplay_gx1.c90 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK); gx1_set_mode()
97 writel(tcfg, par->dc_regs + DC_TIMING_CFG); gx1_set_mode()
104 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); gx1_set_mode()
108 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); gx1_set_mode()
114 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); gx1_set_mode()
135 writel(0, par->dc_regs + DC_FB_ST_OFFSET); gx1_set_mode()
138 writel(info->fix.line_length >> 2, par->dc_regs + DC_LINE_DELTA); gx1_set_mode()
139 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2, gx1_set_mode()
166 writel(val, par->dc_regs + DC_H_TIMING_1); gx1_set_mode()
168 writel(val, par->dc_regs + DC_H_TIMING_2); gx1_set_mode()
170 writel(val, par->dc_regs + DC_H_TIMING_3); gx1_set_mode()
171 writel(val, par->dc_regs + DC_FP_H_TIMING); gx1_set_mode()
173 writel(val, par->dc_regs + DC_V_TIMING_1); gx1_set_mode()
175 writel(val, par->dc_regs + DC_V_TIMING_2); gx1_set_mode()
177 writel(val, par->dc_regs + DC_V_TIMING_3); gx1_set_mode()
179 writel(val, par->dc_regs + DC_FP_V_TIMING); gx1_set_mode()
182 writel(ocfg, par->dc_regs + DC_OUTPUT_CFG); gx1_set_mode()
183 writel(tcfg, par->dc_regs + DC_TIMING_CFG); gx1_set_mode()
185 writel(gcfg, par->dc_regs + DC_GENERAL_CFG); gx1_set_mode()
190 writel(0, par->dc_regs + DC_UNLOCK); gx1_set_mode()
207 writel(regno, par->dc_regs + DC_PAL_ADDRESS); gx1_set_hw_palette_reg()
208 writel(val, par->dc_regs + DC_PAL_DATA); gx1_set_hw_palette_reg()
H A Dvideo_cs5530.c92 writel(value, par->vid_regs + CS5530_DOT_CLK_CONFIG); cs5530_set_dclk_frequency()
93 writel(value | 0x80000100, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* set reset and bypass */ cs5530_set_dclk_frequency()
95 writel(value & 0x7FFFFFFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear reset */ cs5530_set_dclk_frequency()
96 writel(value & 0x7FFFFEFF, par->vid_regs + CS5530_DOT_CLK_CONFIG); /* clear bypass */ cs5530_set_dclk_frequency()
134 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); cs5530_configure_display()
184 writel(dcfg, par->vid_regs + CS5530_DISPLAY_CONFIG); cs5530_blank_display()
/linux-4.4.14/drivers/gpu/ipu-v3/
H A Dipu-dp.c101 writel(reg, flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
105 writel(reg | ((u32) alpha << 24), ipu_dp_set_global_alpha()
109 writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
112 writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); ipu_dp_set_global_alpha()
128 writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS); ipu_dp_set_window_pos()
147 writel(reg, flow->base + DP_COM_CONF); ipu_dp_csc_init()
152 writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0); ipu_dp_csc_init()
153 writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1); ipu_dp_csc_init()
154 writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2); ipu_dp_csc_init()
155 writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3); ipu_dp_csc_init()
156 writel(0x3d6 | (0x0000 << 16) | (2 << 30), ipu_dp_csc_init()
158 writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30), ipu_dp_csc_init()
161 writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0); ipu_dp_csc_init()
162 writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1); ipu_dp_csc_init()
163 writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2); ipu_dp_csc_init()
164 writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3); ipu_dp_csc_init()
165 writel(0x000 | (0x3e42 << 16) | (1 << 30), ipu_dp_csc_init()
167 writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30), ipu_dp_csc_init()
173 writel(reg, flow->base + DP_COM_CONF); ipu_dp_csc_init()
248 writel(reg, flow->base + DP_COM_CONF); ipu_dp_enable_channel()
275 writel(reg, flow->base + DP_COM_CONF); ipu_dp_disable_channel()
277 writel(0, flow->base + DP_FG_POS); ipu_dp_disable_channel()
H A Dipu-dc.c127 writel(reg, dc->base + DC_RL_CH(event)); dc_link_event()
146 writel(reg1, priv->dc_tmpl_reg + word * 8); dc_write_tmpl()
147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); dc_write_tmpl()
232 writel(reg, dc->base + DC_WR_CH_CONF); ipu_dc_init_sync()
234 writel(0x0, dc->base + DC_WR_CH_ADDR); ipu_dc_init_sync()
235 writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di)); ipu_dc_init_sync()
265 writel(reg, dc->base + DC_WR_CH_CONF); ipu_dc_enable_channel()
276 writel(reg, dc->base + DC_WR_CH_CONF); dc_irq_handler()
308 writel(val, dc->base + DC_WR_CH_CONF); ipu_dc_disable_channel()
339 writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr)); ipu_dc_map_config()
344 writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map)); ipu_dc_map_config()
351 writel(reg & ~(0xffff << (16 * (map & 0x1))), ipu_dc_map_clear()
434 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) | ipu_dc_init()
437 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0), ipu_dc_init()
440 writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, ipu_dc_init()
/linux-4.4.14/arch/arm/mach-cns3xxx/
H A Dcore.c107 writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); cns3xxx_power_off()
118 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_shutdown()
128 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_set_oneshot()
139 writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_set_periodic()
141 writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_set_periodic()
150 writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); cns3xxx_timer_set_next_event()
151 writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); cns3xxx_timer_set_next_event()
188 writel(val & ~(1 << 2), stat); cns3xxx_timer_interrupt()
214 writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
216 writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); __cns3xxx_timer_init()
219 writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); __cns3xxx_timer_init()
220 writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); __cns3xxx_timer_init()
222 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); __cns3xxx_timer_init()
223 writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); __cns3xxx_timer_init()
229 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); __cns3xxx_timer_init()
234 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
237 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); __cns3xxx_timer_init()
238 writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); __cns3xxx_timer_init()
243 writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); __cns3xxx_timer_init()
248 writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); __cns3xxx_timer_init()
284 writel(val, base + L310_TAG_LATENCY_CTRL); cns3xxx_l2x0_init()
297 writel(val, base + L310_DATA_LATENCY_CTRL); cns3xxx_l2x0_init()
/linux-4.4.14/arch/mips/ar7/
H A Dirq.c54 writel(1 << ((d->irq - ar7_irq_base) % 32), ar7_unmask_irq()
60 writel(1 << ((d->irq - ar7_irq_base) % 32), ar7_mask_irq()
66 writel(1 << ((d->irq - ar7_irq_base) % 32), ar7_ack_irq()
72 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); ar7_unmask_sec_irq()
77 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); ar7_mask_sec_irq()
82 writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); ar7_ack_sec_irq()
111 writel(0xffffffff, REG(ECR_OFFSET(0))); ar7_irq_init()
112 writel(0xff, REG(ECR_OFFSET(32))); ar7_irq_init()
113 writel(0xffffffff, REG(SEC_ECR_OFFSET)); ar7_irq_init()
114 writel(0xffffffff, REG(CR_OFFSET(0))); ar7_irq_init()
115 writel(0xff, REG(CR_OFFSET(32))); ar7_irq_init()
116 writel(0xffffffff, REG(SEC_CR_OFFSET)); ar7_irq_init()
121 writel(i, REG(CHNL_OFFSET(i))); ar7_irq_init()
156 writel(1, REG(CR_OFFSET(irq))); ar7_cascade()
H A Dgpio.c64 writel(tmp, gpio_out); ar7_gpio_set_value()
79 writel(tmp, gpio >> 5 ? gpio_out1 : gpio_out0); titan_gpio_set_value()
88 writel(readl(gpio_dir) | (1 << gpio), gpio_dir); ar7_gpio_direction_input()
103 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) | (1 << (gpio & 0x1f)), titan_gpio_direction_input()
116 writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); ar7_gpio_direction_output()
133 writel(readl(gpio >> 5 ? gpio_dir1 : gpio_dir0) & ~(1 << titan_gpio_direction_output()
167 writel(readl(gpio_en) | (1 << gpio), gpio_en); ar7_gpio_enable_ar7()
177 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) | (1 << (gpio & 0x1f)), ar7_gpio_enable_titan()
194 writel(readl(gpio_en) & ~(1 << gpio), gpio_en); ar7_gpio_disable_ar7()
204 writel(readl(gpio >> 5 ? gpio_en1 : gpio_en0) & ~(1 << (gpio & 0x1f)), ar7_gpio_disable_titan()
300 writel(tmp, pin_sel + pin_sel_reg); titan_gpio_pinsel()
H A Dclock.c241 writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); tnetd7300_set_clock()
243 writel(4, &clock->pll); tnetd7300_set_clock()
246 writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); tnetd7300_set_clock()
282 writel(0, &clock->ctrl); tnetd7200_set_clock()
283 writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv); tnetd7200_set_clock()
284 writel((mul - 1) & 0xF, &clock->mul); tnetd7200_set_clock()
289 writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv); tnetd7200_set_clock()
291 writel(readl(&clock->cmden) | 1, &clock->cmden); tnetd7200_set_clock()
292 writel(readl(&clock->cmd) | 1, &clock->cmd); tnetd7200_set_clock()
297 writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); tnetd7200_set_clock()
299 writel(readl(&clock->cmden) | 1, &clock->cmden); tnetd7200_set_clock()
300 writel(readl(&clock->cmd) | 1, &clock->cmd); tnetd7200_set_clock()
305 writel(readl(&clock->ctrl) | 1, &clock->ctrl); tnetd7200_set_clock()
/linux-4.4.14/arch/arm/mach-sunxi/
H A Dplatsmp.c83 writel(virt_to_phys(secondary_startup), sun6i_smp_boot_secondary()
87 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); sun6i_smp_boot_secondary()
91 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); sun6i_smp_boot_secondary()
95 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); sun6i_smp_boot_secondary()
99 writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu)); sun6i_smp_boot_secondary()
104 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); sun6i_smp_boot_secondary()
108 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); sun6i_smp_boot_secondary()
112 writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG); sun6i_smp_boot_secondary()
165 writel(virt_to_phys(secondary_startup), sun8i_smp_boot_secondary()
169 writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); sun8i_smp_boot_secondary()
173 writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG); sun8i_smp_boot_secondary()
177 writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG); sun8i_smp_boot_secondary()
181 writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu)); sun8i_smp_boot_secondary()
/linux-4.4.14/arch/arm/mach-highbank/
H A Dsysregs.h58 writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ); highbank_set_pwr_suspend()
64 writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ); highbank_set_pwr_shutdown()
70 writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ); highbank_set_pwr_soft_reset()
76 writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ); highbank_set_pwr_hard_reset()
82 writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ); highbank_clear_pwr_request()
/linux-4.4.14/drivers/usb/phy/
H A Dphy-tegra-usb.c215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); set_pts()
220 writel(val, base + TEGRA_USB_PORTSC1); set_pts()
235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); set_phcd()
242 writel(val, base + TEGRA_USB_PORTSC1); set_phcd()
280 writel(val, base + UTMIP_BIAS_CFG0); utmip_pad_power_on()
305 writel(val, base + UTMIP_BIAS_CFG0); utmip_pad_power_off()
335 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_disable()
341 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_disable()
357 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_enable()
363 writel(val, base + USB_SUSP_CTRL); utmi_phy_clk_enable()
380 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
385 writel(val, base + USB1_LEGACY_CTRL); utmi_phy_power_on()
390 writel(val, base + UTMIP_TX_CFG0); utmi_phy_power_on()
396 writel(val, base + UTMIP_HSRX_CFG0); utmi_phy_power_on()
401 writel(val, base + UTMIP_HSRX_CFG1); utmi_phy_power_on()
406 writel(val, base + UTMIP_DEBOUNCE_CFG0); utmi_phy_power_on()
410 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_power_on()
418 writel(val, base + UTMIP_MISC_CFG1); utmi_phy_power_on()
425 writel(val, base + UTMIP_PLL_CFG1); utmi_phy_power_on()
431 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
435 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
439 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_on()
462 writel(val, base + UTMIP_XCVR_CFG0); utmi_phy_power_on()
468 writel(val, base + UTMIP_XCVR_CFG1); utmi_phy_power_on()
473 writel(val, base + UTMIP_BIAS_CFG1); utmi_phy_power_on()
480 writel(val, base + UTMIP_SPARE_CFG0); utmi_phy_power_on()
485 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
490 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
496 writel(val, base + USB1_LEGACY_CTRL); utmi_phy_power_on()
500 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_on()
512 writel(val, base + USB_USBMODE); utmi_phy_power_on()
532 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_off()
537 writel(val, base + USB_SUSP_CTRL); utmi_phy_power_off()
541 writel(val, base + UTMIP_BAT_CHRG_CFG0); utmi_phy_power_off()
546 writel(val, base + UTMIP_XCVR_CFG0); utmi_phy_power_off()
551 writel(val, base + UTMIP_XCVR_CFG1); utmi_phy_power_off()
563 writel(val, base + UTMIP_TX_CFG0); utmi_phy_preresume()
573 writel(val, base + UTMIP_TX_CFG0); utmi_phy_postresume()
588 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
593 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_start()
604 writel(val, base + UTMIP_MISC_CFG0); utmi_phy_restore_end()
633 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
637 writel(val, base + ULPI_TIMING_CTRL_0); ulpi_phy_power_on()
641 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
644 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
649 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
655 writel(val, base + ULPI_TIMING_CTRL_1); ulpi_phy_power_on()
672 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
677 writel(val, base + USB_SUSP_CTRL); ulpi_phy_power_on()
H A Dphy-ulpi-viewport.c49 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view); ulpi_viewport_read()
54 writel(ULPI_VIEW_RUN | ULPI_VIEW_READ | ULPI_VIEW_ADDR(reg), view); ulpi_viewport_read()
67 writel(ULPI_VIEW_WAKEUP | ULPI_VIEW_WRITE, view); ulpi_viewport_write()
72 writel(ULPI_VIEW_RUN | ULPI_VIEW_WRITE | ULPI_VIEW_DATA_WRITE(val) | ulpi_viewport_write()
/linux-4.4.14/arch/m68k/coldfire/
H A Dintc-5249.c25 writel(imr, MCFSIM2_GPIOINTENABLE); intc2_irq_gpio_mask()
33 writel(imr, MCFSIM2_GPIOINTENABLE); intc2_irq_gpio_unmask()
38 writel(0x1 << (d->irq - MCF_IRQ_GPIO0), MCFSIM2_GPIOINTCLEAR); intc2_irq_gpio_ack()
H A Dm53xx.c311 writel(0x77777777, MCF_SCM_MPR); scm_init()
315 writel(0, MCF_SCM_PACRA); scm_init()
316 writel(0, MCF_SCM_PACRB); scm_init()
317 writel(0, MCF_SCM_PACRC); scm_init()
318 writel(0, MCF_SCM_PACRD); scm_init()
319 writel(0, MCF_SCM_PACRE); scm_init()
320 writel(0, MCF_SCM_PACRF); scm_init()
323 writel(MCF_SCM_BCR_GBR | MCF_SCM_BCR_GBW, MCF_SCM_BCR); scm_init()
332 writel(0x10080000, MCF_FBCS1_CSAR); fbcs_init()
334 writel(0x002A3780, MCF_FBCS1_CSCR); fbcs_init()
335 writel(MCF_FBCS_CSMR_BAM_2M | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR); fbcs_init()
341 writel(EXT_SRAM_ADDRESS, MCF_FBCS1_CSAR); fbcs_init()
342 writel(MCF_FBCS_CSCR_PS_16 | fbcs_init()
347 writel(MCF_FBCS_CSMR_BAM_512K | MCF_FBCS_CSMR_V, MCF_FBCS1_CSMR); fbcs_init()
350 writel(FLASH_ADDRESS, MCF_FBCS0_CSAR); fbcs_init()
351 writel(MCF_FBCS_CSCR_PS_16 | fbcs_init()
357 writel(MCF_FBCS_CSMR_BAM_32M | MCF_FBCS_CSMR_V, MCF_FBCS0_CSMR); fbcs_init()
370 writel(MCF_SDRAMC_SDCS_BA(SDRAM_ADDRESS) | sdramc_init()
377 writel(MCF_SDRAMC_SDCFG1_SRD2RW((int)((SDRAM_CASL + 2) + 0.5)) | sdramc_init()
385 writel(MCF_SDRAMC_SDCFG2_BRD2PRE(SDRAM_BL / 2 + 1) | sdramc_init()
395 writel(MCF_SDRAMC_SDCR_MODE_EN | sdramc_init()
407 writel(MCF_SDRAMC_SDMR_BNKAD_LEMR | sdramc_init()
415 writel(MCF_SDRAMC_SDMR_BNKAD_LMR | sdramc_init()
423 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IPALL, MCF_SDRAMC_SDCR); sdramc_init()
428 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); sdramc_init()
429 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_IREF, MCF_SDRAMC_SDCR); sdramc_init()
434 writel(MCF_SDRAMC_SDMR_BNKAD_LMR | sdramc_init()
442 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_MODE_EN, sdramc_init()
444 writel(MCF_SDRAMC_SDCR_REF | MCF_SDRAMC_SDCR_DQS_OE(0xC), sdramc_init()
501 writel(readl(MCF_SDRAMC_SDCR) & ~MCF_SDRAMC_SDCR_CKE, clock_pll()
526 writel(readl(MCF_SDRAMC_SDCR) | MCF_SDRAMC_SDCR_CKE, clock_pll()
530 writel(MCF_SDRAMC_REFRESH, MCF_SDRAMC_LIMP_FIX); clock_pll()
H A Dintc-525x.c31 writel(imr, MCFSIM2_GPIOINTENABLE); intc2_irq_gpio_mask()
44 writel(imr, MCFSIM2_GPIOINTENABLE); intc2_irq_gpio_unmask()
57 writel(imr, MCFSIM2_GPIOINTCLEAR); intc2_irq_gpio_ack()
80 writel(MCFINTC2_VECBASE, MCFINTC2_INTBASE); mcf_intc2_init()
H A Dintc-5272.c89 writel(v, intc_irqmap[irq].icr); intc_irq_mask()
101 writel(v, intc_irqmap[irq].icr); intc_irq_unmask()
117 writel(v, intc_irqmap[irq].icr); intc_irq_ack()
135 writel(v, MCFSIM_PITR); intc_irq_set_type()
166 writel(0x88888888, MCFSIM_ICR1); init_IRQ()
167 writel(0x88888888, MCFSIM_ICR2); init_IRQ()
168 writel(0x88888888, MCFSIM_ICR3); init_IRQ()
169 writel(0x88888888, MCFSIM_ICR4); init_IRQ()
/linux-4.4.14/drivers/memstick/host/
H A Dtifm_ms.c142 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), tifm_ms_write_data()
144 writel(host->io_word, sock->addr + SOCK_MS_DATA); tifm_ms_write_data()
157 writel(TIFM_MS_SYS_FDIR | readl(sock->addr + SOCK_MS_SYSTEM), tifm_ms_write_data()
238 writel(TIFM_MS_SYS_FDIR tifm_ms_transfer_data()
241 writel(host->io_word, sock->addr + SOCK_MS_DATA); tifm_ms_transfer_data()
243 writel(TIFM_MS_SYS_FDIR tifm_ms_transfer_data()
246 writel(0, sock->addr + SOCK_MS_DATA); tifm_ms_transfer_data()
279 writel(TIFM_FIFO_INT_SETALL, tifm_ms_issue_cmd()
281 writel(TIFM_FIFO_ENABLE, tifm_ms_issue_cmd()
294 writel(ilog2(data_len) - 2, tifm_ms_issue_cmd()
296 writel(TIFM_FIFO_INTMASK, tifm_ms_issue_cmd()
302 writel(TIFM_FIFO_INTMASK, tifm_ms_issue_cmd()
305 writel(sg_dma_address(&host->req->sg), tifm_ms_issue_cmd()
307 writel(sys_param, sock->addr + SOCK_DMA_CONTROL); tifm_ms_issue_cmd()
309 writel(host->mode_mask | TIFM_MS_SYS_FIFO, tifm_ms_issue_cmd()
312 writel(TIFM_FIFO_MORE, tifm_ms_issue_cmd()
317 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL), tifm_ms_issue_cmd()
329 writel(sys_param, sock->addr + SOCK_MS_SYSTEM); tifm_ms_issue_cmd()
333 writel(cmd, sock->addr + SOCK_MS_COMMAND); tifm_ms_issue_cmd()
351 writel(TIFM_FIFO_INT_SETALL, tifm_ms_complete_cmd()
353 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL); tifm_ms_complete_cmd()
362 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL), tifm_ms_complete_cmd()
413 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS); tifm_ms_data_event()
450 writel(TIFM_MS_SYS_INTCLR | readl(sock->addr + SOCK_MS_SYSTEM), tifm_ms_card_event()
511 writel(TIFM_MS_SYS_RESET, sock->addr + SOCK_MS_SYSTEM); tifm_ms_set_param()
512 writel(TIFM_MS_SYS_FCLR | TIFM_MS_SYS_INTCLR, tifm_ms_set_param()
514 writel(0xffffffff, sock->addr + SOCK_MS_STATUS); tifm_ms_set_param()
516 writel(TIFM_MS_SYS_FCLR | TIFM_MS_SYS_INTCLR, tifm_ms_set_param()
518 writel(0xffffffff, sock->addr + SOCK_MS_STATUS); tifm_ms_set_param()
525 writel((~TIFM_CTRL_FAST_CLK) tifm_ms_set_param()
530 writel(TIFM_CTRL_FAST_CLK tifm_ms_set_param()
609 writel(TIFM_FIFO_INT_SETALL, tifm_ms_remove()
611 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL); tifm_ms_remove()
H A Djmb38x_ms.c237 writel(host->io_word[0], host->addr + DATA); jmb38x_ms_write_data()
357 writel(host->io_word[0], host->addr + TPC_P0); jmb38x_ms_transfer_data()
358 writel(host->io_word[1], host->addr + TPC_P1); jmb38x_ms_transfer_data()
360 writel(host->io_word[0], host->addr + DATA); jmb38x_ms_transfer_data()
430 writel(sg_dma_address(&host->req->sg), jmb38x_ms_issue_cmd()
432 writel(((1 << 16) & BLOCK_COUNT_MASK) jmb38x_ms_issue_cmd()
435 writel(DMA_CONTROL_ENABLE, host->addr + DMA_CONTROL); jmb38x_ms_issue_cmd()
437 writel(((1 << 16) & BLOCK_COUNT_MASK) jmb38x_ms_issue_cmd()
445 writel(t_val, host->addr + INT_STATUS_ENABLE); jmb38x_ms_issue_cmd()
446 writel(t_val, host->addr + INT_SIGNAL_ENABLE); jmb38x_ms_issue_cmd()
454 writel(host->io_word[0], host->addr + TPC_P0); jmb38x_ms_issue_cmd()
455 writel(host->io_word[1], host->addr + TPC_P1); jmb38x_ms_issue_cmd()
460 writel(HOST_CONTROL_LED | readl(host->addr + HOST_CONTROL), jmb38x_ms_issue_cmd()
464 writel(cmd, host->addr + TPC); jmb38x_ms_issue_cmd()
486 writel(0, host->addr + BLOCK); jmb38x_ms_complete_cmd()
487 writel(0, host->addr + DMA_CONTROL); jmb38x_ms_complete_cmd()
500 writel(t_val, host->addr + INT_STATUS_ENABLE); jmb38x_ms_complete_cmd()
501 writel(t_val, host->addr + INT_SIGNAL_ENABLE); jmb38x_ms_complete_cmd()
504 writel((~HOST_CONTROL_LED) & readl(host->addr + HOST_CONTROL), jmb38x_ms_complete_cmd()
583 writel(irq_status, host->addr + INT_STATUS); jmb38x_ms_isr()
643 writel(HOST_CONTROL_RESET_REQ | HOST_CONTROL_CLOCK_EN jmb38x_ms_reset()
658 writel(HOST_CONTROL_RESET | HOST_CONTROL_CLOCK_EN jmb38x_ms_reset()
675 writel(INT_STATUS_ALL, host->addr + INT_SIGNAL_ENABLE); jmb38x_ms_reset()
676 writel(INT_STATUS_ALL, host->addr + INT_STATUS_ENABLE); jmb38x_ms_reset()
699 writel(host_ctl, host->addr + HOST_CONTROL); jmb38x_ms_set_param()
701 writel(host->id ? PAD_PU_PD_ON_MS_SOCK1 jmb38x_ms_set_param()
705 writel(PAD_OUTPUT_ENABLE_MS, jmb38x_ms_set_param()
713 writel(host_ctl, host->addr + HOST_CONTROL); jmb38x_ms_set_param()
714 writel(0, host->addr + PAD_OUTPUT_ENABLE); jmb38x_ms_set_param()
715 writel(PAD_PU_PD_OFF, host->addr + PAD_PU_PD); jmb38x_ms_set_param()
750 writel(host_ctl, host->addr + HOST_CONTROL); jmb38x_ms_set_param()
751 writel(CLOCK_CONTROL_OFF, host->addr + CLOCK_CONTROL); jmb38x_ms_set_param()
752 writel(clock_ctl, host->addr + CLOCK_CONTROL); jmb38x_ms_set_param()
1008 writel(0, host->addr + INT_SIGNAL_ENABLE); jmb38x_ms_remove()
1009 writel(0, host->addr + INT_STATUS_ENABLE); jmb38x_ms_remove()
/linux-4.4.14/sound/soc/fsl/
H A Dimx-ssi.c70 writel(sccr, ssi->base + SSI_STCCR); imx_ssi_set_dai_tdm_slot()
75 writel(sccr, ssi->base + SSI_SRCCR); imx_ssi_set_dai_tdm_slot()
77 writel(~tx_mask, ssi->base + SSI_STMSK); imx_ssi_set_dai_tdm_slot()
78 writel(~rx_mask, ssi->base + SSI_SRMSK); imx_ssi_set_dai_tdm_slot()
152 writel(strcr, ssi->base + SSI_STCR); imx_ssi_set_dai_fmt()
153 writel(strcr, ssi->base + SSI_SRCR); imx_ssi_set_dai_fmt()
154 writel(scr, ssi->base + SSI_SCR); imx_ssi_set_dai_fmt()
182 writel(scr, ssi->base + SSI_SCR); imx_ssi_set_dai_sysclk()
229 writel(stccr, ssi->base + SSI_STCCR); imx_ssi_set_dai_clkdiv()
230 writel(srccr, ssi->base + SSI_SRCCR); imx_ssi_set_dai_clkdiv()
270 writel(sccr, ssi->base + reg); imx_ssi_hw_params()
330 writel(scr, ssi->base + SSI_SCR); imx_ssi_trigger()
332 writel(sier, ssi->base + SSI_SIER); imx_ssi_trigger()
355 writel(val, ssi->base + SSI_SFCSR); imx_ssi_dai_probe()
409 writel(0x0, base + SSI_SCR); setup_channel_to_ac97()
410 writel(0x0, base + SSI_STCR); setup_channel_to_ac97()
411 writel(0x0, base + SSI_SRCR); setup_channel_to_ac97()
413 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR); setup_channel_to_ac97()
415 writel(SSI_SFCSR_RFWM0(8) | setup_channel_to_ac97()
420 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR); setup_channel_to_ac97()
421 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR); setup_channel_to_ac97()
423 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR); setup_channel_to_ac97()
424 writel(SSI_SOR_WAIT(3), base + SSI_SOR); setup_channel_to_ac97()
426 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN | setup_channel_to_ac97()
430 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT); setup_channel_to_ac97()
431 writel(0xff, base + SSI_SACCDIS); setup_channel_to_ac97()
432 writel(0x300, base + SSI_SACCEN); setup_channel_to_ac97()
451 writel(lreg, base + SSI_SACADD); imx_ssi_ac97_write()
454 writel(lval , base + SSI_SACDAT); imx_ssi_ac97_write()
456 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT); imx_ssi_ac97_write()
470 writel(lreg, base + SSI_SACADD); imx_ssi_ac97_read()
471 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT); imx_ssi_ac97_read()
561 writel(0x0, ssi->base + SSI_SIER); imx_ssi_probe()
/linux-4.4.14/sound/soc/samsung/
H A Ds3c24xx-i2s.c76 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_snd_txctrl()
77 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); s3c24xx_snd_txctrl()
78 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_snd_txctrl()
93 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_snd_txctrl()
94 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); s3c24xx_snd_txctrl()
95 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_snd_txctrl()
121 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_snd_rxctrl()
122 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); s3c24xx_snd_rxctrl()
123 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_snd_rxctrl()
138 writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); s3c24xx_snd_rxctrl()
139 writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_snd_rxctrl()
140 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_snd_rxctrl()
215 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_i2s_set_fmt()
248 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_i2s_hw_params()
315 writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_i2s_set_sysclk()
332 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_i2s_set_clkdiv()
336 writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_i2s_set_clkdiv()
339 writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR); s3c24xx_i2s_set_clkdiv()
341 writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_i2s_set_clkdiv()
378 writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_i2s_probe()
406 writel(s3c24xx_i2s.iiscon, s3c24xx_i2s.regs + S3C2410_IISCON); s3c24xx_i2s_resume()
407 writel(s3c24xx_i2s.iismod, s3c24xx_i2s.regs + S3C2410_IISMOD); s3c24xx_i2s_resume()
408 writel(s3c24xx_i2s.iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON); s3c24xx_i2s_resume()
409 writel(s3c24xx_i2s.iispsr, s3c24xx_i2s.regs + S3C2410_IISPSR); s3c24xx_i2s_resume()
H A Dac97.c65 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_activate()
69 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_activate()
74 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_activate()
94 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); s3c_ac97_read()
100 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_read()
131 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); s3c_ac97_write()
137 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_write()
144 writel(ac_codec_cmd, s3c_ac97.regs + S3C_AC97_CODEC_CMD); s3c_ac97_write()
152 writel(S3C_AC97_GLBCTRL_COLDRESET, s3c_ac97_cold_reset()
156 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_cold_reset()
170 writel(S3C_AC97_GLBCTRL_WARMRESET, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_warm_reset()
173 writel(0, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_warm_reset()
189 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_irq()
196 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_irq()
235 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_trigger()
261 writel(ac_glbctrl, s3c_ac97.regs + S3C_AC97_GLBCTRL); s3c_ac97_mic_trigger()
H A Ds3c-i2s-v2.c113 writel(con, regs + S3C2412_IISCON); s3c2412_snd_txctrl()
114 writel(mod, regs + S3C2412_IISMOD); s3c2412_snd_txctrl()
142 writel(mod, regs + S3C2412_IISMOD); s3c2412_snd_txctrl()
143 writel(con, regs + S3C2412_IISCON); s3c2412_snd_txctrl()
185 writel(mod, regs + S3C2412_IISMOD); s3c2412_snd_rxctrl()
186 writel(con, regs + S3C2412_IISCON); s3c2412_snd_rxctrl()
210 writel(con, regs + S3C2412_IISCON); s3c2412_snd_rxctrl()
211 writel(mod, regs + S3C2412_IISMOD); s3c2412_snd_rxctrl()
295 writel(iismod, i2s->regs + S3C2412_IISMOD); s3c2412_i2s_set_fmt()
334 writel(iismod, i2s->regs + S3C2412_IISMOD); s3c_i2sv2_hw_params()
379 writel(iismod, i2s->regs + S3C2412_IISMOD); s3c_i2sv2_set_sysclk()
400 writel(capture ? S3C2412_IISFIC_RXFLUSH : S3C2412_IISFIC_TXFLUSH, s3c2412_i2s_trigger()
404 writel(0x0, i2s->regs + S3C2412_IISFIC); s3c2412_i2s_trigger()
482 writel(reg | div, i2s->regs + S3C2412_IISMOD); s3c2412_i2s_set_clkdiv()
511 writel(reg | div, i2s->regs + S3C2412_IISMOD); s3c2412_i2s_set_clkdiv()
517 writel((div << 8) | S3C2412_IISPSR_PSREN, s3c2412_i2s_set_clkdiv()
520 writel(0x0, i2s->regs + S3C2412_IISPSR); s3c2412_i2s_set_clkdiv()
649 writel(iismod, i2s->regs + S3C2412_IISMOD); s3c_i2sv2_probe()
693 writel(i2s->suspend_iiscon, i2s->regs + S3C2412_IISCON); s3c2412_i2s_resume()
694 writel(i2s->suspend_iismod, i2s->regs + S3C2412_IISMOD); s3c2412_i2s_resume()
695 writel(i2s->suspend_iispsr, i2s->regs + S3C2412_IISPSR); s3c2412_i2s_resume()
697 writel(S3C2412_IISFIC_RXFLUSH | S3C2412_IISFIC_TXFLUSH, s3c2412_i2s_resume()
701 writel(0x0, i2s->regs + S3C2412_IISFIC); s3c2412_i2s_resume()
/linux-4.4.14/drivers/thermal/
H A Dhisi_thermal.c87 writel(0x0, data->regs + TEMP0_INT_EN); hisi_thermal_get_sensor_temp()
88 writel(0x1, data->regs + TEMP0_INT_CLR); hisi_thermal_get_sensor_temp()
91 writel(0x0, data->regs + TEMP0_EN); hisi_thermal_get_sensor_temp()
94 writel((sensor->id << 12), data->regs + TEMP0_CFG); hisi_thermal_get_sensor_temp()
97 writel(0x1, data->regs + TEMP0_EN); hisi_thermal_get_sensor_temp()
119 writel(0x0, data->regs + TEMP0_CFG); hisi_thermal_enable_bind_irq_sensor()
122 writel(0x0, data->regs + TEMP0_RST_MSK); hisi_thermal_enable_bind_irq_sensor()
123 writel(0x0, data->regs + TEMP0_EN); hisi_thermal_enable_bind_irq_sensor()
126 writel((sensor->id << 12), data->regs + TEMP0_CFG); hisi_thermal_enable_bind_irq_sensor()
129 writel(_temp_to_step(sensor->thres_temp) | 0x0FFFFFF00, hisi_thermal_enable_bind_irq_sensor()
132 writel(_temp_to_step(HISI_TEMP_RESET), data->regs + TEMP0_RST_TH); hisi_thermal_enable_bind_irq_sensor()
135 writel(0x1, data->regs + TEMP0_RST_MSK); hisi_thermal_enable_bind_irq_sensor()
136 writel(0x1, data->regs + TEMP0_EN); hisi_thermal_enable_bind_irq_sensor()
138 writel(0x0, data->regs + TEMP0_INT_CLR); hisi_thermal_enable_bind_irq_sensor()
139 writel(0x1, data->regs + TEMP0_INT_EN); hisi_thermal_enable_bind_irq_sensor()
151 writel(0x0, data->regs + TEMP0_INT_EN); hisi_thermal_disable_sensor()
152 writel(0x0, data->regs + TEMP0_RST_MSK); hisi_thermal_disable_sensor()
153 writel(0x0, data->regs + TEMP0_EN); hisi_thermal_disable_sensor()
H A Darmada_thermal.c80 writel(reg, priv->control); armadaxp_init_sensor()
85 writel(reg, priv->control); armadaxp_init_sensor()
89 writel((reg | PMU_TDC0_SW_RST_MASK), priv->control); armadaxp_init_sensor()
91 writel(reg, priv->control); armadaxp_init_sensor()
96 writel(reg, priv->sensor); armadaxp_init_sensor()
106 writel(reg, priv->control); armada370_init_sensor()
111 writel(reg, priv->control); armada370_init_sensor()
114 writel(reg, priv->control); armada370_init_sensor()
129 writel(reg, priv->control + 4); armada375_init_sensor()
133 writel(reg, priv->control + 4); armada375_init_sensor()
145 writel(reg, priv->control); armada380_init_sensor()
/linux-4.4.14/drivers/power/reset/
H A Dqnap-poweroff.c65 writel(0x83, UART1_REG(LCR)); qnap_power_off()
66 writel(divisor & 0xff, UART1_REG(DLL)); qnap_power_off()
67 writel((divisor >> 8) & 0xff, UART1_REG(DLM)); qnap_power_off()
68 writel(0x03, UART1_REG(LCR)); qnap_power_off()
69 writel(0x00, UART1_REG(IER)); qnap_power_off()
70 writel(0x00, UART1_REG(FCR)); qnap_power_off()
71 writel(0x00, UART1_REG(MCR)); qnap_power_off()
74 writel(cfg->cmd, UART1_REG(TX)); qnap_power_off()
/linux-4.4.14/drivers/ata/
H A Dahci_mvebu.c37 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); ahci_mvebu_mbus_config()
38 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); ahci_mvebu_mbus_config()
39 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); ahci_mvebu_mbus_config()
45 writel((cs->mbus_attr << 8) | ahci_mvebu_mbus_config()
48 writel(cs->base >> 16, hpriv->mmio + AHCI_WINDOW_BASE(i)); ahci_mvebu_mbus_config()
49 writel(((cs->size - 1) & 0xffff0000), ahci_mvebu_mbus_config()
61 writel(0x4, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_ADDR); ahci_mvebu_regret_option()
62 writel(0x80, hpriv->mmio + AHCI_VENDOR_SPECIFIC_0_DATA); ahci_mvebu_regret_option()
H A Dahci_ceva.c117 writel(tmp, mmio + AHCI_VEND_PAXIC); ahci_ceva_setup()
122 writel(tmp, mmio + HOST_CTL); ahci_ceva_setup()
127 writel(tmp, mmio + AHCI_VEND_PCFG); ahci_ceva_setup()
131 writel(tmp, mmio + AHCI_VEND_PPCFG); ahci_ceva_setup()
135 writel(tmp, mmio + AHCI_VEND_PP2C); ahci_ceva_setup()
139 writel(tmp, mmio + AHCI_VEND_PP3C); ahci_ceva_setup()
143 writel(tmp, mmio + AHCI_VEND_PP4C); ahci_ceva_setup()
147 writel(tmp, mmio + AHCI_VEND_PP5C); ahci_ceva_setup()
151 writel(tmp, mmio + AHCI_VEND_PTC); ahci_ceva_setup()
157 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); ahci_ceva_setup()
H A Dahci_tegra.c184 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); tegra_ahci_controller_init()
197 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); tegra_ahci_controller_init()
207 writel(val, tegra->sata_regs + SCFG_OFFSET + tegra_ahci_controller_init()
218 writel(val, tegra->sata_regs + SCFG_OFFSET + tegra_ahci_controller_init()
221 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, tegra_ahci_controller_init()
223 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, tegra_ahci_controller_init()
226 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); tegra_ahci_controller_init()
232 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); tegra_ahci_controller_init()
234 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); tegra_ahci_controller_init()
238 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); tegra_ahci_controller_init()
245 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); tegra_ahci_controller_init()
249 writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT, tegra_ahci_controller_init()
252 writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT, tegra_ahci_controller_init()
259 writel(val, tegra->sata_regs + SATA_INTR_MASK); tegra_ahci_controller_init()
H A Dahci_qoriq.c113 writel(px_cmd, port_mmio + PORT_CMD); ahci_qoriq_hardreset()
117 writel(px_is, port_mmio + PORT_IRQ_STAT); ahci_qoriq_hardreset()
152 writel(SATA_ECC_DISABLE, qpriv->ecc_addr); ahci_qoriq_phy_init()
153 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ahci_qoriq_phy_init()
154 writel(AHCI_PORT_PHY_2_CFG, reg_base + PORT_PHY2); ahci_qoriq_phy_init()
155 writel(AHCI_PORT_PHY_3_CFG, reg_base + PORT_PHY3); ahci_qoriq_phy_init()
156 writel(AHCI_PORT_PHY_4_CFG, reg_base + PORT_PHY4); ahci_qoriq_phy_init()
157 writel(AHCI_PORT_PHY_5_CFG, reg_base + PORT_PHY5); ahci_qoriq_phy_init()
158 writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); ahci_qoriq_phy_init()
163 writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ahci_qoriq_phy_init()
/linux-4.4.14/drivers/phy/
H A Dphy-mt65xx-usb3.c140 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_init()
144 writel(tmp, port_base + U3P_U2PHYDTM1); phy_instance_init()
149 writel(tmp, port_base + U3P_U2PHYACR4); phy_instance_init()
153 writel(tmp, port_base + U3P_USBPHYACR2); phy_instance_init()
157 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_init()
161 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_init()
165 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_init()
171 writel(tmp, port_base + U3P_USBPHYACR6); phy_instance_init()
176 writel(tmp, port_base + U3P_U3PHYA_DA_REG0); phy_instance_init()
181 writel(tmp, port_base + U3P_U3_PHYA_REG9); phy_instance_init()
186 writel(tmp, port_base + U3P_U3_PHYA_REG6); phy_instance_init()
191 writel(tmp, port_base + U3P_PHYD_CDR1); phy_instance_init()
207 writel(tmp, port_base + U3P_U3_PHYA_REG0); phy_instance_power_on()
214 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_on()
219 writel(tmp, port_base + U3P_USBPHYACR6); phy_instance_power_on()
224 writel(tmp, u3phy->sif_base + U3P_XTALCTL3); phy_instance_power_on()
229 writel(tmp, port_base + U3P_USBPHYACR5); phy_instance_power_on()
235 writel(tmp, port_base + U3P_U2PHYDTM1); phy_instance_power_on()
241 writel(tmp, port_base + U3P_USBPHYACR5); phy_instance_power_on()
246 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_power_on()
250 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_on()
265 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_off()
270 writel(tmp, port_base + U3P_USBPHYACR6); phy_instance_power_off()
276 writel(tmp, port_base + U3P_USBPHYACR5); phy_instance_power_off()
282 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_power_off()
288 writel(tmp, port_base + U3P_U2PHYDTM1); phy_instance_power_off()
293 writel(tmp, port_base + U3P_U3_PHYA_REG0); phy_instance_power_off()
297 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_power_off()
313 writel(tmp, port_base + U3D_U2PHYDCR0); phy_instance_exit()
317 writel(tmp, port_base + U3P_U2PHYDTM0); phy_instance_exit()
H A Dphy-exynos5250-usb2.c233 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); exynos5250_power_on()
239 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); exynos5250_power_on()
262 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); exynos5250_power_on()
266 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); exynos5250_power_on()
285 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); exynos5250_power_on()
295 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); exynos5250_power_on()
296 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); exynos5250_power_on()
299 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); exynos5250_power_on()
300 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); exynos5250_power_on()
311 writel(ehci, drv->reg_phy + EXYNOS_5250_HOSTEHCICTRL); exynos5250_power_on()
317 writel(ohci, drv->reg_phy + EXYNOS_5250_HOSTOHCICTRL); exynos5250_power_on()
341 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS); exynos5250_power_off()
350 writel(ctrl0, drv->reg_phy + EXYNOS_5250_HOSTPHYCTRL0); exynos5250_power_off()
360 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL1); exynos5250_power_off()
361 writel(hsic, drv->reg_phy + EXYNOS_5250_HSICPHYCTRL2); exynos5250_power_off()
H A Dphy-berlin-usb.c125 writel(priv->pll_divider, phy_berlin_usb_power_on()
127 writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL | phy_berlin_usb_power_on()
129 writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5), phy_berlin_usb_power_on()
131 writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 | phy_berlin_usb_power_on()
135 writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1); phy_berlin_usb_power_on()
136 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), phy_berlin_usb_power_on()
139 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) | phy_berlin_usb_power_on()
142 writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4), phy_berlin_usb_power_on()
144 writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 | phy_berlin_usb_power_on()
H A Dphy-s5pv210-usb2.c133 writel(drv->ref_reg_val, drv->reg_phy + S5PV210_UPHYCLK); s5pv210_phy_pwr()
137 writel(pwr, drv->reg_phy + S5PV210_UPHYPWR); s5pv210_phy_pwr()
141 writel(rst, drv->reg_phy + S5PV210_UPHYRST); s5pv210_phy_pwr()
144 writel(rst, drv->reg_phy + S5PV210_UPHYRST); s5pv210_phy_pwr()
148 writel(pwr, drv->reg_phy + S5PV210_UPHYPWR); s5pv210_phy_pwr()
H A Dphy-exynos5250-sata.c102 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); exynos_sata_phy_init()
108 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); exynos_sata_phy_init()
112 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); exynos_sata_phy_init()
116 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); exynos_sata_phy_init()
120 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); exynos_sata_phy_init()
125 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM); exynos_sata_phy_init()
129 writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0); exynos_sata_phy_init()
133 writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0); exynos_sata_phy_init()
142 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); exynos_sata_phy_init()
146 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET); exynos_sata_phy_init()
H A Dphy-exynos4210-usb2.c170 writel(on, drv->reg_phy + EXYNOS_4210_UPHY1CON); exynos4210_phy_pwr()
188 writel(clk, drv->reg_phy + EXYNOS_4210_UPHYCLK); exynos4210_phy_pwr()
192 writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR); exynos4210_phy_pwr()
196 writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST); exynos4210_phy_pwr()
199 writel(rst, drv->reg_phy + EXYNOS_4210_UPHYRST); exynos4210_phy_pwr()
206 writel(pwr, drv->reg_phy + EXYNOS_4210_UPHYPWR); exynos4210_phy_pwr()
/linux-4.4.14/drivers/net/ethernet/moxa/
H A Dmoxart_ether.c36 writel(value, priv->base + reg); moxart_emac_write()
88 writel(SW_RST, priv->base + REG_MAC_CTRL); moxart_mac_reset()
92 writel(0, priv->base + REG_INTERRUPT_MASK); moxart_mac_reset()
101 writel(0x00001010, priv->base + REG_INT_TIMER_CTRL); moxart_mac_enable()
102 writel(0x00000001, priv->base + REG_APOLL_TIMER_CTRL); moxart_mac_enable()
103 writel(0x00000390, priv->base + REG_DMA_BLEN_CTRL); moxart_mac_enable()
106 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); moxart_mac_enable()
109 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); moxart_mac_enable()
124 writel(TX_DESC1_END, desc + TX_REG_OFFSET_DESC1); moxart_mac_setup_desc_ring()
132 writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); moxart_mac_setup_desc_ring()
133 writel(RX_BUF_SIZE & RX_DESC1_BUF_SIZE_MASK, moxart_mac_setup_desc_ring()
144 writel(priv->rx_mapping[i], moxart_mac_setup_desc_ring()
146 writel(priv->rx_buf[i], moxart_mac_setup_desc_ring()
149 writel(RX_DESC1_END, desc + RX_REG_OFFSET_DESC1); moxart_mac_setup_desc_ring()
154 writel(priv->tx_base, priv->base + REG_TXR_BASE_ADDRESS); moxart_mac_setup_desc_ring()
155 writel(priv->rx_base, priv->base + REG_RXR_BASE_ADDRESS); moxart_mac_setup_desc_ring()
189 writel(0, priv->base + REG_INTERRUPT_MASK); moxart_mac_stop()
192 writel(0, priv->base + REG_MAC_CTRL); moxart_mac_stop()
253 writel(RX_DESC0_DMA_OWN, desc + RX_REG_OFFSET_DESC0); moxart_rx_poll()
264 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); moxart_rx_poll()
302 writel(priv->reg_imr, priv->base + REG_INTERRUPT_MASK); moxart_mac_interrupt()
340 writel(priv->tx_mapping[tx_head], moxart_mac_start_xmit()
342 writel(skb->data, moxart_mac_start_xmit()
357 writel(txdes1, desc + TX_REG_OFFSET_DESC1); moxart_mac_start_xmit()
358 writel(TX_DESC0_DMA_OWN, desc + TX_REG_OFFSET_DESC0); moxart_mac_start_xmit()
361 writel(0xffffffff, priv->base + REG_TX_POLL_DEMAND); moxart_mac_start_xmit()
390 writel(readl(priv->base + REG_MCAST_HASH_TABLE1) | netdev_for_each_mc_addr()
394 writel(readl(priv->base + REG_MCAST_HASH_TABLE0) | netdev_for_each_mc_addr()
420 writel(priv->reg_maccr, priv->base + REG_MAC_CTRL); moxart_mac_set_rx_mode()
/linux-4.4.14/drivers/net/ethernet/allwinner/
H A Dsun4i-emac.c99 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); emac_update_speed()
112 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); emac_update_duplex()
193 writel(0, db->membase + EMAC_CTL_REG); emac_reset()
195 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG); emac_reset()
269 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN, emac_setup()
275 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN | emac_setup()
284 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); emac_setup()
287 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG); emac_setup()
290 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2, emac_setup()
294 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM, emac_setup()
298 writel(EMAC_MAX_FRAME_LEN, emac_setup()
317 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN | emac_set_rx_mode()
333 writel(reg_val, db->membase + EMAC_RX_CTL_REG); emac_powerup()
340 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG); emac_powerup()
346 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG); emac_powerup()
349 writel(0x0, db->membase + EMAC_RX_FBC_REG); emac_powerup()
352 writel(0, db->membase + EMAC_INT_CTL_REG); emac_powerup()
354 writel(reg_val, db->membase + EMAC_INT_STA_REG); emac_powerup()
362 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev-> emac_powerup()
364 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev-> emac_powerup()
382 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev-> emac_set_mac_address()
384 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev-> emac_set_mac_address()
404 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN, emac_init_device()
410 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_init_device()
455 writel(channel, db->membase + EMAC_TX_INS_REG); emac_start_xmit()
465 writel(skb->len, db->membase + EMAC_TX_PL0_REG); emac_start_xmit()
467 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1, emac_start_xmit()
474 writel(skb->len, db->membase + EMAC_TX_PL1_REG); emac_start_xmit()
476 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1, emac_start_xmit()
551 writel(reg_val, db->membase + EMAC_RX_CTL_REG); emac_rx()
558 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_rx()
572 writel(reg_val & ~EMAC_CTL_RX_EN, emac_rx()
577 writel(reg_val | (1 << 3), emac_rx()
586 writel(reg_val | EMAC_CTL_RX_EN, emac_rx()
590 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_rx()
674 writel(0, db->membase + EMAC_INT_CTL_REG); emac_interrupt()
680 writel(int_status, db->membase + EMAC_INT_STA_REG); emac_interrupt()
703 writel(reg_val, db->membase + EMAC_INT_CTL_REG); emac_interrupt()
759 writel(0, db->membase + EMAC_INT_CTL_REG); emac_shutdown()
763 writel(reg_val, db->membase + EMAC_INT_STA_REG); emac_shutdown()
768 writel(reg_val, db->membase + EMAC_CTL_REG); emac_shutdown()
/linux-4.4.14/drivers/staging/sm750fb/
H A Dddk750_help.h13 #define POKE32(addr, data) writel(data, addr + mmio750)
/linux-4.4.14/drivers/scsi/qla4xxx/
H A Dql4_inline.h42 writel(set_rmask(IMR_SCSI_INTR_ENABLE), __qla4xxx_enable_intrs()
46 writel(set_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status); __qla4xxx_enable_intrs()
56 writel(clr_rmask(IMR_SCSI_INTR_ENABLE), __qla4xxx_disable_intrs()
60 writel(clr_rmask(CSR_SCSI_INTR_ENABLE), &ha->reg->ctrl_status); __qla4xxx_disable_intrs()
/linux-4.4.14/arch/mips/jz4740/
H A Dtimer.c28 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); jz4740_timer_enable_watchdog()
34 writel(BIT(16), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); jz4740_timer_disable_watchdog()
46 writel(0x000100fc, jz4740_timer_base + JZ_REG_TIMER_STOP_SET); jz4740_timer_init()
49 writel(0x00ff00ff, jz4740_timer_base + JZ_REG_TIMER_MASK_SET); jz4740_timer_init()
/linux-4.4.14/drivers/pci/host/
H A Dpci-xgene.c115 writel(rtdid_val, port->csr_base + RTDID); xgene_pcie_set_rtdid_reg()
191 writel(val, csr_base + addr); xgene_pcie_set_ib_mask()
195 writel(val, csr_base + addr + 0x04); xgene_pcie_set_ib_mask()
199 writel(val, csr_base + addr + 0x04); xgene_pcie_set_ib_mask()
203 writel(val, csr_base + addr + 0x08); xgene_pcie_set_ib_mask()
286 writel(lower_32_bits(cpu_addr), base); xgene_pcie_setup_ob_reg()
287 writel(upper_32_bits(cpu_addr), base + 0x04); xgene_pcie_setup_ob_reg()
288 writel(lower_32_bits(mask), base + 0x08); xgene_pcie_setup_ob_reg()
289 writel(upper_32_bits(mask), base + 0x0c); xgene_pcie_setup_ob_reg()
290 writel(lower_32_bits(pci_addr), base + 0x10); xgene_pcie_setup_ob_reg()
291 writel(upper_32_bits(pci_addr), base + 0x14); xgene_pcie_setup_ob_reg()
296 writel(lower_32_bits(addr), csr_base + CFGBARL); xgene_pcie_setup_cfg_reg()
297 writel(upper_32_bits(addr), csr_base + CFGBARH); xgene_pcie_setup_cfg_reg()
298 writel(EN_REG, csr_base + CFGCTL); xgene_pcie_setup_cfg_reg()
349 writel(lower_32_bits(pim), addr); xgene_pcie_setup_pims()
350 writel(upper_32_bits(pim) | EN_COHERENCY, addr + 0x04); xgene_pcie_setup_pims()
351 writel(lower_32_bits(size), addr + 0x10); xgene_pcie_setup_pims()
352 writel(upper_32_bits(size), addr + 0x14); xgene_pcie_setup_pims()
408 writel(bar_low, bar_addr); xgene_pcie_setup_ib_reg()
409 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); xgene_pcie_setup_ib_reg()
414 writel(bar_low, bar_addr); xgene_pcie_setup_ib_reg()
415 writel(lower_32_bits(mask), csr_base + IR2MSK); xgene_pcie_setup_ib_reg()
420 writel(bar_low, bar_addr); xgene_pcie_setup_ib_reg()
421 writel(upper_32_bits(cpu_addr), bar_addr + 0x4); xgene_pcie_setup_ib_reg()
422 writel(lower_32_bits(mask), csr_base + IR3MSKL); xgene_pcie_setup_ib_reg()
423 writel(upper_32_bits(mask), csr_base + IR3MSKL + 0x4); xgene_pcie_setup_ib_reg()
479 writel(0x0, port->csr_base + i); xgene_pcie_clear_config()
493 writel(val, port->csr_base + BRIDGE_CFG_0); xgene_pcie_setup()
H A Dpci-keystone-dw.c111 writel(BIT(bit_pos), ks_dw_pcie_msi_irq_ack()
113 writel(reg_offset + MSI_IRQ_OFFSET, ks_pcie->va_app_base + IRQ_EOI); ks_dw_pcie_msi_irq_ack()
122 writel(BIT(bit_pos), ks_dw_pcie_msi_set_irq()
132 writel(BIT(bit_pos), ks_dw_pcie_msi_clear_irq()
224 writel(0x1, ks_pcie->va_app_base + IRQ_ENABLE_SET + (i << 4)); ks_dw_pcie_enable_legacy_irqs()
243 writel(offset, ks_pcie->va_app_base + IRQ_EOI); ks_dw_pcie_handle_legacy_irq()
291 writel(DBI_CS2_EN_VAL | readl(reg_virt + CMD_STATUS), ks_dw_pcie_set_dbi_mode()
309 writel(~DBI_CS2_EN_VAL & readl(reg_virt + CMD_STATUS), ks_dw_pcie_clear_dbi_mode()
325 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); ks_dw_pcie_setup_rc_app_regs()
326 writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); ks_dw_pcie_setup_rc_app_regs()
330 writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE); ks_dw_pcie_setup_rc_app_regs()
336 writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i)); ks_dw_pcie_setup_rc_app_regs()
337 writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i)); ks_dw_pcie_setup_rc_app_regs()
342 writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS), ks_dw_pcie_setup_rc_app_regs()
383 writel(regval, ks_pcie->va_app_base + CFG_SETUP); ks_pcie_cfg_setup()
424 writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0); ks_dw_pcie_v3_65_scan_bus()
425 writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0); ks_dw_pcie_v3_65_scan_bus()
433 writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0); ks_dw_pcie_v3_65_scan_bus()
453 writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS); ks_dw_pcie_initiate_link_train()
457 writel(LTSSM_EN_VAL | val, ks_pcie->va_app_base + CMD_STATUS); ks_dw_pcie_initiate_link_train()
/linux-4.4.14/arch/sparc/kernel/
H A Debus.c54 writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR); __ebus_dma_reset()
77 writel(csr, p->regs + EBDMA_CSR); ebus_dma_irq()
117 writel(csr, p->regs + EBDMA_CSR); ebus_dma_register()
137 writel(csr, p->regs + EBDMA_CSR); ebus_dma_irq_enable()
143 writel(csr, p->regs + EBDMA_CSR); ebus_dma_irq_enable()
165 writel(csr, p->regs + EBDMA_CSR); ebus_dma_unregister()
193 writel(len, p->regs + EBDMA_COUNT); ebus_dma_request()
194 writel(bus_addr, p->regs + EBDMA_ADDR); ebus_dma_request()
222 writel(csr, p->regs + EBDMA_CSR); ebus_dma_prepare()
253 writel(csr, p->regs + EBDMA_CSR); ebus_dma_enable()
/linux-4.4.14/arch/arm/mach-berlin/
H A Dplatsmp.c41 writel(val, cpu_ctrl + CPU_RESET_NON_SC); berlin_perform_reset_cpu()
43 writel(val, cpu_ctrl + CPU_RESET_NON_SC); berlin_perform_reset_cpu()
89 writel(boot_inst, vectors_base + RESET_VECT); berlin_smp_prepare_cpus()
95 writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR); berlin_smp_prepare_cpus()
116 writel(val, cpu_ctrl + CPU_RESET_NON_SC); berlin_cpu_kill()
/linux-4.4.14/sound/soc/kirkwood/
H A Dkirkwood-i2s.c68 writel(value, priv->io+KIRKWOOD_I2S_PLAYCTL); kirkwood_i2s_set_fmt()
73 writel(value, priv->io+KIRKWOOD_I2S_RECCTL); kirkwood_i2s_set_fmt()
95 writel(value, io + KIRKWOOD_DCO_CTL); kirkwood_set_dco()
127 writel(clks_ctrl, priv->io + KIRKWOOD_CLOCKS_CTRL); kirkwood_set_rate()
220 writel(i2s_value, priv->io+i2s_reg); kirkwood_i2s_hw_params()
272 writel(value, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_play_trigger()
278 writel(value, priv->io + KIRKWOOD_INT_MASK); kirkwood_i2s_play_trigger()
282 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_play_trigger()
289 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_play_trigger()
293 writel(value, priv->io + KIRKWOOD_INT_MASK); kirkwood_i2s_play_trigger()
297 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_play_trigger()
304 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_play_trigger()
312 writel(ctl, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_play_trigger()
340 writel(value, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_rec_trigger()
345 writel(value, priv->io + KIRKWOOD_INT_MASK); kirkwood_i2s_rec_trigger()
348 writel(ctl, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_rec_trigger()
355 writel(value, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_rec_trigger()
359 writel(value, priv->io + KIRKWOOD_INT_MASK); kirkwood_i2s_rec_trigger()
364 writel(value, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_rec_trigger()
371 writel(value, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_rec_trigger()
378 writel(value, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_rec_trigger()
406 writel(0xffffffff, priv->io + KIRKWOOD_INT_CAUSE); kirkwood_i2s_init()
407 writel(0, priv->io + KIRKWOOD_INT_MASK); kirkwood_i2s_init()
412 writel(reg_data, priv->io + 0x1200); kirkwood_i2s_init()
419 writel(reg_data, priv->io + 0x1200); kirkwood_i2s_init()
424 writel(value, priv->io + KIRKWOOD_PLAYCTL); kirkwood_i2s_init()
428 writel(value, priv->io + KIRKWOOD_RECCTL); kirkwood_i2s_init()
H A Dkirkwood-dma.c57 writel(cause, priv->io + KIRKWOOD_ERR_CAUSE); kirkwood_dma_irq()
69 writel(status, priv->io + KIRKWOOD_INT_CAUSE); kirkwood_dma_irq()
88 writel(0, base + KIRKWOOD_AUDIO_WIN_CTRL_REG(win)); kirkwood_dma_conf_mbus_windows()
89 writel(0, base + KIRKWOOD_AUDIO_WIN_BASE_REG(win)); kirkwood_dma_conf_mbus_windows()
95 writel(cs->base & 0xffff0000, kirkwood_dma_conf_mbus_windows()
97 writel(((cs->size - 1) & 0xffff0000) | kirkwood_dma_conf_mbus_windows()
145 writel((unsigned int)-1, priv->io + KIRKWOOD_ERR_MASK); kirkwood_dma_open()
180 writel(0, priv->io + KIRKWOOD_ERR_MASK); kirkwood_dma_close()
216 writel(count, priv->io + KIRKWOOD_PLAY_BYTE_INT_COUNT); kirkwood_dma_prepare()
217 writel(runtime->dma_addr, priv->io + KIRKWOOD_PLAY_BUF_ADDR); kirkwood_dma_prepare()
218 writel(size, priv->io + KIRKWOOD_PLAY_BUF_SIZE); kirkwood_dma_prepare()
220 writel(count, priv->io + KIRKWOOD_REC_BYTE_INT_COUNT); kirkwood_dma_prepare()
221 writel(runtime->dma_addr, priv->io + KIRKWOOD_REC_BUF_ADDR); kirkwood_dma_prepare()
222 writel(size, priv->io + KIRKWOOD_REC_BUF_SIZE); kirkwood_dma_prepare()
/linux-4.4.14/arch/arm/mach-integrator/
H A Dintegrator_ap.c125 writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); irq_resume()
126 writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); irq_resume()
128 writel(ic_irq_enable, VA_IC_BASE + IRQ_ENABLE_SET); irq_resume()
156 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, ap_flash_init()
161 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); ap_flash_init()
165 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); ap_flash_init()
166 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); ap_flash_init()
167 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); ap_flash_init()
176 writel(INTEGRATOR_SC_CTRL_nFLVPPEN | INTEGRATOR_SC_CTRL_nFLWP, ap_flash_exit()
181 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); ap_flash_exit()
185 writel(0xa05f, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); ap_flash_exit()
186 writel(tmp, ebi_base + INTEGRATOR_EBI_CSR1_OFFSET); ap_flash_exit()
187 writel(0, ebi_base + INTEGRATOR_EBI_LOCK_OFFSET); ap_flash_exit()
194 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, ap_flash_set_vpp()
197 writel(INTEGRATOR_SC_CTRL_nFLVPPEN, ap_flash_set_vpp()
/linux-4.4.14/drivers/i2c/busses/
H A Di2c-lpc2k.c92 writel(LPC24XX_CLEAR_ALL, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_reset()
93 writel(0, i2c->base + LPC24XX_I2ADDR); i2c_lpc2k_reset()
94 writel(LPC24XX_I2EN, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_reset()
105 writel(LPC24XX_STO, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_clear_arb()
140 writel(data, i2c->base + LPC24XX_I2DAT); i2c_lpc2k_pump_msg()
141 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
151 writel(i2c->msg->buf[i2c->msg_idx], i2c_lpc2k_pump_msg()
155 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_pump_msg()
156 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
171 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
174 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_pump_msg()
177 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
195 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_pump_msg()
196 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
212 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
215 writel(LPC24XX_AA, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_pump_msg()
218 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
226 writel(LPC24XX_STO_AA, i2c->base + LPC24XX_I2CONSET); i2c_lpc2k_pump_msg()
236 writel(LPC24XX_STA | LPC24XX_STO, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
256 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); i2c_lpc2k_pump_msg()
263 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET); lpc2k_process_msg()
275 writel(i2c->msg->buf[0], lpc2k_process_msg()
281 writel(LPC24XX_STA, i2c->base + LPC24XX_I2CONSET); lpc2k_process_msg()
284 writel(LPC24XX_SI, i2c->base + LPC24XX_I2CONCLR); lpc2k_process_msg()
424 writel(scl_high, i2c->base + LPC24XX_I2SCLH); i2c_lpc2k_probe()
425 writel(clkrate - scl_high, i2c->base + LPC24XX_I2SCLL); i2c_lpc2k_probe()
H A Di2c-bcm-iproc.c115 writel(status, iproc_i2c->base + IS_OFFSET); bcm_iproc_i2c_isr()
173 writel(addr, iproc_i2c->base + M_TX_OFFSET); bcm_iproc_i2c_xfer_single_msg()
184 writel(val, iproc_i2c->base + M_TX_OFFSET); bcm_iproc_i2c_xfer_single_msg()
197 writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET); bcm_iproc_i2c_xfer_single_msg()
210 writel(val, iproc_i2c->base + M_CMD_OFFSET); bcm_iproc_i2c_xfer_single_msg()
215 writel(0, iproc_i2c->base + IE_OFFSET); bcm_iproc_i2c_xfer_single_msg()
228 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); bcm_iproc_i2c_xfer_single_msg()
237 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); bcm_iproc_i2c_xfer_single_msg()
317 writel(val, iproc_i2c->base + TIM_CFG_OFFSET); bcm_iproc_i2c_cfg_speed()
332 writel(val, iproc_i2c->base + CFG_OFFSET); bcm_iproc_i2c_init()
339 writel(val, iproc_i2c->base + CFG_OFFSET); bcm_iproc_i2c_init()
343 writel(val, iproc_i2c->base + M_FIFO_CTRL_OFFSET); bcm_iproc_i2c_init()
346 writel(0, iproc_i2c->base + IE_OFFSET); bcm_iproc_i2c_init()
349 writel(0xffffffff, iproc_i2c->base + IS_OFFSET); bcm_iproc_i2c_init()
364 writel(val, iproc_i2c->base + CFG_OFFSET); bcm_iproc_i2c_enable_disable()
434 writel(0, iproc_i2c->base + IE_OFFSET); bcm_iproc_i2c_remove()
452 writel(0, iproc_i2c->base + IE_OFFSET); bcm_iproc_i2c_suspend()
481 writel(val, iproc_i2c->base + TIM_CFG_OFFSET); bcm_iproc_i2c_resume()
H A Di2c-bcm-kona.c176 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | bcm_kona_i2c_send_cmd_to_ctrl()
182 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | bcm_kona_i2c_send_cmd_to_ctrl()
189 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | bcm_kona_i2c_send_cmd_to_ctrl()
196 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | bcm_kona_i2c_send_cmd_to_ctrl()
208 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, bcm_kona_i2c_enable_clock()
214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, bcm_kona_i2c_disable_clock()
228 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, bcm_kona_i2c_isr()
231 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); bcm_kona_i2c_isr()
264 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); bcm_kona_send_i2c_cmd()
276 writel(0, dev->base + IER_OFFSET); bcm_kona_send_i2c_cmd()
300 writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET); bcm_kona_i2c_read_fifo_single()
303 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | bcm_kona_i2c_read_fifo_single()
311 writel(0, dev->base + IER_OFFSET); bcm_kona_i2c_read_fifo_single()
368 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); bcm_kona_i2c_write_byte()
371 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); bcm_kona_i2c_write_byte()
377 writel(data, dev->base + DAT_OFFSET); bcm_kona_i2c_write_byte()
383 writel(0, dev->base + IER_OFFSET); bcm_kona_i2c_write_byte()
412 writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK, bcm_kona_i2c_write_fifo_single()
420 writel(buf[k], (dev->base + DAT_OFFSET)); bcm_kona_i2c_write_fifo_single()
432 writel(0, dev->base + IER_OFFSET); bcm_kona_i2c_write_fifo_single()
518 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, bcm_kona_i2c_enable_autosense()
524 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, bcm_kona_i2c_config_timing()
527 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | bcm_kona_i2c_config_timing()
533 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | bcm_kona_i2c_config_timing()
541 writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) | bcm_kona_i2c_config_timing_hs()
547 writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) | bcm_kona_i2c_config_timing_hs()
552 writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK, bcm_kona_i2c_config_timing_hs()
620 writel(0, dev->base + PADCTL_OFFSET); bcm_kona_i2c_xfer()
696 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); bcm_kona_i2c_xfer()
805 writel(0, dev->base + TOUT_OFFSET); bcm_kona_i2c_probe()
811 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, bcm_kona_i2c_probe()
815 writel(0, dev->base + IER_OFFSET); bcm_kona_i2c_probe()
818 writel(ISR_CMDBUSY_MASK | bcm_kona_i2c_probe()
846 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); bcm_kona_i2c_probe()
H A Di2c-sirf.c115 writel(regval, i2c_sirfsoc_queue_cmd()
128 writel(regval, i2c_sirfsoc_queue_cmd()
130 writel(siic->buf[siic->finished_len++], i2c_sirfsoc_queue_cmd()
137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); i2c_sirfsoc_queue_cmd()
148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); i2c_sirfsoc_irq()
160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, i2c_sirfsoc_irq()
175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); i2c_sirfsoc_irq()
191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); i2c_sirfsoc_set_address()
201 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); i2c_sirfsoc_set_address()
212 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, i2c_sirfsoc_xfer_msg()
221 writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN), i2c_sirfsoc_xfer_msg()
223 writel(0, siic->base + SIRFSOC_I2C_CMD_START); i2c_sirfsoc_xfer_msg()
227 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, i2c_sirfsoc_xfer_msg()
348 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); i2c_sirfsoc_probe()
351 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, i2c_sirfsoc_probe()
385 writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL); i2c_sirfsoc_probe()
387 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY); i2c_sirfsoc_probe()
389 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY); i2c_sirfsoc_probe()
418 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); i2c_sirfsoc_remove()
446 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); i2c_sirfsoc_resume()
449 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, i2c_sirfsoc_resume()
451 writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL); i2c_sirfsoc_resume()
452 writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY); i2c_sirfsoc_resume()
H A Di2c-axxia.c116 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); i2c_int_disable()
124 writel(int_en | mask, idev->base + MST_INT_ENABLE); i2c_int_enable()
149 writel(0x01, idev->base + SOFT_RESET); axxia_i2c_init()
159 writel(0x1, idev->base + GLOBAL_CONTROL); axxia_i2c_init()
174 writel(t_high, idev->base + SCL_HIGH_PERIOD); axxia_i2c_init()
176 writel(t_low, idev->base + SCL_LOW_PERIOD); axxia_i2c_init()
178 writel(t_setup, idev->base + SDA_SETUP_TIME); axxia_i2c_init()
180 writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME); axxia_i2c_init()
182 writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN); axxia_i2c_init()
197 writel(prescale, idev->base + TIMER_CLOCK_DIV); axxia_i2c_init()
199 writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL); axxia_i2c_init()
205 writel(0x01, idev->base + INTERRUPT_ENABLE); axxia_i2c_init()
249 writel(msg->len, idev->base + MST_RX_XFER); axxia_i2c_empty_rx_fifo()
269 writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA); axxia_i2c_fill_tx_fifo()
331 writel(INT_MST, idev->base + INTERRUPT_STATUS); axxia_i2c_isr()
375 writel(rx_xfer, idev->base + MST_RX_XFER); axxia_i2c_xfer_msg()
376 writel(tx_xfer, idev->base + MST_TX_XFER); axxia_i2c_xfer_msg()
377 writel(addr_1, idev->base + MST_ADDR_1); axxia_i2c_xfer_msg()
378 writel(addr_2, idev->base + MST_ADDR_2); axxia_i2c_xfer_msg()
386 writel(CMD_MANUAL, idev->base + MST_COMMAND); axxia_i2c_xfer_msg()
418 writel(0xb, idev->base + MST_COMMAND); axxia_i2c_stop()
463 writel(tmp, idev->base + I2C_BUS_MONITOR); axxia_i2c_set_scl()
H A Di2c-uniphier-f.c118 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); uniphier_fi2c_fill_txfifo()
140 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); uniphier_fi2c_set_irqs()
145 writel(-1, priv->membase + UNIPHIER_FI2C_IC); uniphier_fi2c_clear_irqs()
154 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STO, uniphier_fi2c_stop()
222 writel(UNIPHIER_FI2C_CR_MST | uniphier_fi2c_interrupt()
254 writel(0, priv->membase + UNIPHIER_FI2C_TBC); uniphier_fi2c_tx_init()
256 writel(UNIPHIER_FI2C_DTTX_CMD | addr << 1, uniphier_fi2c_tx_init()
271 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); uniphier_fi2c_rx_init()
280 writel(0, priv->membase + UNIPHIER_FI2C_RBC); uniphier_fi2c_rx_init()
286 writel(UNIPHIER_FI2C_DTTX_CMD | UNIPHIER_FI2C_DTTX_RD | addr << 1, uniphier_fi2c_rx_init()
292 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST); uniphier_fi2c_reset()
297 writel(UNIPHIER_FI2C_BRST_FOEN | UNIPHIER_FI2C_BRST_RSCL, uniphier_fi2c_prepare_operation()
328 writel(UNIPHIER_FI2C_RST_TBRST | UNIPHIER_FI2C_RST_RBRST, uniphier_fi2c_master_xfer_one()
339 writel(UNIPHIER_FI2C_CR_MST | UNIPHIER_FI2C_CR_STA, uniphier_fi2c_master_xfer_one()
433 writel(val ? UNIPHIER_FI2C_BRST_RSCL : 0, uniphier_fi2c_set_scl()
489 writel(clk_count, priv->membase + UNIPHIER_FI2C_CYC); uniphier_fi2c_clk_init()
490 writel(clk_count / 2, priv->membase + UNIPHIER_FI2C_LCTL); uniphier_fi2c_clk_init()
491 writel(clk_count / 2, priv->membase + UNIPHIER_FI2C_SSUT); uniphier_fi2c_clk_init()
492 writel(clk_count / 16, priv->membase + UNIPHIER_FI2C_DSUT); uniphier_fi2c_clk_init()
H A Di2c-mv64xxx.c207 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); mv64xxx_i2c_hw_init()
208 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING); mv64xxx_i2c_hw_init()
209 writel(0, drv_data->reg_base + mv64xxx_i2c_hw_init()
211 writel(0, drv_data->reg_base + mv64xxx_i2c_hw_init()
215 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset); mv64xxx_i2c_hw_init()
216 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n), mv64xxx_i2c_hw_init()
218 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr); mv64xxx_i2c_hw_init()
219 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr); mv64xxx_i2c_hw_init()
220 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP, mv64xxx_i2c_hw_init()
342 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START, mv64xxx_i2c_send_start()
370 writel(drv_data->cntl_bits, mv64xxx_i2c_do_action()
375 writel(drv_data->addr1, mv64xxx_i2c_do_action()
377 writel(drv_data->cntl_bits, mv64xxx_i2c_do_action()
382 writel(drv_data->addr2, mv64xxx_i2c_do_action()
384 writel(drv_data->cntl_bits, mv64xxx_i2c_do_action()
389 writel(drv_data->msg->buf[drv_data->byte_posn++], mv64xxx_i2c_do_action()
391 writel(drv_data->cntl_bits, mv64xxx_i2c_do_action()
398 writel(drv_data->cntl_bits, mv64xxx_i2c_do_action()
406 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, mv64xxx_i2c_do_action()
425 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP, mv64xxx_i2c_do_action()
487 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); mv64xxx_i2c_intr_offload()
488 writel(0, drv_data->reg_base + mv64xxx_i2c_intr_offload()
517 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG, mv64xxx_i2c_intr()
599 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO); mv64xxx_i2c_prepare_tx()
600 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI); mv64xxx_i2c_prepare_tx()
654 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL); mv64xxx_i2c_offload_xfer()
H A Di2c-qup.c142 writel(QUP_RESET_STATE, qup->base + QUP_STATE); qup_i2c_interrupt()
151 writel(qup_err, qup->base + QUP_ERROR_FLAGS); qup_i2c_interrupt()
157 writel(QUP_RESET_STATE, qup->base + QUP_STATE); qup_i2c_interrupt()
162 writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL); qup_i2c_interrupt()
165 writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL); qup_i2c_interrupt()
217 writel(state, qup->base + QUP_STATE); qup_i2c_change_state()
254 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); qup_i2c_set_write_mode()
255 writel(total, qup->base + QUP_MX_WRITE_CNT); qup_i2c_set_write_mode()
258 writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN, qup_i2c_set_write_mode()
260 writel(total, qup->base + QUP_MX_OUTPUT_CNT); qup_i2c_set_write_mode()
298 writel(val, qup->base + QUP_OUT_FIFO_BASE); qup_i2c_issue_write()
321 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); qup_i2c_write_one()
336 writel(1, qup->base + QUP_SW_RESET); qup_i2c_write_one()
363 writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE); qup_i2c_set_read_mode()
364 writel(len, qup->base + QUP_MX_READ_CNT); qup_i2c_set_read_mode()
367 writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN, qup_i2c_set_read_mode()
369 writel(len, qup->base + QUP_MX_INPUT_CNT); qup_i2c_set_read_mode()
383 writel(val, qup->base + QUP_OUT_FIFO_BASE); qup_i2c_issue_read()
426 writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL); qup_i2c_read_one()
441 writel(1, qup->base + QUP_SW_RESET); qup_i2c_read_one()
474 writel(1, qup->base + QUP_SW_RESET); qup_i2c_xfer()
480 writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG); qup_i2c_xfer()
549 writel(config, qup->base + QUP_CONFIG); qup_i2c_disable_clocks()
611 writel(1, qup->base + QUP_SW_RESET); qup_i2c_probe()
/linux-4.4.14/drivers/misc/
H A Dtifm_7xx1.c54 writel(TIFM_IRQ_ENABLE, fm->addr + FM_CLEAR_INTERRUPT_ENABLE); tifm_7xx1_isr()
69 writel(irq_status, fm->addr + FM_INTERRUPT_STATUS); tifm_7xx1_isr()
74 writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE); tifm_7xx1_isr()
87 writel(0x0e00, sock_addr + SOCK_CONTROL); tifm_7xx1_toggle_sock_power()
101 writel(readl(sock_addr + SOCK_CONTROL) | TIFM_CTRL_LED, tifm_7xx1_toggle_sock_power()
109 writel((s_state & TIFM_CTRL_POWER_MASK) | 0x0c00, tifm_7xx1_toggle_sock_power()
121 writel(readl(sock_addr + SOCK_CONTROL) & (~TIFM_CTRL_LED), tifm_7xx1_toggle_sock_power()
129 writel((~TIFM_CTRL_POWER_MASK) & readl(sock_addr + SOCK_CONTROL), tifm_7xx1_sock_power_off()
175 writel(0x0e00, sock_addr + SOCK_CONTROL); tifm_7xx1_switch_media()
202 writel(TIFM_IRQ_FIFOMASK(socket_change_set) tifm_7xx1_switch_media()
206 writel(TIFM_IRQ_FIFOMASK(socket_change_set) tifm_7xx1_switch_media()
210 writel(TIFM_IRQ_ENABLE, fm->addr + FM_SET_INTERRUPT_ENABLE); tifm_7xx1_switch_media()
267 writel(TIFM_IRQ_ENABLE | TIFM_IRQ_SOCKMASK((1 << fm->num_sockets) - 1), tifm_7xx1_resume()
278 writel(TIFM_IRQ_FIFOMASK(good_sockets) tifm_7xx1_resume()
281 writel(TIFM_IRQ_FIFOMASK(good_sockets) tifm_7xx1_resume()
294 writel(TIFM_IRQ_ENABLE, tifm_7xx1_resume()
373 writel(TIFM_IRQ_ENABLE | TIFM_IRQ_SOCKMASK((1 << fm->num_sockets) - 1), tifm_7xx1_probe()
375 writel(TIFM_IRQ_ENABLE | TIFM_IRQ_SOCKMASK((1 << fm->num_sockets) - 1), tifm_7xx1_probe()
401 writel(TIFM_IRQ_SETALL, fm->addr + FM_CLEAR_INTERRUPT_ENABLE); tifm_7xx1_remove()
H A Dspear13xx_pcie_gadget.c72 writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID), enable_dbi_access()
74 writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID), enable_dbi_access()
82 writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), disable_dbi_access()
84 writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID), disable_dbi_access()
123 writel(val, va_address); spear_dbi_write_reg()
247 writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID), pcie_gadget_link_store()
250 writel(readl(&app_reg->app_ctrl_0) pcie_gadget_link_store()
345 writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID), pcie_gadget_inta_store()
348 writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID), pcie_gadget_inta_store()
383 writel(ven_msi, &app_reg->ven_msi_1); pcie_gadget_send_msi_store()
386 writel(ven_msi, &app_reg->ven_msi_1); pcie_gadget_send_msi_store()
513 writel(address, &app_reg->pim0_mem_addr_start); pcie_gadget_bar0_address_store()
569 writel(data, (ulong)config->va_bar0_address + config->bar0_rw_offset); pcie_gadget_bar0_data_store()
612 writel(config->base, &app_reg->in0_mem_addr_start); spear13xx_pcie_device_init()
613 writel(app_reg->in0_mem_addr_start + IN0_MEM_SIZE, spear13xx_pcie_device_init()
615 writel(app_reg->in0_mem_addr_limit + 1, &app_reg->in1_mem_addr_start); spear13xx_pcie_device_init()
616 writel(app_reg->in1_mem_addr_start + IN1_MEM_SIZE, spear13xx_pcie_device_init()
618 writel(app_reg->in1_mem_addr_limit + 1, &app_reg->in_io_addr_start); spear13xx_pcie_device_init()
619 writel(app_reg->in_io_addr_start + IN_IO_SIZE, spear13xx_pcie_device_init()
621 writel(app_reg->in_io_addr_limit + 1, &app_reg->in_cfg0_addr_start); spear13xx_pcie_device_init()
622 writel(app_reg->in_cfg0_addr_start + IN_CFG0_SIZE, spear13xx_pcie_device_init()
624 writel(app_reg->in_cfg0_addr_limit + 1, &app_reg->in_cfg1_addr_start); spear13xx_pcie_device_init()
625 writel(app_reg->in_cfg1_addr_start + IN_CFG1_SIZE, spear13xx_pcie_device_init()
627 writel(app_reg->in_cfg1_addr_limit + 1, &app_reg->in_msg_addr_start); spear13xx_pcie_device_init()
628 writel(app_reg->in_msg_addr_start + IN_MSG_SIZE, spear13xx_pcie_device_init()
631 writel(app_reg->in0_mem_addr_start, &app_reg->pom0_mem_addr_start); spear13xx_pcie_device_init()
632 writel(app_reg->in1_mem_addr_start, &app_reg->pom1_mem_addr_start); spear13xx_pcie_device_init()
633 writel(app_reg->in_io_addr_start, &app_reg->pom_io_addr_start); spear13xx_pcie_device_init()
644 writel(SPEAR13XX_SYSRAM1_BASE, &app_reg->pim0_mem_addr_start); spear13xx_pcie_device_init()
645 writel(0, &app_reg->pim1_mem_addr_start); spear13xx_pcie_device_init()
646 writel(INBOUND_ADDR_MASK + 1, &app_reg->mem0_addr_offset_limit); spear13xx_pcie_device_init()
648 writel(0x0, &app_reg->pim_io_addr_start); spear13xx_pcie_device_init()
649 writel(0x0, &app_reg->pim_io_addr_start); spear13xx_pcie_device_init()
650 writel(0x0, &app_reg->pim_rom_addr_start); spear13xx_pcie_device_init()
652 writel(DEVICE_TYPE_EP | (1 << MISCTRL_EN_ID) spear13xx_pcie_device_init()
656 writel(0, &app_reg->int_mask); spear13xx_pcie_device_init()
H A Darm-charlcd.c82 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); charlcd_interrupt()
98 writel(0x00, lcd->virtbase + CHAR_MASK); charlcd_wait_complete_irq()
132 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); charlcd_4bit_read_char()
150 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); charlcd_4bit_read_char()
166 writel(CHAR_RAW_CLEAR, lcd->virtbase + CHAR_RAW); charlcd_4bit_read_bf()
168 writel(0x01, lcd->virtbase + CHAR_MASK); charlcd_4bit_read_bf()
190 writel(cmdhi, lcd->virtbase + CHAR_COM); charlcd_4bit_command()
192 writel(cmdlo, lcd->virtbase + CHAR_COM); charlcd_4bit_command()
201 writel(chhi, lcd->virtbase + CHAR_DAT); charlcd_4bit_char()
203 writel(chlo, lcd->virtbase + CHAR_DAT); charlcd_4bit_char()
235 writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM); charlcd_4bit_init()
237 writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM); charlcd_4bit_init()
239 writel(HD_FUNCSET | HD_FUNCSET_8BIT, lcd->virtbase + CHAR_COM); charlcd_4bit_init()
242 writel(HD_FUNCSET, lcd->virtbase + CHAR_COM); charlcd_4bit_init()
/linux-4.4.14/drivers/net/ethernet/amd/
H A Damd8111e.c123 writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) | amd8111e_read_phy()
152 writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) | amd8111e_write_phy()
392 writel(VAL0|STINTEN, mmio+INTEN0); amd8111e_set_coalesce()
393 writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout, amd8111e_set_coalesce()
406 writel(VAL0|STINTEN,mmio+INTEN0); amd8111e_set_coalesce()
407 writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout, amd8111e_set_coalesce()
412 writel(0,mmio+STVAL); amd8111e_set_coalesce()
413 writel(STINTEN, mmio+INTEN0); amd8111e_set_coalesce()
414 writel(0, mmio +DLY_INT_B); amd8111e_set_coalesce()
415 writel(0, mmio+DLY_INT_A); amd8111e_set_coalesce()
419 writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /* 0.5 sec */ amd8111e_set_coalesce()
420 writel(VAL0|STINTEN, mmio+INTEN0); amd8111e_set_coalesce()
438 writel(RUN, mmio + CMD0); amd8111e_restart()
444 writel((u32) VAL1|EN_PMGR, mmio + CMD3 ); amd8111e_restart()
445 writel((u32)XPHYANE|XPHYRST , mmio + CTRL2); amd8111e_restart()
452 writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 ); amd8111e_restart()
455 writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN | amd8111e_restart()
459 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); amd8111e_restart()
462 writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0); amd8111e_restart()
463 writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0); amd8111e_restart()
473 writel((u32)VAL2|JUMBO, mmio + CMD3); amd8111e_restart()
475 writel( REX_UFLO, mmio + CMD2); amd8111e_restart()
477 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2); amd8111e_restart()
479 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2); amd8111e_restart()
480 writel((u32)JUMBO, mmio + CMD3); amd8111e_restart()
484 writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3); amd8111e_restart()
486 writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 ); amd8111e_restart()
499 writel(VAL2 | RDMD0, mmio + CMD0); amd8111e_restart()
500 writel(VAL0 | INTREN | RUN, mmio + CMD0); amd8111e_restart()
516 writel(RUN, mmio + CMD0); amd8111e_init_hw_default()
522 writel(0, mmio + RCV_RING_BASE_ADDR0); amd8111e_init_hw_default()
525 writel(0, mmio + XMT_RING_BASE_ADDR0); amd8111e_init_hw_default()
526 writel(0, mmio + XMT_RING_BASE_ADDR1); amd8111e_init_hw_default()
527 writel(0, mmio + XMT_RING_BASE_ADDR2); amd8111e_init_hw_default()
528 writel(0, mmio + XMT_RING_BASE_ADDR3); amd8111e_init_hw_default()
531 writel(CMD0_CLEAR,mmio + CMD0); amd8111e_init_hw_default()
534 writel(CMD2_CLEAR, mmio +CMD2); amd8111e_init_hw_default()
537 writel(CMD7_CLEAR , mmio + CMD7); amd8111e_init_hw_default()
540 writel(0x0, mmio + DLY_INT_A); amd8111e_init_hw_default()
541 writel(0x0, mmio + DLY_INT_B); amd8111e_init_hw_default()
544 writel(0x0, mmio + FLOW_CONTROL); amd8111e_init_hw_default()
548 writel(reg_val, mmio + INT0); amd8111e_init_hw_default()
551 writel(0x0, mmio + STVAL); amd8111e_init_hw_default()
554 writel( INTEN0_CLEAR, mmio + INTEN0); amd8111e_init_hw_default()
557 writel(0x0 , mmio + LADRF); amd8111e_init_hw_default()
560 writel( 0x80010,mmio + SRAM_SIZE); amd8111e_init_hw_default()
563 writel(0x0, mmio + RCV_RING_LEN0); amd8111e_init_hw_default()
566 writel(0x0, mmio + XMT_RING_LEN0); amd8111e_init_hw_default()
567 writel(0x0, mmio + XMT_RING_LEN1); amd8111e_init_hw_default()
568 writel(0x0, mmio + XMT_RING_LEN2); amd8111e_init_hw_default()
569 writel(0x0, mmio + XMT_RING_LEN3); amd8111e_init_hw_default()
572 writel(0x0, mmio + XMT_RING_LIMIT); amd8111e_init_hw_default()
584 writel( VAL2|JUMBO, mmio + CMD3); amd8111e_init_hw_default()
586 writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 ); amd8111e_init_hw_default()
589 writel(CTRL1_DEFAULT, mmio + CTRL1); amd8111e_init_hw_default()
604 writel(INTREN, lp->mmio + CMD0); amd8111e_disable_interrupt()
608 writel(intr0, lp->mmio + INT0); amd8111e_disable_interrupt()
618 writel(RUN, lp->mmio + CMD0); amd8111e_stop_chip()
803 writel(intr0 & RINT0,mmio + INT0); amd8111e_rx_poll()
811 writel(VAL0|RINTEN0, mmio + INTEN0); amd8111e_rx_poll()
812 writel(VAL2 | RDMD0, mmio + CMD0); amd8111e_rx_poll()
1132 writel(INTREN, mmio + CMD0); amd8111e_interrupt()
1146 writel(intr0, mmio + INT0); amd8111e_interrupt()
1152 writel(RINTEN0, mmio + INTEN0); amd8111e_interrupt()
1158 writel(RINTEN0, mmio + INTEN0); amd8111e_interrupt()
1175 writel( VAL0 | INTREN,mmio + CMD0); amd8111e_interrupt()
1323 writel( VAL1 | TDMD0, lp->mmio + CMD0); amd8111e_start_xmit()
1324 writel( VAL2 | RDMD0,lp->mmio + CMD0); amd8111e_start_xmit()
1364 writel( VAL2 | PROM, lp->mmio + CMD2); amd8111e_set_multicast_list()
1368 writel( PROM, lp->mmio + CMD2); amd8111e_set_multicast_list()
1383 writel(PROM, lp->mmio + CMD2); amd8111e_set_multicast_list()
1573 writel(RUN, lp->mmio + CMD0); amd8111e_change_mtu()
1586 writel( VAL1|MPPLBA, lp->mmio + CMD3); amd8111e_enable_magicpkt()
1587 writel( VAL0|MPEN_SW, lp->mmio + CMD7); amd8111e_enable_magicpkt()
1598 writel(VAL0|LCMODE_SW,lp->mmio + CMD7); amd8111e_enable_link_change()
/linux-4.4.14/arch/arm/mach-mvebu/
H A Dpm.c54 writel(reg, sdram_ctrl + SDRAM_DLB_EVICTION_OFFS); mvebu_pm_powerdown()
61 writel(reg, sdram_ctrl + SDRAM_CONFIG_OFFS); mvebu_pm_powerdown()
123 writel(BOOT_MAGIC_WORD, store_addr++); mvebu_pm_store_armadaxp_bootinfo()
124 writel(resume_pc, store_addr++); mvebu_pm_store_armadaxp_bootinfo()
132 writel(MBUS_WINDOW_12_CTRL, store_addr++); mvebu_pm_store_armadaxp_bootinfo()
133 writel(0x0, store_addr++); mvebu_pm_store_armadaxp_bootinfo()
139 writel(MBUS_INTERNAL_REG_ADDRESS, store_addr++); mvebu_pm_store_armadaxp_bootinfo()
140 writel(mvebu_internal_reg_base(), store_addr++); mvebu_pm_store_armadaxp_bootinfo()
149 writel(BOOT_MAGIC_LIST_END, store_addr); mvebu_pm_store_armadaxp_bootinfo()
/linux-4.4.14/drivers/net/ethernet/
H A Dkorina.c144 writel(0, &ch->dmandptr); korina_start_dma()
145 writel(dma_addr, &ch->dmadptr); korina_start_dma()
152 writel(0x10, &ch->dmac); korina_abort_dma()
157 writel(0, &ch->dmas); korina_abort_dma()
160 writel(0, &ch->dmadptr); korina_abort_dma()
161 writel(0, &ch->dmandptr); korina_abort_dma()
166 writel(dma_addr, &ch->dmandptr); korina_chain_dma()
244 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), korina_send_packet()
260 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), korina_send_packet()
299 writel(0, &lp->eth_regs->miimcfg); mdio_read()
300 writel(0, &lp->eth_regs->miimcmd); mdio_read()
301 writel(mii_id | reg, &lp->eth_regs->miimaddr); mdio_read()
302 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); mdio_read()
314 writel(0, &lp->eth_regs->miimcfg); mdio_write()
315 writel(1, &lp->eth_regs->miimcmd); mdio_write()
316 writel(mii_id | reg, &lp->eth_regs->miimaddr); mdio_write()
317 writel(ETH_MII_CMD_SCN, &lp->eth_regs->miimcmd); mdio_write()
318 writel(val, &lp->eth_regs->miimwtd); mdio_write()
332 writel(dmasm | (DMA_STAT_DONE | korina_rx_dma_interrupt()
438 writel(~DMA_STAT_DONE, &lp->rx_dma_regs->dmas); korina_rx()
444 writel(~(DMA_STAT_HALT | DMA_STAT_ERR), korina_rx()
469 writel(readl(&lp->rx_dma_regs->dmasm) & korina_poll()
508 writel((u32)(hash_table[1] << 16 | hash_table[0]),
510 writel((u32)(hash_table[3] << 16 | hash_table[2]),
515 writel(recognise, &lp->eth_regs->etharc);
593 writel(~dmas, &lp->tx_dma_regs->dmas); korina_tx()
595 writel(readl(&lp->tx_dma_regs->dmasm) & korina_tx()
614 writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR), korina_tx_dma_interrupt()
621 writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), korina_tx_dma_interrupt()
645 writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD, korina_check_media()
648 writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD, korina_check_media()
812 writel(0, &lp->eth_regs->ethintfc); korina_init()
817 writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc); korina_init()
826 writel(0, &lp->rx_dma_regs->dmas); korina_init()
830 writel(readl(&lp->tx_dma_regs->dmasm) & korina_init()
833 writel(readl(&lp->rx_dma_regs->dmasm) & korina_init()
838 writel(ETH_ARC_AB, &lp->eth_regs->etharc); korina_init()
841 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0); korina_init()
842 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0); korina_init()
844 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1); korina_init()
845 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1); korina_init()
847 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2); korina_init()
848 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2); korina_init()
850 writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3); korina_init()
851 writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3); korina_init()
855 writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD, korina_init()
859 writel(0x15, &lp->eth_regs->ethipgt); korina_init()
861 writel(0x12, &lp->eth_regs->ethipgr); korina_init()
865 writel(((idt_cpu_freq) / MII_CLOCK + 1) & ~1, korina_init()
869 writel(48, &lp->eth_regs->ethfifott); korina_init()
871 writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1); korina_init()
896 writel(readl(&lp->tx_dma_regs->dmasm) | korina_restart_task()
899 writel(readl(&lp->rx_dma_regs->dmasm) | korina_restart_task()
924 writel(value, &lp->eth_regs->ethintfc); korina_clear_and_restart()
1060 writel(tmp, &lp->tx_dma_regs->dmasm); korina_close()
1065 writel(tmp, &lp->rx_dma_regs->dmasm); korina_close()
/linux-4.4.14/drivers/clk/mediatek/
H A Dclk-pll.c105 writel(val, pll->pd_addr); mtk_pll_set_rate_regs()
113 writel(val, pll->pcw_addr); mtk_pll_set_rate_regs()
120 writel(con1, pll->base_addr + REG_CON1); mtk_pll_set_rate_regs()
122 writel(con1 + 1, pll->tuner_addr); mtk_pll_set_rate_regs()
219 writel(r, pll->pwr_addr); mtk_pll_prepare()
223 writel(r, pll->pwr_addr); mtk_pll_prepare()
228 writel(r, pll->base_addr + REG_CON0); mtk_pll_prepare()
232 writel(r, pll->tuner_addr); mtk_pll_prepare()
240 writel(r, pll->base_addr + REG_CON0); mtk_pll_prepare()
254 writel(r, pll->base_addr + REG_CON0); mtk_pll_unprepare()
259 writel(r, pll->tuner_addr); mtk_pll_unprepare()
264 writel(r, pll->base_addr + REG_CON0); mtk_pll_unprepare()
267 writel(r, pll->pwr_addr); mtk_pll_unprepare()
270 writel(r, pll->pwr_addr); mtk_pll_unprepare()
H A Dclk-apmixed.c52 writel(val, tx->base_addr); mtk_ref2usb_tx_prepare()
56 writel(val, tx->base_addr); mtk_ref2usb_tx_prepare()
59 writel(val, tx->base_addr); mtk_ref2usb_tx_prepare()
71 writel(val, tx->base_addr); mtk_ref2usb_tx_unprepare()
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dsungem.c128 writel(cmd, gp->regs + MIF_FRAME); __sungem_phy_read()
166 writel(cmd, gp->regs + MIF_FRAME); __sungem_phy_write()
191 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK); gem_enable_ints()
197 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK); gem_disable_ints()
368 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); gem_rxmac_reset()
379 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB, gem_rxmac_reset()
392 writel(0, gp->regs + RXDMA_CFG); gem_rxmac_reset()
406 writel(gp->swrst_base | GREG_SWRST_RXRST, gem_rxmac_reset()
434 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); gem_rxmac_reset()
435 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); gem_rxmac_reset()
436 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); gem_rxmac_reset()
439 writel(val, gp->regs + RXDMA_CFG); gem_rxmac_reset()
441 writel(((5 & RXDMA_BLANK_IPKTS) | gem_rxmac_reset()
445 writel(((5 & RXDMA_BLANK_IPKTS) | gem_rxmac_reset()
450 writel(val, gp->regs + RXDMA_PTHRESH); gem_rxmac_reset()
452 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); gem_rxmac_reset()
453 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); gem_rxmac_reset()
455 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); gem_rxmac_reset()
740 writel(kick, gp->regs + RXDMA_KICK); gem_post_rxds()
1111 writel(gp->tx_new, gp->regs + TXDMA_KICK); gem_start_xmit()
1124 writel(val, gp->regs + PCS_MIICTRL); gem_pcs_reset()
1145 writel(val, gp->regs + PCS_CFG); gem_pcs_reinit_adv()
1153 writel(val, gp->regs + PCS_MIIADV); gem_pcs_reinit_adv()
1161 writel(val, gp->regs + PCS_MIICTRL); gem_pcs_reinit_adv()
1165 writel(val, gp->regs + PCS_CFG); gem_pcs_reinit_adv()
1176 writel(val, gp->regs + PCS_SCTRL); gem_pcs_reinit_adv()
1187 writel(0xffffffff, gp->regs + GREG_IMASK); gem_reset()
1190 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST, gem_reset()
1215 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); gem_start_dma()
1217 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); gem_start_dma()
1219 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); gem_start_dma()
1221 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); gem_start_dma()
1228 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); gem_start_dma()
1239 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG); gem_stop_dma()
1241 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG); gem_stop_dma()
1243 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG); gem_stop_dma()
1245 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); gem_stop_dma()
1379 writel(val, gp->regs + MAC_TXCFG); gem_set_link_modes()
1393 writel(val, gp->regs + MAC_XIFCFG); gem_set_link_modes()
1400 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); gem_set_link_modes()
1403 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); gem_set_link_modes()
1406 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG); gem_set_link_modes()
1409 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG); gem_set_link_modes()
1421 writel(512, gp->regs + MAC_STIME); gem_set_link_modes()
1423 writel(64, gp->regs + MAC_STIME); gem_set_link_modes()
1429 writel(val, gp->regs + MAC_MCCFG); gem_set_link_modes()
1673 writel(mifcfg, gp->regs + MIF_CFG); gem_init_phy()
1713 writel(val, gp->regs + PCS_DMODE); gem_init_phy()
1749 writel(val, gp->regs + TXDMA_CFG); gem_init_dma()
1751 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI); gem_init_dma()
1752 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW); gem_init_dma()
1755 writel(0, gp->regs + TXDMA_KICK); gem_init_dma()
1759 writel(val, gp->regs + RXDMA_CFG); gem_init_dma()
1761 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI); gem_init_dma()
1762 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW); gem_init_dma()
1764 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK); gem_init_dma()
1768 writel(val, gp->regs + RXDMA_PTHRESH); gem_init_dma()
1771 writel(((5 & RXDMA_BLANK_IPKTS) | gem_init_dma()
1775 writel(((5 & RXDMA_BLANK_IPKTS) | gem_init_dma()
1788 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2)); gem_setup_multicast()
1805 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2)); gem_setup_multicast()
1816 writel(0x1bf0, gp->regs + MAC_SNDPAUSE); gem_init_mac()
1818 writel(0x00, gp->regs + MAC_IPG0); gem_init_mac()
1819 writel(0x08, gp->regs + MAC_IPG1); gem_init_mac()
1820 writel(0x04, gp->regs + MAC_IPG2); gem_init_mac()
1821 writel(0x40, gp->regs + MAC_STIME); gem_init_mac()
1822 writel(0x40, gp->regs + MAC_MINFSZ); gem_init_mac()
1825 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ); gem_init_mac()
1827 writel(0x07, gp->regs + MAC_PASIZE); gem_init_mac()
1828 writel(0x04, gp->regs + MAC_JAMSIZE); gem_init_mac()
1829 writel(0x10, gp->regs + MAC_ATTLIM); gem_init_mac()
1830 writel(0x8808, gp->regs + MAC_MCTYPE); gem_init_mac()
1832 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED); gem_init_mac()
1834 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); gem_init_mac()
1835 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); gem_init_mac()
1836 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); gem_init_mac()
1838 writel(0, gp->regs + MAC_ADDR3); gem_init_mac()
1839 writel(0, gp->regs + MAC_ADDR4); gem_init_mac()
1840 writel(0, gp->regs + MAC_ADDR5); gem_init_mac()
1842 writel(0x0001, gp->regs + MAC_ADDR6); gem_init_mac()
1843 writel(0xc200, gp->regs + MAC_ADDR7); gem_init_mac()
1844 writel(0x0180, gp->regs + MAC_ADDR8); gem_init_mac()
1846 writel(0, gp->regs + MAC_AFILT0); gem_init_mac()
1847 writel(0, gp->regs + MAC_AFILT1); gem_init_mac()
1848 writel(0, gp->regs + MAC_AFILT2); gem_init_mac()
1849 writel(0, gp->regs + MAC_AF21MSK); gem_init_mac()
1850 writel(0, gp->regs + MAC_AF0MSK); gem_init_mac()
1856 writel(0, gp->regs + MAC_NCOLL); gem_init_mac()
1857 writel(0, gp->regs + MAC_FASUCC); gem_init_mac()
1858 writel(0, gp->regs + MAC_ECOLL); gem_init_mac()
1859 writel(0, gp->regs + MAC_LCOLL); gem_init_mac()
1860 writel(0, gp->regs + MAC_DTIMER); gem_init_mac()
1861 writel(0, gp->regs + MAC_PATMPS); gem_init_mac()
1862 writel(0, gp->regs + MAC_RFCTR); gem_init_mac()
1863 writel(0, gp->regs + MAC_LERR); gem_init_mac()
1864 writel(0, gp->regs + MAC_AERR); gem_init_mac()
1865 writel(0, gp->regs + MAC_FCSERR); gem_init_mac()
1866 writel(0, gp->regs + MAC_RXCVERR); gem_init_mac()
1871 writel(0, gp->regs + MAC_TXCFG); gem_init_mac()
1872 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG); gem_init_mac()
1873 writel(0, gp->regs + MAC_MCCFG); gem_init_mac()
1874 writel(0, gp->regs + MAC_XIFCFG); gem_init_mac()
1880 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK); gem_init_mac()
1881 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK); gem_init_mac()
1886 writel(0xffffffff, gp->regs + MAC_MCMASK); gem_init_mac()
1891 writel(0, gp->regs + WOL_WAKECSR); gem_init_mac()
1926 writel(cfg, gp->regs + GREG_CFG); gem_init_pause_thresholds()
1934 writel(cfg, gp->regs + GREG_CFG); gem_init_pause_thresholds()
1956 writel(mif_cfg, gp->regs + MIF_CFG); gem_check_invariants()
1957 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE); gem_check_invariants()
1958 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG); gem_check_invariants()
1993 writel(mif_cfg, gp->regs + MIF_CFG); gem_check_invariants()
1997 writel(mif_cfg, gp->regs + MIF_CFG); gem_check_invariants()
2088 writel(mifcfg, gp->regs + MIF_CFG); gem_stop_phy()
2095 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB, gem_stop_phy()
2097 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0); gem_stop_phy()
2098 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1); gem_stop_phy()
2099 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2); gem_stop_phy()
2101 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT); gem_stop_phy()
2105 writel(csr, gp->regs + WOL_WAKECSR); gem_stop_phy()
2107 writel(0, gp->regs + MAC_RXCFG); gem_stop_phy()
2116 writel(0, gp->regs + MAC_TXCFG); gem_stop_phy()
2117 writel(0, gp->regs + MAC_XIFCFG); gem_stop_phy()
2118 writel(0, gp->regs + TXDMA_CFG); gem_stop_phy()
2119 writel(0, gp->regs + RXDMA_CFG); gem_stop_phy()
2123 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST); gem_stop_phy()
2124 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST); gem_stop_phy()
2132 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG); gem_stop_phy()
2133 writel(0, gp->regs + MIF_BBCLK); gem_stop_phy()
2134 writel(0, gp->regs + MIF_BBDATA); gem_stop_phy()
2135 writel(0, gp->regs + MIF_BBOENAB); gem_stop_phy()
2136 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG); gem_stop_phy()
2403 writel(0, gp->regs + MAC_FCSERR); gem_get_stats()
2406 writel(0, gp->regs + MAC_AERR); gem_get_stats()
2409 writel(0, gp->regs + MAC_LERR); gem_get_stats()
2414 writel(0, gp->regs + MAC_ECOLL); gem_get_stats()
2415 writel(0, gp->regs + MAC_LCOLL); gem_get_stats()
2439 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0); gem_set_mac_address()
2440 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1); gem_set_mac_address()
2441 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2); gem_set_mac_address()
2466 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG); gem_set_multicast()
2476 writel(rxcfg, gp->regs + MAC_RXCFG); gem_set_multicast()
H A Dcassini.c298 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); cas_disable_irq()
315 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, cas_disable_irq()
320 writel(INTRN_MASK_CLEAR_ALL, cp->regs + cas_disable_irq()
338 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); cas_enable_irq()
354 writel(INTRN_MASK_RX_EN, cp->regs + cas_enable_irq()
390 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, cas_entropy_reset()
413 writel(cmd, cp->regs + REG_MIF_FRAME); cas_phy_read()
435 writel(cmd, cp->regs + REG_MIF_FRAME); cas_phy_write()
688 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, cas_mif_poll()
690 writel(cfg, cp->regs + REG_MIF_CFG); cas_mif_poll()
769 writel(val, cp->regs + REG_PCS_MII_CTRL); cas_begin_auto_negotiation()
880 writel(PCS_DATAPATH_MODE_MII, cas_phy_init()
916 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? cas_phy_init()
958 writel(PCS_DATAPATH_MODE_SERDES, cas_phy_init()
963 writel(0, cp->regs + REG_SATURN_PCFG); cas_phy_init()
968 writel(val, cp->regs + REG_PCS_MII_CTRL); cas_phy_init()
984 writel(0x0, cp->regs + REG_PCS_CFG); cas_phy_init()
991 writel(val, cp->regs + REG_PCS_MII_ADVERT); cas_phy_init()
994 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG); cas_phy_init()
997 writel(PCS_SERDES_CTRL_SYNCD_EN, cas_phy_init()
1177 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR); cas_load_firmware()
1181 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); cas_load_firmware()
1190 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); cas_load_firmware()
1196 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); cas_load_firmware()
1215 writel(val, cp->regs + REG_RX_CFG); cas_init_rx_dma()
1219 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); cas_init_rx_dma()
1220 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); cas_init_rx_dma()
1221 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); cas_init_rx_dma()
1229 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); cas_init_rx_dma()
1230 writel((desc_dma + val) & 0xffffffff, cp->regs + cas_init_rx_dma()
1232 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + cas_init_rx_dma()
1239 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); cas_init_rx_dma()
1240 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); cas_init_rx_dma()
1247 writel((desc_dma + val) >> 32, cp->regs + cas_init_rx_dma()
1249 writel((desc_dma + val) & 0xffffffff, cp->regs + cas_init_rx_dma()
1259 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR); cas_init_rx_dma()
1266 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1, cas_init_rx_dma()
1270 writel(INTR_RX_DONE_ALT, cas_init_rx_dma()
1279 writel(val, cp->regs + REG_RX_PAUSE_THRESH); cas_init_rx_dma()
1283 writel(i, cp->regs + REG_RX_TABLE_ADDR); cas_init_rx_dma()
1284 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW); cas_init_rx_dma()
1285 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID); cas_init_rx_dma()
1286 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI); cas_init_rx_dma()
1290 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR); cas_init_rx_dma()
1291 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR); cas_init_rx_dma()
1297 writel(val, cp->regs + REG_RX_BLANK); cas_init_rx_dma()
1299 writel(0x0, cp->regs + REG_RX_BLANK); cas_init_rx_dma()
1309 writel(val, cp->regs + REG_RX_AE_THRESH); cas_init_rx_dma()
1312 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); cas_init_rx_dma()
1318 writel(0x0, cp->regs + REG_RX_RED); cas_init_rx_dma()
1348 writel(val, cp->regs + REG_RX_PAGE_SIZE); cas_init_rx_dma()
1357 writel(val, cp->regs + REG_HP_CFG); cas_init_rx_dma()
1463 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1475 writel(0, cp->regs + REG_RX_CFG);
1489 writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1509 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1510 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1512 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
2209 writel(entry, cp->regs + REG_RX_KICK); cas_post_page()
2212 writel(entry, cp->regs + REG_PLUS_RX_KICK1); cas_post_page()
2270 writel(cluster, cp->regs + REG_RX_KICK); cas_post_rxds_ringN()
2273 writel(cluster, cp->regs + REG_PLUS_RX_KICK1); cas_post_rxds_ringN()
2426 writel(last, cp->regs + REG_RX_COMP_TAIL); cas_post_rxcs_ringN()
2428 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring)); cas_post_rxcs_ringN()
2860 writel(entry, cp->regs + REG_TX_KICKN(ring)); cas_xmit_tx_ringN()
2895 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI); cas_init_tx_dma()
2896 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW); cas_init_tx_dma()
2913 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i)); cas_init_tx_dma()
2914 writel((desc_dma + off) & 0xffffffff, cp->regs + cas_init_tx_dma()
2920 writel(val, cp->regs + REG_TX_CFG); cas_init_tx_dma()
2926 writel(0x800, cp->regs + REG_TX_MAXBURST_0); cas_init_tx_dma()
2927 writel(0x1600, cp->regs + REG_TX_MAXBURST_1); cas_init_tx_dma()
2928 writel(0x2400, cp->regs + REG_TX_MAXBURST_2); cas_init_tx_dma()
2929 writel(0x4800, cp->regs + REG_TX_MAXBURST_3); cas_init_tx_dma()
2931 writel(0x800, cp->regs + REG_TX_MAXBURST_0); cas_init_tx_dma()
2932 writel(0x800, cp->regs + REG_TX_MAXBURST_1); cas_init_tx_dma()
2933 writel(0x800, cp->regs + REG_TX_MAXBURST_2); cas_init_tx_dma()
2934 writel(0x800, cp->regs + REG_TX_MAXBURST_3); cas_init_tx_dma()
2958 writel((ha->addr[4] << 8) | ha->addr[5], cas_process_mc_list()
2960 writel((ha->addr[2] << 8) | ha->addr[3], cas_process_mc_list()
2962 writel((ha->addr[0] << 8) | ha->addr[1], cas_process_mc_list()
2976 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i)); cas_process_mc_list()
2990 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i)); cas_setup_multicast()
3004 writel(0, cp->regs + REG_MAC_COLL_NORMAL); cas_clear_mac_err()
3005 writel(0, cp->regs + REG_MAC_COLL_FIRST); cas_clear_mac_err()
3006 writel(0, cp->regs + REG_MAC_COLL_EXCESS); cas_clear_mac_err()
3007 writel(0, cp->regs + REG_MAC_COLL_LATE); cas_clear_mac_err()
3008 writel(0, cp->regs + REG_MAC_TIMER_DEFER); cas_clear_mac_err()
3009 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK); cas_clear_mac_err()
3010 writel(0, cp->regs + REG_MAC_RECV_FRAME); cas_clear_mac_err()
3011 writel(0, cp->regs + REG_MAC_LEN_ERR); cas_clear_mac_err()
3012 writel(0, cp->regs + REG_MAC_ALIGN_ERR); cas_clear_mac_err()
3013 writel(0, cp->regs + REG_MAC_FCS_ERR); cas_clear_mac_err()
3014 writel(0, cp->regs + REG_MAC_RX_CODE_ERR); cas_clear_mac_err()
3023 writel(0x1, cp->regs + REG_MAC_TX_RESET); cas_mac_reset()
3024 writel(0x1, cp->regs + REG_MAC_RX_RESET); cas_mac_reset()
3059 writel(CAWR_RR_DIS, cp->regs + REG_CAWR); cas_init_mac()
3066 writel(INF_BURST_EN, cp->regs + REG_INF_BURST); cas_init_mac()
3069 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE); cas_init_mac()
3071 writel(0x00, cp->regs + REG_MAC_IPG0); cas_init_mac()
3072 writel(0x08, cp->regs + REG_MAC_IPG1); cas_init_mac()
3073 writel(0x04, cp->regs + REG_MAC_IPG2); cas_init_mac()
3076 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); cas_init_mac()
3079 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN); cas_init_mac()
3085 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) | cas_init_mac()
3095 writel(0x41, cp->regs + REG_MAC_PA_SIZE); cas_init_mac()
3097 writel(0x07, cp->regs + REG_MAC_PA_SIZE); cas_init_mac()
3098 writel(0x04, cp->regs + REG_MAC_JAM_SIZE); cas_init_mac()
3099 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT); cas_init_mac()
3100 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE); cas_init_mac()
3102 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED); cas_init_mac()
3104 writel(0, cp->regs + REG_MAC_ADDR_FILTER0); cas_init_mac()
3105 writel(0, cp->regs + REG_MAC_ADDR_FILTER1); cas_init_mac()
3106 writel(0, cp->regs + REG_MAC_ADDR_FILTER2); cas_init_mac()
3107 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK); cas_init_mac()
3108 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK); cas_init_mac()
3112 writel(0x0, cp->regs + REG_MAC_ADDRN(i)); cas_init_mac()
3114 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0)); cas_init_mac()
3115 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1)); cas_init_mac()
3116 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2)); cas_init_mac()
3118 writel(0x0001, cp->regs + REG_MAC_ADDRN(42)); cas_init_mac()
3119 writel(0xc200, cp->regs + REG_MAC_ADDRN(43)); cas_init_mac()
3120 writel(0x0180, cp->regs + REG_MAC_ADDRN(44)); cas_init_mac()
3132 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK); cas_init_mac()
3133 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); cas_init_mac()
3138 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK); cas_init_mac()
3205 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD, cas_get_vpd_info()
3367 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN); cas_get_vpd_info()
3450 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); cas_check_invariants()
3488 writel(val, cp->regs + REG_TX_CFG); cas_start_dma()
3490 writel(val, cp->regs + REG_RX_CFG); cas_start_dma()
3494 writel(val, cp->regs + REG_MAC_TX_CFG); cas_start_dma()
3496 writel(val, cp->regs + REG_MAC_RX_CFG); cas_start_dma()
3527 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); cas_start_dma()
3528 writel(0, cp->regs + REG_RX_COMP_TAIL); cas_start_dma()
3532 writel(RX_DESC_RINGN_SIZE(1) - 4, cas_start_dma()
3536 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i)); cas_start_dma()
3638 writel(val, cp->regs + REG_MAC_XIF_CFG); cas_set_link_modes()
3659 writel(val | MAC_TX_CFG_CARRIER_EXTEND, cas_set_link_modes()
3664 writel(val | MAC_RX_CFG_CARRIER_EXTEND, cas_set_link_modes()
3667 writel(0x200, cp->regs + REG_MAC_SLOT_TIME); cas_set_link_modes()
3674 writel(val, cp->regs + REG_MAC_TX_CFG); cas_set_link_modes()
3689 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, cas_set_link_modes()
3691 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); cas_set_link_modes()
3715 writel(val, cp->regs + REG_MAC_CTRL_CFG); cas_set_link_modes()
3745 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); cas_hard_reset()
3763 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK), cas_global_reset()
3766 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET); cas_global_reset()
3783 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE | cas_global_reset()
3790 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO | cas_global_reset()
3798 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); cas_global_reset()
3813 writel(val, cp->regs + REG_TX_CFG); cas_reset()
3817 writel(val, cp->regs + REG_RX_CFG); cas_reset()
4502 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); cas_set_multicast()
4512 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); cas_set_multicast()
4522 writel(rxcfg, cp->regs + REG_MAC_RX_CFG); cas_set_multicast()
/linux-4.4.14/drivers/net/ethernet/nxp/
H A Dlpc_eth.c454 writel(tmp, LPC_ENET_SA2(pldat->net_base)); __lpc_set_mac()
456 writel(tmp, LPC_ENET_SA1(pldat->net_base)); __lpc_set_mac()
458 writel(tmp, LPC_ENET_SA0(pldat->net_base)); __lpc_set_mac()
494 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); __lpc_params_setup()
497 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); __lpc_params_setup()
498 writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base)); __lpc_params_setup()
502 writel(tmp, LPC_ENET_MAC2(pldat->net_base)); __lpc_params_setup()
505 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); __lpc_params_setup()
506 writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base)); __lpc_params_setup()
510 writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base)); __lpc_params_setup()
512 writel(0, LPC_ENET_SUPP(pldat->net_base)); __lpc_params_setup()
518 writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX | __lpc_eth_reset()
521 writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET | __lpc_eth_reset()
528 writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base)); __lpc_mii_mngt_reset()
531 writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28), __lpc_mii_mngt_reset()
549 writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN), lpc_eth_enable_int()
555 writel(0, LPC_ENET_INTENABLE(regbase)); lpc_eth_disable_int()
618 writel((ENET_TX_DESC - 1), __lpc_txrx_desc_setup()
620 writel(__va_to_pa(pldat->tx_desc_v, pldat), __lpc_txrx_desc_setup()
622 writel(__va_to_pa(pldat->tx_stat_v, pldat), __lpc_txrx_desc_setup()
624 writel((ENET_RX_DESC - 1), __lpc_txrx_desc_setup()
626 writel(__va_to_pa(pldat->rx_desc_v, pldat), __lpc_txrx_desc_setup()
628 writel(__va_to_pa(pldat->rx_stat_v, pldat), __lpc_txrx_desc_setup()
639 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); __lpc_eth_init()
642 writel(tmp, LPC_ENET_MAC1(pldat->net_base)); __lpc_eth_init()
645 writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base)); __lpc_eth_init()
646 writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE), __lpc_eth_init()
648 writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base)); __lpc_eth_init()
651 writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) | __lpc_eth_init()
654 writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base)); __lpc_eth_init()
657 writel(LPC_COMMAND_PASSRUNTFRAME, __lpc_eth_init()
660 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII), __lpc_eth_init()
662 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base)); __lpc_eth_init()
671 writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT), __lpc_eth_init()
680 writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base)); __lpc_eth_init()
687 writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); __lpc_eth_init()
690 writel(tmp, LPC_ENET_MAC1(pldat->net_base)); __lpc_eth_init()
697 writel(0, LPC_ENET_MAC1(pldat->net_base)); __lpc_eth_shutdown()
698 writel(0, LPC_ENET_MAC2(pldat->net_base)); __lpc_eth_shutdown()
710 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); lpc_mdio_read()
711 writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base)); lpc_mdio_read()
721 writel(0, LPC_ENET_MCMD(pldat->net_base)); lpc_mdio_read()
732 writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); lpc_mdio_write()
733 writel(phydata, LPC_ENET_MWTD(pldat->net_base)); lpc_mdio_write()
837 writel(LPC_COMMAND_PASSRUNTFRAME, lpc_mii_init()
840 writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII), lpc_mii_init()
842 writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base)); lpc_mii_init()
1003 writel(rxconsidx, __lpc_handle_recv()
1042 writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base)); __lpc_eth_interrupt()
1070 writel(0, LPC_ENET_MAC1(pldat->net_base)); lpc_eth_close()
1071 writel(0, LPC_ENET_MAC2(pldat->net_base)); lpc_eth_close()
1120 writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base)); lpc_eth_hard_start_xmit()
1176 writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base)); lpc_eth_set_multicast_list()
1193 writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base));
1194 writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base));
/linux-4.4.14/drivers/tty/serial/
H A Dnetx-serial.c122 writel(val & ~CR_TIE, port->membase + UART_CR); netx_stop_tx()
129 writel(val & ~CR_RIE, port->membase + UART_CR); netx_stop_rx()
136 writel(val | CR_MSIE, port->membase + UART_CR); netx_enable_ms()
144 writel(port->x_char, port->membase + UART_DR); netx_transmit_buffer()
158 writel(xmit->buf[xmit->tail], port->membase + UART_DR); netx_transmit_buffer()
172 writel( netx_start_tx()
209 writel(0, port->membase + UART_SR); netx_rxint()
264 writel(0, port->membase + UART_IIR); netx_int()
289 writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR); netx_set_mctrl()
303 writel(line_cr, port->membase + UART_LINE_CR); netx_break_ctl()
319 writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN, netx_startup()
322 writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN, netx_startup()
331 writel(0, port->membase + UART_CR) ; netx_shutdown()
385 writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE), netx_set_termios()
392 writel(old_cr & ~CR_UART_EN, port->membase + UART_CR); netx_set_termios()
399 writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB); netx_set_termios()
400 writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB); netx_set_termios()
401 writel(line_cr, port->membase + UART_LINE_CR); netx_set_termios()
403 writel(rts_cr, port->membase + UART_RTS_CR); netx_set_termios()
427 writel(old_cr, port->membase + UART_CR); netx_set_termios()
532 writel(ch, port->membase + UART_DR); netx_console_putchar()
542 writel(cr_save | CR_UART_EN, port->membase + UART_CR); netx_console_write()
547 writel(cr_save, port->membase + UART_CR); netx_console_write()
687 writel(1, port->membase + UART_RXFIFO_IRQLEVEL); serial_netx_probe()
H A Dimx.c305 writel(ucr->ucr1, port->membase + UCR1); imx_port_ucrs_restore()
306 writel(ucr->ucr2, port->membase + UCR2); imx_port_ucrs_restore()
307 writel(ucr->ucr3, port->membase + UCR3); imx_port_ucrs_restore()
372 writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1); imx_stop_tx()
382 writel(temp, port->membase + UCR2); imx_stop_tx()
386 writel(temp, port->membase + UCR4); imx_stop_tx()
408 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2); imx_stop_rx()
412 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1); imx_stop_rx()
433 writel(sport->port.x_char, sport->port.membase + URTX0); imx_transmit_buffer()
453 writel(temp, sport->port.membase + UCR1); imx_transmit_buffer()
455 writel(temp, sport->port.membase + UCR1); imx_transmit_buffer()
464 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0); imx_transmit_buffer()
490 writel(temp, sport->port.membase + UCR1); dma_tx_callback()
564 writel(temp, sport->port.membase + UCR1); imx_dma_tx()
588 writel(temp, port->membase + UCR2); imx_start_tx()
592 writel(temp, port->membase + UCR4); imx_start_tx()
597 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1); imx_start_tx()
607 writel(temp, sport->port.membase + UCR1); imx_start_tx()
626 writel(USR1_RTSD, sport->port.membase + USR1); imx_rtsint()
663 writel(USR2_BRCD, sport->port.membase + USR2); imx_rxint()
735 writel(temp, sport->port.membase + UCR1); imx_dma_rxint()
739 writel(temp, sport->port.membase + UCR2); imx_dma_rxint()
774 writel(USR1_AWAKE, sport->port.membase + USR1); imx_int()
778 writel(USR2_ORE, sport->port.membase + USR2); imx_int()
831 writel(temp, sport->port.membase + UCR2); imx_set_mctrl()
837 writel(temp, sport->port.membase + uts_reg(sport)); imx_set_mctrl()
855 writel(temp, sport->port.membase + UCR1); imx_break_ctl()
871 writel(temp, sport->port.membase + UCR1); imx_rx_dma_done()
875 writel(temp, sport->port.membase + UCR2); imx_rx_dma_done()
981 writel(val, sport->port.membase + UFCR); imx_setup_ufcr()
1068 writel(temp, sport->port.membase + UCR1); imx_enable_dma()
1072 writel(temp, sport->port.membase + UCR2); imx_enable_dma()
1086 writel(temp, sport->port.membase + UCR1); imx_disable_dma()
1091 writel(temp, sport->port.membase + UCR2); imx_disable_dma()
1127 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4); imx_startup()
1140 writel(temp, sport->port.membase + UCR2); imx_startup()
1148 writel(USR1_RTSD, sport->port.membase + USR1); imx_startup()
1149 writel(USR2_ORE, sport->port.membase + USR2); imx_startup()
1157 writel(temp, sport->port.membase + UCR1); imx_startup()
1161 writel(temp, sport->port.membase + UCR4); imx_startup()
1167 writel(temp, sport->port.membase + UCR2); imx_startup()
1172 writel(temp, sport->port.membase + UCR3); imx_startup()
1213 writel(temp, sport->port.membase + UCR2); imx_shutdown()
1229 writel(temp, sport->port.membase + UCR1); imx_shutdown()
1253 writel(temp, sport->port.membase + UCR1); imx_flush_buffer()
1270 writel(temp, sport->port.membase + UCR2); imx_flush_buffer()
1276 writel(ubir, sport->port.membase + UBIR); imx_flush_buffer()
1277 writel(ubmr, sport->port.membase + UBMR); imx_flush_buffer()
1278 writel(uts, sport->port.membase + IMX21_UTS); imx_flush_buffer()
1384 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN), imx_set_termios()
1392 writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN), imx_set_termios()
1423 writel(ufcr, sport->port.membase + UFCR); imx_set_termios()
1425 writel(num, sport->port.membase + UBIR); imx_set_termios()
1426 writel(denom, sport->port.membase + UBMR); imx_set_termios()
1429 writel(sport->port.uartclk / div / 1000, imx_set_termios()
1432 writel(old_ucr1, sport->port.membase + UCR1); imx_set_termios()
1435 writel(ucr2 | old_ucr2, sport->port.membase + UCR2); imx_set_termios()
1514 writel(temp, sport->port.membase + UCR1); imx_poll_init()
1518 writel(temp, sport->port.membase + UCR2); imx_poll_init()
1576 writel(temp, sport->port.membase + UCR2); imx_rs485_config()
1617 writel(ch, sport->port.membase + URTX0); imx_console_putchar()
1660 writel(ucr1, sport->port.membase + UCR1); imx_console_write()
1662 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2); imx_console_write()
2020 writel(sport->saved_reg[4], sport->port.membase + UFCR); serial_imx_restore_context()
2021 writel(sport->saved_reg[5], sport->port.membase + UESC); serial_imx_restore_context()
2022 writel(sport->saved_reg[6], sport->port.membase + UTIM); serial_imx_restore_context()
2023 writel(sport->saved_reg[7], sport->port.membase + UBIR); serial_imx_restore_context()
2024 writel(sport->saved_reg[8], sport->port.membase + UBMR); serial_imx_restore_context()
2025 writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS); serial_imx_restore_context()
2026 writel(sport->saved_reg[0], sport->port.membase + UCR1); serial_imx_restore_context()
2027 writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2); serial_imx_restore_context()
2028 writel(sport->saved_reg[2], sport->port.membase + UCR3); serial_imx_restore_context()
2029 writel(sport->saved_reg[3], sport->port.membase + UCR4); serial_imx_restore_context()
2058 writel(val, sport->port.membase + UCR3); serial_imx_enable_wakeup()
2065 writel(val, sport->port.membase + UCR1); serial_imx_enable_wakeup()
H A Dxilinx_uartps.c210 writel(CDNS_UART_IXR_FRAMING, cdns_uart_isr()
276 writel(CDNS_UART_IXR_TXEMPTY, cdns_uart_isr()
288 writel(port->state->xmit.buf[ cdns_uart_isr()
308 writel(isrstatus, port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_isr()
403 writel(mreg, port->membase + CDNS_UART_MR_OFFSET); cdns_uart_set_baud_rate()
404 writel(cd, port->membase + CDNS_UART_BAUDGEN_OFFSET); cdns_uart_set_baud_rate()
405 writel(bdiv, port->membase + CDNS_UART_BAUDDIV_OFFSET); cdns_uart_set_baud_rate()
454 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
481 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
492 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_clk_notifier_cb()
496 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_clk_notifier_cb()
522 writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, cdns_uart_start_tx()
534 writel(port->state->xmit.buf[port->state->xmit.tail], cdns_uart_start_tx()
544 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR_OFFSET); cdns_uart_start_tx()
546 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_start_tx()
563 writel(regval, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_tx()
577 writel(regval, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_stop_rx()
611 writel(CDNS_UART_CR_STARTBRK | status, cdns_uart_break_ctl()
615 writel(CDNS_UART_CR_STOPBRK | status, cdns_uart_break_ctl()
650 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
671 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
680 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_set_termios()
682 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_set_termios()
743 writel(cval, port->membase + CDNS_UART_MR_OFFSET); cdns_uart_set_termios()
764 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, cdns_uart_startup()
770 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST, cdns_uart_startup()
778 writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS)) cdns_uart_startup()
786 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT cdns_uart_startup()
794 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM_OFFSET); cdns_uart_startup()
800 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_startup()
803 writel(readl(port->membase + CDNS_UART_ISR_OFFSET), cdns_uart_startup()
807 writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY | cdns_uart_startup()
825 writel(status, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_shutdown()
828 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS, cdns_uart_shutdown()
940 writel(val, port->membase + CDNS_UART_MODEMCR_OFFSET); cdns_uart_set_mctrl()
951 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_poll_get_char()
961 writel(imr, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_poll_get_char()
972 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_poll_put_char()
980 writel(c, port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_poll_put_char()
988 writel(imr, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_poll_put_char()
1075 writel(ch, port->membase + CDNS_UART_FIFO_OFFSET); cdns_uart_console_putchar()
1119 writel(imr, port->membase + CDNS_UART_IDR_OFFSET); cdns_uart_console_write()
1126 writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN, cdns_uart_console_write()
1132 writel(ctrl, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_console_write()
1135 writel(imr, port->membase + CDNS_UART_IER_OFFSET); cdns_uart_console_write()
1251 writel(1, port->membase + CDNS_UART_RXWM_OFFSET); cdns_uart_suspend()
1253 writel(CDNS_UART_IXR_TOUT, cdns_uart_suspend()
1295 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_resume()
1301 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT_OFFSET); cdns_uart_resume()
1306 writel(ctrl_reg, port->membase + CDNS_UART_CR_OFFSET); cdns_uart_resume()
1312 writel(rx_trigger_level, cdns_uart_resume()
1315 writel(CDNS_UART_IXR_TOUT, cdns_uart_resume()
H A Dlpc32xx_hs.c136 writel((u32)ch, LPC32XX_HSUART_FIFO(port->membase)); lpc32xx_hsuart_console_putchar()
271 writel(LPC32XX_HSU_FE_INT, __serial_lpc32xx_rx()
294 writel((u32)port->x_char, LPC32XX_HSUART_FIFO(port->membase)); __serial_lpc32xx_tx()
306 writel((u32) xmit->buf[xmit->tail], __serial_lpc32xx_tx()
321 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); __serial_lpc32xx_tx()
338 writel(LPC32XX_HSU_BRK_INT, LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
345 writel(LPC32XX_HSU_FE_INT, LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
349 writel(LPC32XX_HSU_RX_OE_INT, serial_lpc32xx_interrupt()
362 writel(LPC32XX_HSU_TX_INT, LPC32XX_HSUART_IIR(port->membase)); serial_lpc32xx_interrupt()
403 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_stop_tx()
414 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_start_tx()
424 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_stop_rx()
426 writel((LPC32XX_HSU_BRK_INT | LPC32XX_HSU_RX_OE_INT | serial_lpc32xx_stop_rx()
443 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_break_ctl()
473 writel(tmp, LPC32XX_UARTCTL_CLOOP); lpc32xx_loopback_set()
487 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | serial_lpc32xx_startup()
491 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); serial_lpc32xx_startup()
499 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_startup()
508 writel((tmp | LPC32XX_HSU_RX_INT_EN | LPC32XX_HSU_ERR_INT_EN), serial_lpc32xx_startup()
524 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_shutdown()
561 writel(tmp, LPC32XX_HSUART_CTRL(port->membase)); serial_lpc32xx_set_termios()
563 writel(quot, LPC32XX_HSUART_RATE(port->membase)); serial_lpc32xx_set_termios()
624 writel((LPC32XX_HSU_TX_INT | LPC32XX_HSU_FE_INT | serial_lpc32xx_config_port()
628 writel(0xFF, LPC32XX_HSUART_RATE(port->membase)); serial_lpc32xx_config_port()
632 writel(LPC32XX_HSU_TX_TL8B | LPC32XX_HSU_RX_TL32B | serial_lpc32xx_config_port()
/linux-4.4.14/drivers/mmc/host/
H A Dmoxart-mmc.c192 writel(*status & mask, host->base + REG_CLEAR); moxart_wait_for_status()
209 writel(RSP_TIMEOUT | RSP_CRC_OK | moxart_send_command()
211 writel(cmd->arg, host->base + REG_ARGUMENT); moxart_send_command()
225 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); moxart_send_command()
390 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); moxart_prepare_data()
391 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); moxart_prepare_data()
392 writel(host->rate, host->base + REG_DATA_TIMER); moxart_prepare_data()
393 writel(host->data_len, host->base + REG_DATA_LENGTH); moxart_prepare_data()
394 writel(datactrl, host->base + REG_DATA_CONTROL); moxart_prepare_data()
421 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); moxart_request()
430 writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK); moxart_request()
481 writel(MASK_INTR_PIO, host->base + REG_CLEAR); moxart_irq()
482 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); moxart_irq()
511 writel(ctrl, host->base + REG_CLOCK_CONTROL); moxart_set_ios()
515 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, moxart_set_ios()
523 writel(SD_POWER_ON | (u32) power, moxart_set_ios()
529 writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH); moxart_set_ios()
532 writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH); moxart_set_ios()
535 writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH); moxart_set_ios()
660 writel(0, host->base + REG_INTERRUPT_MASK); moxart_probe()
662 writel(CMD_SDC_RESET, host->base + REG_COMMAND); moxart_probe()
701 writel(0, host->base + REG_INTERRUPT_MASK); moxart_remove()
702 writel(0, host->base + REG_POWER_CONTROL); moxart_remove()
703 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, moxart_remove()
H A Dtifm_sd.c150 writel(val, sock->addr + SOCK_MMCSD_DATA); tifm_sd_write_fifo()
162 writel(val, sock->addr + SOCK_MMCSD_DATA); tifm_sd_write_fifo()
185 writel(host->bounce_buf_data[0], tifm_sd_transfer_data()
319 writel(sg_dma_address(sg) + dma_off, sock->addr + SOCK_DMA_ADDRESS); tifm_sd_set_dma_data()
321 writel((dma_blk_cnt << 8) | TIFM_DMA_TX | TIFM_DMA_EN, tifm_sd_set_dma_data()
324 writel((dma_blk_cnt << 8) | TIFM_DMA_EN, tifm_sd_set_dma_data()
386 writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH); tifm_sd_exec()
387 writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW); tifm_sd_exec()
388 writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND); tifm_sd_exec()
433 writel(TIFM_MMCSD_EOFB tifm_sd_check_status()
444 writel((~TIFM_MMCSD_EOFB) tifm_sd_check_status()
453 writel((~TIFM_MMCSD_EOFB) tifm_sd_check_status()
499 writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS); tifm_sd_data_event()
522 writel(host_status & TIFM_MMCSD_ERRMASK, tifm_sd_card_event()
536 writel(TIFM_FIFO_INT_SETALL, tifm_sd_card_event()
538 writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL); tifm_sd_card_event()
569 writel(host_status & TIFM_MMCSD_AE, tifm_sd_card_event()
589 writel(host_status, sock->addr + SOCK_MMCSD_STATUS); tifm_sd_card_event()
606 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO); tifm_sd_set_data_timeout()
607 writel((~TIFM_MMCSD_DPE) tifm_sd_set_data_timeout()
614 writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO); tifm_sd_set_data_timeout()
615 writel(TIFM_MMCSD_DPE tifm_sd_set_data_timeout()
654 writel(TIFM_MMCSD_EOFB tifm_sd_request()
659 writel(TIFM_MMCSD_BUFINT tifm_sd_request()
662 writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) tifm_sd_request()
697 writel(TIFM_FIFO_INT_SETALL, tifm_sd_request()
699 writel(ilog2(r_data->blksz) - 2, tifm_sd_request()
701 writel(TIFM_FIFO_ENABLE, tifm_sd_request()
703 writel(TIFM_FIFO_INTMASK, tifm_sd_request()
707 writel(TIFM_MMCSD_TXDE, tifm_sd_request()
710 writel(TIFM_MMCSD_RXDE, tifm_sd_request()
716 writel(r_data->blocks - 1, tifm_sd_request()
718 writel(r_data->blksz - 1, tifm_sd_request()
724 writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL), tifm_sd_request()
760 writel((~TIFM_MMCSD_BUFINT) tifm_sd_end_cmd()
779 writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL), tifm_sd_end_cmd()
812 writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG), tifm_sd_ios()
815 writel((~TIFM_MMCSD_4BBUS) tifm_sd_ios()
836 writel((~TIFM_CTRL_FAST_CLK) tifm_sd_ios()
842 writel(TIFM_CTRL_FAST_CLK tifm_sd_ios()
850 writel(host->clk_div tifm_sd_ios()
890 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE); tifm_sd_initialize_host()
894 writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL); tifm_sd_initialize_host()
895 writel(host->clk_div | TIFM_MMCSD_POWER, tifm_sd_initialize_host()
913 writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS); tifm_sd_initialize_host()
914 writel(host->clk_div | TIFM_MMCSD_POWER, tifm_sd_initialize_host()
916 writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG); tifm_sd_initialize_host()
919 writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); tifm_sd_initialize_host()
920 writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND); tifm_sd_initialize_host()
924 writel(host_status, sock->addr + SOCK_MMCSD_STATUS); tifm_sd_initialize_host()
939 writel(TIFM_MMCSD_CERR | TIFM_MMCSD_BRS | TIFM_MMCSD_EOC tifm_sd_initialize_host()
1006 writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE); tifm_sd_remove()
1014 writel(TIFM_FIFO_INT_SETALL, tifm_sd_remove()
1016 writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET); tifm_sd_remove()
H A Ddavinci_mmc.c262 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); davinci_fifo_data_trans()
361 writel(0x1FFF, host->base + DAVINCI_MMCTOR); mmc_davinci_start_command()
384 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); mmc_davinci_start_command()
385 writel(cmd_reg, host->base + DAVINCI_MMCCMD); mmc_davinci_start_command()
399 writel(im_val, host->base + DAVINCI_MMCIM); mmc_davinci_start_command()
566 writel(0, host->base + DAVINCI_MMCBLEN); mmc_davinci_prepare_data()
567 writel(0, host->base + DAVINCI_MMCNBLK); mmc_davinci_prepare_data()
582 writel(timeout, host->base + DAVINCI_MMCTOD); mmc_davinci_prepare_data()
583 writel(data->blocks, host->base + DAVINCI_MMCNBLK); mmc_davinci_prepare_data()
584 writel(data->blksz, host->base + DAVINCI_MMCBLEN); mmc_davinci_prepare_data()
590 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST, mmc_davinci_prepare_data()
592 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR, mmc_davinci_prepare_data()
598 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST, mmc_davinci_prepare_data()
600 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD, mmc_davinci_prepare_data()
703 writel(temp, host->base + DAVINCI_MMCCLK); calculate_clk_divider()
715 writel(temp, host->base + DAVINCI_MMCCLK); calculate_clk_divider()
721 writel(temp, host->base + DAVINCI_MMCCLK); calculate_clk_divider()
723 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); calculate_clk_divider()
754 writel((readl(host->base + DAVINCI_MMCCTL) & mmc_davinci_set_ios()
761 writel((readl(host->base + DAVINCI_MMCCTL) & mmc_davinci_set_ios()
765 writel(readl(host->base + DAVINCI_MMCCTL) | mmc_davinci_set_ios()
772 writel(readl(host->base + DAVINCI_MMCCTL) & mmc_davinci_set_ios()
776 writel(readl(host->base + DAVINCI_MMCCTL) & mmc_davinci_set_ios()
790 writel(0, host->base + DAVINCI_MMCARGHL); mmc_davinci_set_ios()
791 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD); mmc_davinci_set_ios()
821 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); mmc_davinci_xfer_done()
839 writel(0, host->base + DAVINCI_MMCIM); mmc_davinci_xfer_done()
867 writel(0, host->base + DAVINCI_MMCIM); mmc_davinci_cmd_done()
883 writel(temp, host->base + DAVINCI_MMCCTL); mmc_davinci_reset_ctrl()
903 writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); mmc_davinci_sdio_irq()
922 writel(0, host->base + DAVINCI_MMCIM); mmc_davinci_irq()
947 writel(0, host->base + DAVINCI_MMCIM); mmc_davinci_irq()
962 writel(im_val, host->base + DAVINCI_MMCIM); mmc_davinci_irq()
1080 writel(SDIOIST_IOINT, host->base + DAVINCI_SDIOIST); mmc_davinci_enable_sdio_irq()
1084 writel(readl(host->base + DAVINCI_SDIOIEN) | mmc_davinci_enable_sdio_irq()
1089 writel(readl(host->base + DAVINCI_SDIOIEN) & ~SDIOIEN_IOINTEN, mmc_davinci_enable_sdio_irq()
1155 writel(0, host->base + DAVINCI_MMCCLK); init_mmcsd_host()
1156 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK); init_mmcsd_host()
1158 writel(0x1FFF, host->base + DAVINCI_MMCTOR); init_mmcsd_host()
1159 writel(0xFFFF, host->base + DAVINCI_MMCTOD); init_mmcsd_host()
1438 writel(0, host->base + DAVINCI_MMCIM); davinci_mmcsd_suspend()
/linux-4.4.14/arch/mips/include/asm/mach-jz4740/
H A Dtimer.h66 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_SET); jz4740_timer_stop()
71 writel(BIT(timer), jz4740_timer_base + JZ_REG_TIMER_STOP_CLEAR); jz4740_timer_start()
111 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); jz4740_timer_ack_full()
116 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_FLAG_CLEAR); jz4740_timer_irq_full_enable()
117 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_CLEAR); jz4740_timer_irq_full_enable()
122 writel(JZ_TIMER_IRQ_FULL(timer), jz4740_timer_base + JZ_REG_TIMER_MASK_SET); jz4740_timer_irq_full_disable()
/linux-4.4.14/arch/arm/mach-socfpga/
H A Dplatsmp.c38 writel(RSTMGR_MPUMODRST_CPU1, socfpga_boot_secondary()
43 writel(virt_to_phys(secondary_startup), socfpga_boot_secondary()
51 writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST); socfpga_boot_secondary()
62 writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + socfpga_a10_boot_secondary()
66 writel(virt_to_phys(secondary_startup), socfpga_a10_boot_secondary()
74 writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST); socfpga_a10_boot_secondary()
/linux-4.4.14/arch/arm/mach-dove/
H A Dmpp.c77 writel(mpp_gen_cfg, DOVE_MPP_GENERAL_VIRT_BASE); dove_mpp_cfg_nfc()
114 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); dove_mpp_cfg_au1()
115 writel(ssp_ctrl1, DOVE_SSP_CTRL_STATUS_1); dove_mpp_cfg_au1()
116 writel(mpp_gen_ctrl, DOVE_MPP_GENERAL_VIRT_BASE); dove_mpp_cfg_au1()
117 writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2); dove_mpp_cfg_au1()
143 writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE); dove_mpp_conf_grp()
/linux-4.4.14/arch/arm/mach-ep93xx/
H A Dtimer-ep93xx.c79 writel(tmode, EP93XX_TIMER3_CONTROL); ep93xx_clkevt_set_next_event()
82 writel(next, EP93XX_TIMER3_LOAD); ep93xx_clkevt_set_next_event()
83 writel(tmode | EP93XX_TIMER123_CONTROL_ENABLE, ep93xx_clkevt_set_next_event()
92 writel(0, EP93XX_TIMER3_CONTROL); ep93xx_clkevt_shutdown()
112 writel(1, EP93XX_TIMER3_CLEAR); ep93xx_timer_interrupt()
129 writel(EP93XX_TIMER4_VALUE_HIGH_ENABLE, ep93xx_timer_init()
/linux-4.4.14/drivers/usb/chipidea/
H A Dusbmisc_imx.c114 writel(val, usbmisc->base); usbmisc_imx25_init()
123 writel(val, usbmisc->base); usbmisc_imx25_init()
146 writel(val | MX25_BM_EXTERNAL_VBUS_DIVIDER, reg); usbmisc_imx25_post()
179 writel(val, usbmisc->base); usbmisc_imx27_init()
199 writel(val, usbmisc->base + MX53_USB_OTG_PHY_CTRL_1_OFFSET); usbmisc_imx53_init()
222 writel(val, reg); usbmisc_imx53_init()
246 writel(val, usbmisc->base + data->index * 4); usbmisc_imx6q_set_wakeup()
251 writel(val, usbmisc->base + data->index * 4); usbmisc_imx6q_set_wakeup()
271 writel(reg | MX6_BM_OVER_CUR_DIS, usbmisc_imx6q_init()
277 writel(reg | MX6_BM_NON_BURST_SETTING, usbmisc_imx6q_init()
301 writel(val | MX6SX_USB_VBUS_WAKEUP_SOURCE_BVALID, reg); usbmisc_imx6sx_init()
307 writel(val & ~MX6SX_BM_DPDM_WAKEUP_EN, usbmisc_imx6sx_init()
329 writel(reg | VF610_OVER_CUR_DIS, usbmisc->base); usbmisc_vf610_init()
347 writel(val | wakeup_setting, usbmisc->base); usbmisc_imx7d_set_wakeup()
351 writel(val & ~wakeup_setting, usbmisc->base); usbmisc_imx7d_set_wakeup()
370 writel(reg | MX6_BM_OVER_CUR_DIS, usbmisc->base); usbmisc_imx7d_init()
375 writel(reg | MX7D_USB_VBUS_WAKEUP_SOURCE_BVALID, usbmisc_imx7d_init()
/linux-4.4.14/drivers/rtc/
H A Drtc-stmp3xxx.c91 writel(timeout, rtc_data->io + STMP3XXX_RTC_WATCHDOG); stmp3xxx_wdt_set_timeout()
92 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, stmp3xxx_wdt_set_timeout()
94 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, stmp3xxx_wdt_set_timeout()
97 writel(STMP3XXX_RTC_CTRL_WATCHDOGEN, stmp3xxx_wdt_set_timeout()
99 writel(STMP3XXX_RTC_PERSISTENT1_FORCE_UPDATER, stmp3xxx_wdt_set_timeout()
166 writel(t, rtc_data->io + STMP3XXX_RTC_SECONDS); stmp3xxx_rtc_set_mmss()
177 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ, stmp3xxx_rtc_interrupt()
191 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | stmp3xxx_alarm_irq_enable()
195 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, stmp3xxx_alarm_irq_enable()
198 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | stmp3xxx_alarm_irq_enable()
202 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, stmp3xxx_alarm_irq_enable()
222 writel(t, rtc_data->io + STMP3XXX_RTC_ALARM); stmp3xxx_rtc_set_alarm()
245 writel(STMP3XXX_RTC_CTRL_ALARM_IRQ_EN, stmp3xxx_rtc_remove()
335 writel(pers0_set, rtc_data->io + STMP3XXX_RTC_PERSISTENT0 + stmp3xxx_rtc_probe()
338 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | stmp3xxx_rtc_probe()
343 writel(STMP3XXX_RTC_CTRL_ONEMSEC_IRQ_EN | stmp3xxx_rtc_probe()
375 writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN | stmp3xxx_rtc_resume()
H A Drtc-sun6i.c128 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); sun6i_rtc_alarmirq()
149 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, sun6i_rtc_setaie()
153 writel(alrm_val, chip->base + SUN6I_ALRM_EN); sun6i_rtc_setaie()
154 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); sun6i_rtc_setaie()
155 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); sun6i_rtc_setaie()
237 writel(0, chip->base + SUN6I_ALRM_COUNTER); sun6i_rtc_setalarm()
240 writel(time_gap, chip->base + SUN6I_ALRM_COUNTER); sun6i_rtc_setalarm()
301 writel(time, chip->base + SUN6I_RTC_HMS); sun6i_rtc_settime()
315 writel(date, chip->base + SUN6I_RTC_YMD); sun6i_rtc_settime()
382 writel(0, chip->base + SUN6I_ALRM_COUNTER); sun6i_rtc_probe()
385 writel(0, chip->base + SUN6I_ALRM_EN); sun6i_rtc_probe()
388 writel(0, chip->base + SUN6I_ALRM_IRQ_EN); sun6i_rtc_probe()
391 writel(0, chip->base + SUN6I_ALRM1_EN); sun6i_rtc_probe()
394 writel(0, chip->base + SUN6I_ALRM1_IRQ_EN); sun6i_rtc_probe()
397 writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND, sun6i_rtc_probe()
401 writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND, sun6i_rtc_probe()
405 writel(0, chip->base + SUN6I_ALARM_CONFIG); sun6i_rtc_probe()
H A Drtc-mv.c59 writel(rtc_reg, ioaddr + RTC_TIME_REG_OFFS); mv_rtc_set_time()
64 writel(rtc_reg, ioaddr + RTC_DATE_REG_OFFS); mv_rtc_set_time()
153 writel(rtc_reg, ioaddr + RTC_ALARM_TIME_REG_OFFS); mv_rtc_set_alarm()
169 writel(rtc_reg, ioaddr + RTC_ALARM_DATE_REG_OFFS); mv_rtc_set_alarm()
170 writel(0, ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS); mv_rtc_set_alarm()
171 writel(alm->enabled ? 1 : 0, mv_rtc_set_alarm()
187 writel(1, ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS); mv_rtc_alarm_irq_enable()
189 writel(0, ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS); mv_rtc_alarm_irq_enable()
203 writel(0, ioaddr + RTC_ALARM_INTERRUPT_CASUE_REG_OFFS); mv_rtc_interrupt()
270 writel(0x130101, pdata->ioaddr + RTC_DATE_REG_OFFS); mv_rtc_probe()
292 writel(0, pdata->ioaddr + RTC_ALARM_INTERRUPT_MASK_REG_OFFS); mv_rtc_probe()
H A Drtc-coh901331.c59 writel(1, rtap->virtbase + COH901331_IRQ_EVENT); coh901331_interrupt()
67 writel(0, rtap->virtbase + COH901331_IRQ_MASK); coh901331_interrupt()
96 writel(secs, rtap->virtbase + COH901331_SET_TIME); coh901331_set_mmss()
122 writel(time, rtap->virtbase + COH901331_ALARM); coh901331_set_alarm()
123 writel(alarm->enabled, rtap->virtbase + COH901331_IRQ_MASK); coh901331_set_alarm()
135 writel(1, rtap->virtbase + COH901331_IRQ_MASK); coh901331_alarm_irq_enable()
137 writel(0, rtap->virtbase + COH901331_IRQ_MASK); coh901331_alarm_irq_enable()
228 writel(0, rtap->virtbase + COH901331_IRQ_MASK); coh901331_suspend()
244 writel(rtap->irqmaskstore, rtap->virtbase + COH901331_IRQ_MASK); coh901331_resume()
258 writel(0, rtap->virtbase + COH901331_IRQ_MASK); coh901331_shutdown()
/linux-4.4.14/drivers/mtd/spi-nor/
H A Dfsl-quadspi.c313 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); fsl_qspi_unlock_lut()
314 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); fsl_qspi_unlock_lut()
319 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); fsl_qspi_lock_lut()
320 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); fsl_qspi_lock_lut()
330 writel(reg, q->iobase + QUADSPI_FR); fsl_qspi_irq_handler()
351 writel(0, base + QUADSPI_LUT_BASE + i * 4); fsl_qspi_init_lut()
367 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), fsl_qspi_init_lut()
369 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), fsl_qspi_init_lut()
374 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); fsl_qspi_init_lut()
388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), fsl_qspi_init_lut()
390 writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); fsl_qspi_init_lut()
394 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1), fsl_qspi_init_lut()
403 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), fsl_qspi_init_lut()
408 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), fsl_qspi_init_lut()
413 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8), fsl_qspi_init_lut()
418 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2), fsl_qspi_init_lut()
423 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1), fsl_qspi_init_lut()
428 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); fsl_qspi_init_lut()
432 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); fsl_qspi_init_lut()
436 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); fsl_qspi_init_lut()
493 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR); fsl_qspi_runcmd()
494 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, fsl_qspi_runcmd()
496 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); fsl_qspi_runcmd()
510 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR); fsl_qspi_runcmd()
524 writel(reg, base + QUADSPI_MCR); fsl_qspi_runcmd()
566 writel(reg, q->iobase + QUADSPI_MCR); fsl_qspi_invalid()
575 writel(reg, q->iobase + QUADSPI_MCR); fsl_qspi_invalid()
590 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); fsl_qspi_nor_write()
595 writel(tmp, q->iobase + QUADSPI_TBDR); fsl_qspi_nor_write()
602 writel(tmp, q->iobase + QUADSPI_TBDR); fsl_qspi_nor_write()
618 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); fsl_qspi_set_map_addr()
619 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); fsl_qspi_set_map_addr()
620 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); fsl_qspi_set_map_addr()
621 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); fsl_qspi_set_map_addr()
643 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); fsl_qspi_init_abh_read()
644 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); fsl_qspi_init_abh_read()
645 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); fsl_qspi_init_abh_read()
650 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8) fsl_qspi_init_abh_read()
654 writel(0, base + QUADSPI_BUF0IND); fsl_qspi_init_abh_read()
655 writel(0, base + QUADSPI_BUF1IND); fsl_qspi_init_abh_read()
656 writel(0, base + QUADSPI_BUF2IND); fsl_qspi_init_abh_read()
660 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT, fsl_qspi_init_abh_read()
716 writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, fsl_qspi_nor_setup()
724 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, fsl_qspi_nor_setup()
728 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK fsl_qspi_nor_setup()
734 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, fsl_qspi_nor_setup()
738 writel(0xffffffff, q->iobase + QUADSPI_FR); fsl_qspi_nor_setup()
741 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); fsl_qspi_nor_setup()
1106 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); fsl_qspi_remove()
1107 writel(0x0, q->iobase + QUADSPI_RSER); fsl_qspi_remove()
/linux-4.4.14/drivers/bcma/
H A Ddriver_chipcommon_b.c37 writel(offset, ccb->mii + 0x00); bcma_chipco_b_mii_write()
39 writel(value, ccb->mii + 0x04); bcma_chipco_b_mii_write()
/linux-4.4.14/arch/unicore32/include/mach/
H A Ddma.h40 writel(readl(DMAC_CONFIG(ch)) & ~DMAC_CONFIG_EN, DMAC_CONFIG(ch)); puv3_stop_dma()
45 writel(readl(DMAC_CONFIG(ch)) | DMAC_CONFIG_EN, DMAC_CONFIG(ch)); puv3_resume_dma()
/linux-4.4.14/drivers/watchdog/
H A Dpnx4008_wdt.c90 writel(RESET_COUNT, WDTIM_CTRL(wdt_base)); pnx4008_wdt_start()
95 writel(M_RES2 | STOP_COUNT0 | RESET_COUNT0, WDTIM_MCTRL(wdt_base)); pnx4008_wdt_start()
97 writel(MATCH_OUTPUT_HIGH, WDTIM_EMR(wdt_base)); pnx4008_wdt_start()
99 writel(MATCH_INT, WDTIM_INT(wdt_base)); pnx4008_wdt_start()
101 writel(0xFFFF, WDTIM_PULSE(wdt_base)); pnx4008_wdt_start()
102 writel(wdd->timeout * WDOG_COUNTER_RATE, WDTIM_MATCH0(wdt_base)); pnx4008_wdt_start()
104 writel(COUNT_ENAB | DEBUG_EN, WDTIM_CTRL(wdt_base)); pnx4008_wdt_start()
114 writel(0, WDTIM_CTRL(wdt_base)); /*stop counter */ pnx4008_wdt_stop()
H A Dmoxart_wdt.c43 writel(1, moxart_wdt->base + REG_COUNT); moxart_restart_handle()
44 writel(0x5ab9, moxart_wdt->base + REG_MODE); moxart_restart_handle()
45 writel(0x03, moxart_wdt->base + REG_ENABLE); moxart_restart_handle()
54 writel(0, moxart_wdt->base + REG_ENABLE); moxart_wdt_stop()
63 writel(moxart_wdt->clock_frequency * wdt_dev->timeout, moxart_wdt_start()
65 writel(0x5ab9, moxart_wdt->base + REG_MODE); moxart_wdt_start()
66 writel(0x03, moxart_wdt->base + REG_ENABLE); moxart_wdt_start()
H A Dqcom-wdt.c45 writel(0, wdt->base + WDT_EN); qcom_wdt_start()
46 writel(1, wdt->base + WDT_RST); qcom_wdt_start()
47 writel(wdd->timeout * wdt->rate, wdt->base + WDT_BITE_TIME); qcom_wdt_start()
48 writel(1, wdt->base + WDT_EN); qcom_wdt_start()
56 writel(0, wdt->base + WDT_EN); qcom_wdt_stop()
64 writel(1, wdt->base + WDT_RST); qcom_wdt_ping()
102 writel(0, wdt->base + WDT_EN); qcom_wdt_restart()
103 writel(1, wdt->base + WDT_RST); qcom_wdt_restart()
104 writel(timeout, wdt->base + WDT_BITE_TIME); qcom_wdt_restart()
105 writel(1, wdt->base + WDT_EN); qcom_wdt_restart()
/linux-4.4.14/drivers/input/keyboard/
H A Dbcm-keypad.c112 writel(0xFFFFFFFF, kp->base + KPICRN_OFFSET(reg_num)); bcm_kp_report_keys()
153 writel(kp->kpior, kp->base + KPIOR_OFFSET); bcm_kp_start()
155 writel(kp->imr0_val, kp->base + KPIMR0_OFFSET); bcm_kp_start()
156 writel(kp->imr1_val, kp->base + KPIMR1_OFFSET); bcm_kp_start()
158 writel(kp->kpemr, kp->base + KPEMR0_OFFSET); bcm_kp_start()
159 writel(kp->kpemr, kp->base + KPEMR1_OFFSET); bcm_kp_start()
160 writel(kp->kpemr, kp->base + KPEMR2_OFFSET); bcm_kp_start()
161 writel(kp->kpemr, kp->base + KPEMR3_OFFSET); bcm_kp_start()
163 writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET); bcm_kp_start()
164 writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET); bcm_kp_start()
169 writel(kp->kpcr | KPCR_ENABLE, kp->base + KPCR_OFFSET); bcm_kp_start()
180 writel(0, kp->base + KPCR_OFFSET); bcm_kp_stop()
181 writel(0, kp->base + KPIMR0_OFFSET); bcm_kp_stop()
182 writel(0, kp->base + KPIMR1_OFFSET); bcm_kp_stop()
183 writel(0xFFFFFFFF, kp->base + KPICR0_OFFSET); bcm_kp_stop()
184 writel(0xFFFFFFFF, kp->base + KPICR1_OFFSET); bcm_kp_stop()
H A Dlpc32xx-keys.c112 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); lpc32xx_kscan_irq()
128 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); lpc32xx_kscan_open()
137 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); lpc32xx_kscan_close()
252 writel(kscandat->deb_clks, LPC32XX_KS_DEB(kscandat->kscan_base)); lpc32xx_kscan_probe()
253 writel(kscandat->scan_delay, LPC32XX_KS_SCAN_CTL(kscandat->kscan_base)); lpc32xx_kscan_probe()
254 writel(LPC32XX_KSCAN_FTST_USE32K_CLK, lpc32xx_kscan_probe()
256 writel(kscandat->matrix_sz, lpc32xx_kscan_probe()
258 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); lpc32xx_kscan_probe()
290 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); lpc32xx_kscan_suspend()
311 writel(1, LPC32XX_KS_IRQ(kscandat->kscan_base)); lpc32xx_kscan_resume()
/linux-4.4.14/drivers/clk/rockchip/
H A Dsoftrst.c41 writel(BIT(offset) | (BIT(offset) << 16), rockchip_softrst_assert()
50 writel(reg | BIT(offset), softrst->reg_base + (bank * 4)); rockchip_softrst_assert()
68 writel((BIT(offset) << 16), softrst->reg_base + (bank * 4)); rockchip_softrst_deassert()
76 writel(reg & ~BIT(offset), softrst->reg_base + (bank * 4)); rockchip_softrst_deassert()
/linux-4.4.14/arch/ia64/include/asm/
H A Diosapic.h69 writel(reg, iosapic + IOSAPIC_REG_SELECT); __ia64_native_iosapic_read()
76 writel(reg, iosapic + IOSAPIC_REG_SELECT); __ia64_native_iosapic_write()
77 writel(val, iosapic + IOSAPIC_WINDOW); __ia64_native_iosapic_write()
82 writel(vector, iosapic + IOSAPIC_EOI); iosapic_eoi()
/linux-4.4.14/arch/arm/mach-rockchip/
H A Drockchip.c48 writel(0, reg_base + 0x30); rockchip_timer_init()
49 writel(0xffffffff, reg_base + 0x20); rockchip_timer_init()
50 writel(0xffffffff, reg_base + 0x24); rockchip_timer_init()
51 writel(1, reg_base + 0x30); rockchip_timer_init()
/linux-4.4.14/drivers/vlynq/
H A Dvlynq.c124 writel(readl(&dev->local->control) | VLYNQ_CTRL_RESET, vlynq_reset()
131 writel(readl(&dev->local->control) & ~VLYNQ_CTRL_RESET, vlynq_reset()
148 writel(val, &dev->remote->int_device[virq >> 2]); vlynq_irq_unmask()
161 writel(val, &dev->remote->int_device[virq >> 2]); vlynq_irq_mask()
191 writel(val, &dev->remote->int_device[virq >> 2]); vlynq_irq_type()
202 writel(status, &dev->local->status); vlynq_local_ack()
212 writel(status, &dev->remote->status); vlynq_remote_ack()
222 writel(status, &dev->local->int_status); vlynq_irq()
271 writel(readl(&dev->local->status), &dev->local->status); vlynq_setup_irq()
272 writel(readl(&dev->remote->status), &dev->remote->status); vlynq_setup_irq()
279 writel(VLYNQ_INT_OFFSET, &dev->local->int_ptr); vlynq_setup_irq()
280 writel(val, &dev->local->control); vlynq_setup_irq()
285 writel(VLYNQ_INT_OFFSET, &dev->remote->int_ptr); vlynq_setup_irq()
286 writel(val, &dev->remote->int_ptr); vlynq_setup_irq()
287 writel(val, &dev->remote->control); vlynq_setup_irq()
303 writel(0, &dev->remote->int_device[virq >> 2]); vlynq_setup_irq()
402 writel((readl(&dev->remote->control) & __vlynq_try_remote()
407 writel((readl(&dev->local->control) __vlynq_try_remote()
444 writel((readl(&dev->local->control) & __vlynq_try_local()
476 writel((readl(&dev->remote->control) & __vlynq_try_external()
480 writel((readl(&dev->local->control) & __vlynq_try_external()
531 writel(VLYNQ_CTRL_CLOCK_INT | __vlynq_enable_device()
534 writel(0, &dev->remote->control); __vlynq_enable_device()
551 writel(0, &dev->local->control); __vlynq_enable_device()
552 writel(VLYNQ_CTRL_CLOCK_INT | __vlynq_enable_device()
606 writel(tx_offset, &dev->local->tx_offset); vlynq_set_local_mapping()
608 writel(mapping[i].offset, &dev->local->rx_mapping[i].offset); vlynq_set_local_mapping()
609 writel(mapping[i].size, &dev->local->rx_mapping[i].size); vlynq_set_local_mapping()
623 writel(tx_offset, &dev->remote->tx_offset); vlynq_set_remote_mapping()
625 writel(mapping[i].offset, &dev->remote->rx_mapping[i].offset); vlynq_set_remote_mapping()
626 writel(mapping[i].size, &dev->remote->rx_mapping[i].size); vlynq_set_remote_mapping()
/linux-4.4.14/drivers/clk/
H A Dclk-highbank.c63 writel(reg, hbclk->reg); clk_pll_prepare()
80 writel(reg, hbclk->reg); clk_pll_unprepare()
90 writel(reg, hbclk->reg); clk_pll_enable()
102 writel(reg, hbclk->reg); clk_pll_disable()
170 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); clk_pll_set_rate()
172 writel(reg | HB_PLL_RESET, hbclk->reg); clk_pll_set_rate()
175 writel(reg | HB_PLL_RESET, hbclk->reg); clk_pll_set_rate()
176 writel(reg, hbclk->reg); clk_pll_set_rate()
185 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); clk_pll_set_rate()
188 writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg); clk_pll_set_rate()
190 writel(reg, hbclk->reg); clk_pll_set_rate()
265 writel(div >> 1, hbclk->reg); clk_periclk_set_rate()
/linux-4.4.14/lib/
H A Dstmp_device.c34 writel(mask, addr + STMP_OFFSET_REG_CLR); stmp_clear_poll_bit()
53 writel(STMP_MODULE_CLKGATE, reset_addr + STMP_OFFSET_REG_CLR); stmp_reset_block()
56 writel(STMP_MODULE_SFTRST, reset_addr + STMP_OFFSET_REG_SET); stmp_reset_block()
/linux-4.4.14/include/drm/
H A Ddrm_os_linux.h17 writel(val & 0xffffffff, reg); writeq()
18 writel(val >> 32, reg + 0x4UL); writeq()
36 #define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset))
/linux-4.4.14/arch/arm/mach-prima2/
H A Drstc.c44 writel(readl(sirfsoc_rstc_base + sirfsoc_reset_module()
48 writel(readl(sirfsoc_rstc_base + sirfsoc_reset_module()
70 writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base); sirfsoc_restart()
/linux-4.4.14/sound/arm/
H A Daaci.c54 writel(maincr, aaci->base + AACI_MAINCR); aaci_ac97_select_codec()
87 writel(val << 4, aaci->base + AACI_SL2TX); aaci_ac97_write()
88 writel(reg << 12, aaci->base + AACI_SL1TX); aaci_ac97_write()
126 writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX); aaci_ac97_read()
203 writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR); aaci_fifo_irq()
208 writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR); aaci_fifo_irq()
218 writel(0, aacirun->base + AACI_IE); aaci_fifo_irq()
268 writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR); aaci_fifo_irq()
278 writel(0, aacirun->base + AACI_IE); aaci_fifo_irq()
579 writel(ie, aacirun->base + AACI_IE); aaci_pcm_playback_stop()
582 writel(aacirun->cr, aacirun->base + AACI_TXCR); aaci_pcm_playback_stop()
594 writel(ie, aacirun->base + AACI_IE); aaci_pcm_playback_start()
595 writel(aacirun->cr, aacirun->base + AACI_TXCR); aaci_pcm_playback_start()
657 writel(ie, aacirun->base+AACI_IE); aaci_pcm_capture_stop()
661 writel(aacirun->cr, aacirun->base + AACI_RXCR); aaci_pcm_capture_stop()
676 writel(aacirun->cr, aacirun->base + AACI_RXCR); aaci_pcm_capture_start()
680 writel(ie, aacirun->base + AACI_IE); aaci_pcm_capture_start()
845 writel(0, aaci->base + AACI_RESET); aaci_probe_ac97()
847 writel(RESET_NRST, aaci->base + AACI_RESET); aaci_probe_ac97()
960 writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR); aaci_size_fifo()
963 writel(0, aacirun->fifo); aaci_size_fifo()
965 writel(0, aacirun->base + AACI_TXCR); aaci_size_fifo()
972 writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR); aaci_size_fifo()
975 writel(aaci->maincr, aaci->base + AACI_MAINCR); aaci_size_fifo()
1026 writel(0, base + AACI_IE); aaci_probe()
1027 writel(0, base + AACI_TXCR); aaci_probe()
1028 writel(0, base + AACI_RXCR); aaci_probe()
1031 writel(0x1fff, aaci->base + AACI_INTCLR); aaci_probe()
1032 writel(aaci->maincr, aaci->base + AACI_MAINCR); aaci_probe()
1079 writel(0, aaci->base + AACI_MAINCR); aaci_remove()
/linux-4.4.14/drivers/virtio/
H A Dvirtio_mmio.c121 writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); vm_get_features()
125 writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); vm_get_features()
145 writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); vm_finalize_features()
146 writel((u32)(vdev->features >> 32), vm_finalize_features()
149 writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); vm_finalize_features()
150 writel((u32)vdev->features, vm_finalize_features()
228 writel(le32_to_cpu(l), base + offset); vm_set()
232 writel(le32_to_cpu(l), base + offset); vm_set()
234 writel(le32_to_cpu(l), base + offset + sizeof l); vm_set()
265 writel(status, vm_dev->base + VIRTIO_MMIO_STATUS); vm_set_status()
273 writel(0, vm_dev->base + VIRTIO_MMIO_STATUS); vm_reset()
287 writel(vq->index, vm_dev->base + VIRTIO_MMIO_QUEUE_NOTIFY); vm_notify()
302 writel(status, vm_dev->base + VIRTIO_MMIO_INTERRUPT_ACK); vm_interrupt()
335 writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL); vm_del_vq()
337 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); vm_del_vq()
339 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY); vm_del_vq()
375 writel(index, vm_dev->base + VIRTIO_MMIO_QUEUE_SEL); vm_setup_vq()
432 writel(info->num, vm_dev->base + VIRTIO_MMIO_QUEUE_NUM); vm_setup_vq()
434 writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_QUEUE_ALIGN); vm_setup_vq()
435 writel(virt_to_phys(info->queue) >> PAGE_SHIFT, vm_setup_vq()
441 writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_LOW); vm_setup_vq()
442 writel((u32)(addr >> 32), vm_setup_vq()
446 writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_AVAIL_LOW); vm_setup_vq()
447 writel((u32)(addr >> 32), vm_setup_vq()
451 writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_USED_LOW); vm_setup_vq()
452 writel((u32)(addr >> 32), vm_setup_vq()
455 writel(1, vm_dev->base + VIRTIO_MMIO_QUEUE_READY); vm_setup_vq()
469 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN); vm_setup_vq()
471 writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_READY); vm_setup_vq()
586 writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_GUEST_PAGE_SIZE); virtio_mmio_probe()
/linux-4.4.14/drivers/media/platform/sti/c8sectpfe/
H A Dc8sectpfe-core.c130 writel(channel->back_buffer_busaddr, channel->irec + channel_swdemux_tsklet()
133 writel(wp, channel->irec + DMA_PRDS_BUSWP_TP(0)); channel_swdemux_tsklet()
186 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); c8sectpfe_start_feed()
215 writel(channel->fifo, c8sectpfe_start_feed()
217 writel(channel->fifo + FIFO_LEN - 1, c8sectpfe_start_feed()
220 writel(channel->fifo, c8sectpfe_start_feed()
222 writel(channel->fifo, c8sectpfe_start_feed()
227 writel(channel->back_buffer_busaddr, channel->irec + c8sectpfe_start_feed()
231 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0)); c8sectpfe_start_feed()
233 writel(channel->back_buffer_busaddr, channel->irec + c8sectpfe_start_feed()
237 writel(C8SECTPFE_SYS_ENABLE | C8SECTPFE_SYS_RESET c8sectpfe_start_feed()
241 writel(0x1, channel->irec + DMA_PRDS_TPENABLE); c8sectpfe_start_feed()
281 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(channel->tsin_id)); c8sectpfe_stop_feed()
299 writel(0, fei->io + C8SECTPFE_IB_SYS(channel->tsin_id)); c8sectpfe_stop_feed()
302 writel(0, channel->irec + DMA_PRDS_TPENABLE); c8sectpfe_stop_feed()
308 writel(idlereq, fei->io + DMA_IDLE_REQ); c8sectpfe_stop_feed()
323 writel(channel->back_buffer_busaddr, c8sectpfe_stop_feed()
327 writel(tmp, channel->irec + DMA_PRDS_BUSTOP_TP(0)); c8sectpfe_stop_feed()
329 writel(channel->back_buffer_busaddr, c8sectpfe_stop_feed()
419 writel(0, fei->io + DMA_IDLE_REQ); c8sectpfe_idle_irq_handler()
552 writel(tmp, fei->io + SYS_INPUT_CLKEN); configure_memdma_and_inputblock()
565 writel(tmp, fei->io + C8SECTPFE_IB_IP_FMT_CFG(tsin->tsin_id)); configure_memdma_and_inputblock()
567 writel(C8SECTPFE_SYNC(0x9) | configure_memdma_and_inputblock()
572 writel(TS_PKT_SIZE, fei->io + C8SECTPFE_IB_PKT_LEN(tsin->tsin_id)); configure_memdma_and_inputblock()
578 writel(tsin->fifo, fei->io + C8SECTPFE_IB_BUFF_STRT(tsin->tsin_id)); configure_memdma_and_inputblock()
579 writel(tsin->fifo + FIFO_LEN - 1, configure_memdma_and_inputblock()
582 writel(tsin->fifo, fei->io + C8SECTPFE_IB_READ_PNT(tsin->tsin_id)); configure_memdma_and_inputblock()
583 writel(tsin->fifo, fei->io + C8SECTPFE_IB_WRT_PNT(tsin->tsin_id)); configure_memdma_and_inputblock()
585 writel(tsin->pid_buffer_busaddr, configure_memdma_and_inputblock()
603 writel(tmp, fei->io + C8SECTPFE_IB_PID_SET(tsin->tsin_id)); configure_memdma_and_inputblock()
621 writel(tsin->fifo, tsin->irec + DMA_PRDS_MEMBASE); configure_memdma_and_inputblock()
623 writel(tsin->fifo + FIFO_LEN - 1, tsin->irec + DMA_PRDS_MEMTOP); configure_memdma_and_inputblock()
625 writel((188 + 7)&~7, tsin->irec + DMA_PRDS_PKTSIZE); configure_memdma_and_inputblock()
627 writel(0x1, tsin->irec + DMA_PRDS_TPENABLE); configure_memdma_and_inputblock()
631 writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSBASE_TP(0)); configure_memdma_and_inputblock()
634 writel(tmp, tsin->irec + DMA_PRDS_BUSTOP_TP(0)); configure_memdma_and_inputblock()
636 writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSWP_TP(0)); configure_memdma_and_inputblock()
637 writel(tsin->back_buffer_busaddr, tsin->irec + DMA_PRDS_BUSRP_TP(0)); configure_memdma_and_inputblock()
721 writel(0, fei->io + SYS_INPUT_CLKEN); c8sectpfe_probe()
724 writel(MEMDMAENABLE, fei->io + SYS_OTHER_CLKEN); c8sectpfe_probe()
922 writel(0x0, fei->io + DMA_CPU_RUN); c8sectpfe_remove()
926 writel(0, fei->io + SYS_INPUT_CLKEN); c8sectpfe_remove()
929 writel(0, fei->io + SYS_OTHER_CLKEN); c8sectpfe_remove()
1183 writel(0x1, fei->io + DMA_PER_STBUS_SYNC); load_c8sectpfe_fw_cb()
1186 writel(0x1, fei->io + DMA_CPU_RUN); load_c8sectpfe_fw_cb()
/linux-4.4.14/drivers/input/serio/
H A Dsun4i-ps2.c117 writel(rval, drvdata->reg_base + PS2_REG_LSTS); sun4i_ps2_interrupt()
124 writel(rval, drvdata->reg_base + PS2_REG_FSTS); sun4i_ps2_interrupt()
133 writel(intr_status, drvdata->reg_base + PS2_REG_LSTS); sun4i_ps2_interrupt()
134 writel(fifo_status, drvdata->reg_base + PS2_REG_FSTS); sun4i_ps2_interrupt()
153 writel(rval, drvdata->reg_base + PS2_REG_LCTL); sun4i_ps2_open()
160 writel(rval, drvdata->reg_base + PS2_REG_FCTL); sun4i_ps2_open()
167 writel(rval, drvdata->reg_base + PS2_REG_CLKDR); sun4i_ps2_open()
174 writel(rval, drvdata->reg_base + PS2_REG_GCTL); sun4i_ps2_open()
187 writel(rval & ~(PS2_GCTL_INTEN), drvdata->reg_base + PS2_REG_GCTL); sun4i_ps2_close()
199 writel(val, drvdata->reg_base + PS2_REG_DATA); sun4i_ps2_write()
263 writel(0, drvdata->reg_base + PS2_REG_GCTL); sun4i_ps2_probe()
/linux-4.4.14/drivers/pwm/
H A Dpwm-bcm2835.c50 writel(value, pc->base + PWM_CONTROL); bcm2835_pwm_request()
62 writel(value, pc->base + PWM_CONTROL); bcm2835_pwm_free()
76 writel(duty_ns / pc->scaler, pc->base + DUTY(pwm->hwpwm)); bcm2835_pwm_config()
77 writel(period_ns / pc->scaler, pc->base + PERIOD(pwm->hwpwm)); bcm2835_pwm_config()
89 writel(value, pc->base + PWM_CONTROL); bcm2835_pwm_enable()
101 writel(value, pc->base + PWM_CONTROL); bcm2835_pwm_disable()
117 writel(value, pc->base + PWM_CONTROL); bcm2835_set_polarity()
/linux-4.4.14/drivers/net/phy/
H A Dmdio-sun4i.c46 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); sun4i_mdio_read()
48 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_read()
59 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_read()
73 writel((mii_id << 8) | regnum, data->membase + EMAC_MAC_MADR_REG); sun4i_mdio_write()
75 writel(0x1, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_write()
86 writel(0x0, data->membase + EMAC_MAC_MCMD_REG); sun4i_mdio_write()
88 writel(value, data->membase + EMAC_MAC_MWTD_REG); sun4i_mdio_write()
/linux-4.4.14/drivers/clk/ingenic/
H A Djz4740-cgu.c247 writel(lcr, cgu->base + CGU_REG_LCR); jz4740_clock_set_wait_mode()
255 writel(clkgr, cgu->base + CGU_REG_CLKGR); jz4740_clock_udc_disable_auto_suspend()
264 writel(clkgr, cgu->base + CGU_REG_CLKGR); jz4740_clock_udc_enable_auto_suspend()
278 writel(clkgr, cgu->base + CGU_REG_CLKGR); jz4740_clock_suspend()
282 writel(cppcr, cgu->base + CGU_REG_CPPCR); jz4740_clock_suspend()
291 writel(cppcr, cgu->base + CGU_REG_CPPCR); jz4740_clock_resume()
302 writel(clkgr, cgu->base + CGU_REG_CLKGR); jz4740_clock_resume()
/linux-4.4.14/drivers/net/ethernet/alteon/
H A Dacenic.c614 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); acenic_remove_one()
616 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl); acenic_remove_one()
621 writel(1, &regs->Mb0Lo); acenic_remove_one()
853 writel(*(u32 *)(cmd), &regs->CmdRng[idx]); ace_issue_cmd()
856 writel(idx, &regs->CmdPrd); ace_issue_cmd()
883 writel(HW_RESET | (HW_RESET << 24), &regs->HostCtrl); ace_init()
895 writel((WORD_SWAP | CLR_INT | ((WORD_SWAP | CLR_INT) << 24)), ace_init()
898 writel((CLR_INT | WORD_SWAP | ((CLR_INT | WORD_SWAP) << 24)), ace_init()
906 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); ace_init()
908 writel(0, &regs->Mb0Lo); ace_init()
919 writel(0, &regs->LocalCtrl); ace_init()
928 writel(readl(&regs->CpuBCtrl) | CPU_HALT, &regs->CpuBCtrl); ace_init()
935 writel(SRAM_BANK_512K, &regs->LocalCtrl); ace_init()
936 writel(SYNC_SRAM_TIMING, &regs->MiscCfg); ace_init()
955 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ACE_BYTE_SWAP_BD | ace_init()
958 writel(ACE_BYTE_SWAP_DMA | ACE_WARN | ACE_FATAL | ace_init()
988 writel(mac1, &regs->MacAddrHi); ace_init()
989 writel(mac2, &regs->MacAddrLo); ace_init()
1107 writel(tmp, &regs->PciState); ace_init()
1186 writel(tmp_ptr >> 32, &regs->InfoPtrHi); ace_init()
1187 writel(tmp_ptr & 0xffffffff, &regs->InfoPtrLo); ace_init()
1197 writel(0, &regs->EvtCsm); ace_init()
1204 writel(0, &regs->CmdRng[i]); ace_init()
1206 writel(0, &regs->CmdPrd); ace_init()
1207 writel(0, &regs->CmdCsm); ace_init()
1283 writel(TX_RING_BASE, &regs->WinBase); ace_init()
1289 writel(0, (__force void __iomem *)ap->tx_ring + i * 4); ace_init()
1318 writel(DMA_THRESH_16W, &regs->DmaReadCfg); ace_init()
1319 writel(DMA_THRESH_16W, &regs->DmaWriteCfg); ace_init()
1321 writel(DMA_THRESH_8W, &regs->DmaReadCfg); ace_init()
1322 writel(DMA_THRESH_8W, &regs->DmaWriteCfg); ace_init()
1325 writel(0, &regs->MaskInt); ace_init()
1326 writel(1, &regs->IfIdx); ace_init()
1332 writel(1, &regs->AssistState); ace_init()
1335 writel(DEF_STAT, &regs->TuneStatTicks); ace_init()
1336 writel(DEF_TRACE, &regs->TuneTrace); ace_init()
1346 writel(tx_coal_tick[board_idx], ace_init()
1349 writel(max_tx_desc[board_idx], &regs->TuneMaxTxDesc); ace_init()
1352 writel(rx_coal_tick[board_idx], ace_init()
1355 writel(max_rx_desc[board_idx], &regs->TuneMaxRxDesc); ace_init()
1358 writel(trace[board_idx], &regs->TuneTrace); ace_init()
1361 writel(tx_ratio[board_idx], &regs->TxBufRat); ace_init()
1414 writel(tmp, &regs->TuneLink); ace_init()
1416 writel(tmp, &regs->TuneFastLink); ace_init()
1418 writel(ap->firmware_start, &regs->Pc); ace_init()
1420 writel(0, &regs->Mb0Lo); ace_init()
1433 writel(0, &regs->RxRetCsm); ace_init()
1441 writel(1, &regs->AssistState); /* enable DMA */ ace_init()
1446 writel(readl(&regs->CpuCtrl) & ~(CPU_HALT|CPU_TRACE), &regs->CpuCtrl); ace_init()
1460 writel(readl(&regs->CpuCtrl) | CPU_HALT, &regs->CpuCtrl); ace_init()
1473 writel(readl(&regs->CpuBCtrl) | CPU_HALT, ace_init()
1475 writel(0, &regs->Mb0Lo); ace_init()
1515 writel(DEF_TX_COAL, &regs->TuneTxCoalTicks); ace_set_rxtx_parms()
1517 writel(DEF_TX_MAX_DESC, &regs->TuneMaxTxDesc); ace_set_rxtx_parms()
1519 writel(DEF_RX_COAL, &regs->TuneRxCoalTicks); ace_set_rxtx_parms()
1521 writel(DEF_RX_MAX_DESC, &regs->TuneMaxRxDesc); ace_set_rxtx_parms()
1523 writel(DEF_TX_RATIO, &regs->TxBufRat); ace_set_rxtx_parms()
1526 writel(DEF_JUMBO_TX_COAL, ace_set_rxtx_parms()
1529 writel(DEF_JUMBO_TX_MAX_DESC, ace_set_rxtx_parms()
1532 writel(DEF_JUMBO_RX_COAL, ace_set_rxtx_parms()
1535 writel(DEF_JUMBO_RX_MAX_DESC, ace_set_rxtx_parms()
1538 writel(DEF_JUMBO_TX_RATIO, &regs->TxBufRat); ace_set_rxtx_parms()
1676 writel(idx, &regs->RxStdPrd); ace_load_std_rx_ring()
1731 writel(idx, &regs->RxMiniPrd); ace_load_mini_rx_ring()
1793 writel(idx, &regs->RxJumboPrd); ace_load_jumbo_rx_ring()
1896 writel(0, &((ap->regs)->RxJumboPrd)); ace_handle_event()
2027 writel(idx, &ap->regs->RxRetCsm); ace_rx_int()
2123 * writel(0, &regs->Mb0Lo). ace_interrupt()
2128 writel(0, &regs->Mb0Lo); ace_interrupt()
2164 writel(evtcsm, &regs->EvtCsm); ace_interrupt()
2241 writel(dev->mtu + ETH_HLEN + 4, &regs->IfMtu); ace_open()
2336 writel(0, &tx->addr.addrhi); ace_close()
2337 writel(0, &tx->addr.addrlo); ace_close()
2338 writel(0, &tx->flagsize); ace_close()
2396 writel(addr >> 32, &io->addr.addrhi); ace_load_tx_bd()
2397 writel(addr & 0xffffffff, &io->addr.addrlo); ace_load_tx_bd()
2398 writel(flagsize, &io->flagsize); ace_load_tx_bd()
2399 writel(vlan_tag, &io->vlanres); ace_load_tx_bd()
2554 writel(new_mtu + ETH_HLEN + 4, &regs->IfMtu); ace_change_mtu()
2685 writel(link, &regs->TuneLink); ace_set_settings()
2687 writel(link, &regs->TuneFastLink); ace_set_settings()
2732 writel(da[0] << 8 | da[1], &regs->MacAddrHi); ace_set_mac_addr()
2733 writel((da[2] << 24) | (da[3] << 16) | (da[4] << 8) | da[5], ace_set_mac_addr()
2827 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase); ace_copy()
2830 writel(be32_to_cpup(src), tdest); ace_copy()
2853 writel(dest & ~(ACE_WINDOW_SIZE - 1), &regs->WinBase); ace_clear()
2856 writel(0, tdest + i*4); ace_clear()
2959 writel(local, &regs->LocalCtrl); eeprom_start()
2964 writel(local, &regs->LocalCtrl); eeprom_start()
2969 writel(local, &regs->LocalCtrl); eeprom_start()
2974 writel(local, &regs->LocalCtrl); eeprom_start()
2989 writel(local, &regs->LocalCtrl); eeprom_prep()
2999 writel(local, &regs->LocalCtrl); eeprom_prep()
3005 writel(local, &regs->LocalCtrl); eeprom_prep()
3010 writel(local, &regs->LocalCtrl); eeprom_prep()
3024 writel(local, &regs->LocalCtrl); eeprom_check_ack()
3029 writel(local, &regs->LocalCtrl); eeprom_check_ack()
3037 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl); eeprom_check_ack()
3052 writel(local, &regs->LocalCtrl); eeprom_stop()
3057 writel(local, &regs->LocalCtrl); eeprom_stop()
3062 writel(local, &regs->LocalCtrl); eeprom_stop()
3067 writel(local, &regs->LocalCtrl); eeprom_stop()
3072 writel(local, &regs->LocalCtrl); eeprom_stop()
3136 writel(local, &regs->LocalCtrl); read_eeprom_byte()
3141 writel(local, &regs->LocalCtrl); read_eeprom_byte()
3152 writel(local, &regs->LocalCtrl); read_eeprom_byte()
3158 writel(local, &regs->LocalCtrl); read_eeprom_byte()
3166 writel(local, &regs->LocalCtrl); read_eeprom_byte()
3170 writel(readl(&regs->LocalCtrl) | EEPROM_CLK_OUT, &regs->LocalCtrl); read_eeprom_byte()
3173 writel(readl(&regs->LocalCtrl) & ~EEPROM_CLK_OUT, &regs->LocalCtrl); read_eeprom_byte()
/linux-4.4.14/drivers/usb/gadget/udc/
H A Dnet2280.h30 writel(index, &regs->idxaddr); get_idx_reg()
38 writel(index, &regs->idxaddr); set_idx_reg()
39 writel(value, &regs->idxdata); set_idx_reg()
120 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | allow_status()
134 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE), &ep->regs->ep_rsp); allow_status_338x()
196 writel(BIT(CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE) | set_halt()
206 writel(BIT(CLEAR_ENDPOINT_HALT) | clear_halt()
258 writel(BIT(GPIO3_LED_SELECT) | net2280_led_init()
287 writel(val, &dev->regs->gpioctl); net2280_led_speed()
300 writel(val, &dev->regs->gpioctl); net2280_led_active()
306 writel(readl(&dev->regs->gpioctl) & ~0x0f, net2280_led_shutdown()
344 writel(tmp | (count << EP_FIFO_BYTE_COUNT), &ep->cfg->ep_cfg); set_fifo_bytecount()
351 writel(BIT(SET_NAK_OUT_PACKETS), &ep->regs->ep_rsp); start_out_naking()
362 writel(BIT(CLEAR_NAK_OUT_PACKETS), &ep->regs->ep_rsp); stop_out_naking()
H A Damd5536udc.c283 writel(tmp, &dev->regs->irqmsk); udc_mask_unused_interrupts()
286 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk); udc_mask_unused_interrupts()
303 writel(tmp, &dev->regs->ep_irqmsk); udc_enable_ep0_interrupts()
324 writel(tmp, &dev->regs->irqmsk); udc_enable_dev_setup_interrupts()
401 writel(tmp, &dev->ep[ep->num].regs->ctl); udc_ep_enable()
408 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); udc_ep_enable()
424 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); udc_ep_enable()
432 writel(tmp, &ep->regs->ctl); udc_ep_enable()
443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); udc_ep_enable()
472 writel(tmp, &dev->csr->ne[udc_csr_epix]); udc_ep_enable()
477 writel(tmp, &dev->regs->ep_irqmsk); udc_ep_enable()
486 writel(tmp, &ep->regs->ctl); udc_ep_enable()
511 writel(tmp, &ep->regs->ctl); ep_init()
517 writel(tmp, &regs->ep_irqmsk); ep_init()
523 writel(tmp, &ep->regs->ctl); ep_init()
527 writel(tmp, &ep->regs->sts); ep_init()
532 writel(tmp, &ep->regs->ctl); ep_init()
536 writel(0, &ep->regs->desptr); ep_init()
722 writel(*(buf + i), ep->txfifo); udc_txfifo_write()
731 writel(0, &ep->regs->confirm); udc_txfifo_write()
1004 writel(tmp, &ep->regs->ctl); prep_dma()
1099 writel(tmp, &dev->regs->ctl); udc_set_rde()
1162 writel(tmp, &dev->regs->ctl); udc_queue()
1170 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); udc_queue()
1201 writel(tmp, &dev->regs->ctl); udc_queue()
1216 writel(req->td_phys, &ep->regs->desptr); udc_queue()
1222 writel(tmp, &ep->regs->ctl); udc_queue()
1231 writel(tmp, &dev->regs->ep_irqmsk); udc_queue()
1237 writel(tmp, &dev->regs->ep_irqmsk); udc_queue()
1332 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE), udc_dequeue()
1344 writel(ep->bna_dummy_req->td_phys, udc_dequeue()
1347 writel(tmp, &udc->regs->ctl); udc_dequeue()
1390 writel(tmp, &ep->regs->ctl); udc_set_halt()
1412 writel(tmp, &ep->regs->ctl); udc_set_halt()
1456 writel(tmp, &dev->regs->ctl); udc_remote_wakeup()
1458 writel(tmp, &dev->regs->ctl); udc_remote_wakeup()
1530 writel(tmp, &dev->regs->ctl); udc_basic_init()
1539 writel(tmp, &dev->regs->cfg); udc_basic_init()
1569 writel(tmp, &dev->regs->cfg); startup_registers()
1633 writel(reg, &dev->ep[tmp].regs->ctl); udc_setup_endpoints()
1740 writel(tmp, &dev->regs->cfg); udc_tasklet_disconnect()
1757 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts); udc_soft_reset()
1759 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts); udc_soft_reset()
1762 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); udc_soft_reset()
1784 writel(tmp, &udc->regs->ctl); udc_timer_function()
1837 writel(tmp, &ep->regs->ctl);*/ udc_handle_halt_state()
1841 writel(tmp, &ep->regs->ctl); udc_handle_halt_state()
1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); activate_control_endpoints()
1906 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); activate_control_endpoints()
1916 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); activate_control_endpoints()
1926 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); activate_control_endpoints()
1936 writel(tmp, &dev->csr->ne[0]); activate_control_endpoints()
1942 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma, activate_control_endpoints()
1944 writel(dev->ep[UDC_EP0OUT_IX].td_phys, activate_control_endpoints()
1963 writel(tmp, &dev->regs->ctl); activate_control_endpoints()
1969 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); activate_control_endpoints()
1976 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); activate_control_endpoints()
2015 writel(tmp, &dev->regs->ctl); amd5536_udc_start()
2056 writel(tmp, &dev->regs->ctl); amd5536_udc_stop()
2075 writel(reg, &dev->ep[tmp].regs->ctl); udc_process_cnak_queue()
2086 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl); udc_process_cnak_queue()
2141 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); udc_data_out_isr()
2155 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); udc_data_out_isr()
2272 writel(req->td_phys, udc_data_out_isr()
2285 writel(ep->bna_dummy_req->td_phys, udc_data_out_isr()
2329 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts); udc_data_out_isr()
2358 writel(epsts, &ep->regs->sts); udc_data_in_isr()
2370 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); udc_data_in_isr()
2409 writel(tmp, &dev->regs->ep_irqmsk); udc_data_in_isr()
2460 writel(req->td_phys, &ep->regs->desptr); udc_data_in_isr()
2472 writel(tmp, &ep->regs->ctl); udc_data_in_isr()
2481 writel(tmp, udc_data_in_isr()
2486 writel(epsts, &ep->regs->sts); udc_data_in_isr()
2509 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2515 writel(AMD_BIT(UDC_EPSTS_BNA),
2536 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2542 writel(UDC_EPSTS_OUT_CLEAR,
2571 writel(ep->bna_dummy_req->td_phys,
2622 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2629 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2638 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2645 writel(UDC_EPSTS_OUT_CLEAR,
2652 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2674 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2721 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts); udc_control_in_isr()
2730 writel(AMD_BIT(UDC_EPSTS_TDC), udc_control_in_isr()
2739 writel(AMD_BIT(UDC_EPSTS_IN), udc_control_in_isr()
2747 writel(tmp, &ep->regs->ctl); udc_control_in_isr()
2756 writel(req->td_phys, &ep->regs->desptr); udc_control_in_isr()
2768 writel(tmp, udc_control_in_isr()
2800 writel(AMD_BIT(UDC_EPSTS_IN), udc_control_in_isr()
2857 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2863 writel(tmp, &ep->regs->ctl);
2916 writel(tmp, &dev->csr->ne[udc_csr_epix]);
2922 writel(tmp, &ep->regs->ctl);
2972 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2973 writel(tmp, &dev->regs->cfg);
2984 writel(tmp, &dev->regs->irqmsk);
3028 writel(tmp, &dev->regs->irqmsk);
3068 writel(ep_irq, &dev->regs->ep_irqsts); udc_irq()
3084 writel(reg, &dev->regs->irqsts); udc_irq()
3145 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); udc_pci_remove()
3275 writel(reg, &dev->regs->ctl); udc_probe()
/linux-4.4.14/drivers/input/touchscreen/
H A Dimx6ul_tsc.c111 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); imx6ul_adc_init()
116 writel(adc_hc, tsc->adc_regs + REG_ADC_HC0); imx6ul_adc_init()
121 writel(adc_gc, tsc->adc_regs + REG_ADC_GC); imx6ul_adc_init()
139 writel(adc_cfg, tsc->adc_regs + REG_ADC_CFG); imx6ul_adc_init()
154 writel(adc_hc0, tsc->adc_regs + REG_ADC_HC0); imx6ul_tsc_channel_config()
157 writel(adc_hc1, tsc->adc_regs + REG_ADC_HC1); imx6ul_tsc_channel_config()
160 writel(adc_hc2, tsc->adc_regs + REG_ADC_HC2); imx6ul_tsc_channel_config()
163 writel(adc_hc3, tsc->adc_regs + REG_ADC_HC3); imx6ul_tsc_channel_config()
166 writel(adc_hc4, tsc->adc_regs + REG_ADC_HC4); imx6ul_tsc_channel_config()
181 writel(basic_setting, tsc->tsc_regs + REG_TSC_BASIC_SETING); imx6ul_tsc_set()
183 writel(DE_GLITCH_2, tsc->tsc_regs + REG_TSC_DEBUG_MODE2); imx6ul_tsc_set()
185 writel(tsc->pre_charge_time, tsc->tsc_regs + REG_TSC_PRE_CHARGE_TIME); imx6ul_tsc_set()
186 writel(MEASURE_INT_EN, tsc->tsc_regs + REG_TSC_INT_EN); imx6ul_tsc_set()
187 writel(MEASURE_SIG_EN | VALID_SIG_EN, imx6ul_tsc_set()
194 writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL); imx6ul_tsc_set()
218 writel(tsc_flow, tsc->tsc_regs + REG_TSC_FLOW_CONTROL); imx6ul_tsc_disable()
223 writel(adc_cfg, tsc->adc_regs + REG_ADC_HC0); imx6ul_tsc_disable()
257 writel(MEASURE_SIGNAL | DETECT_SIGNAL, tsc_irq_fn()
263 writel(start, tsc->tsc_regs + REG_TSC_FLOW_CONTROL); tsc_irq_fn()
/linux-4.4.14/drivers/net/ethernet/natsemi/
H A Dns83820.c469 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
477 writel(dev->rx_info.phy_descs + kick_rx()
634 writel(readl(dev->base + TXCFG) phy_intr()
637 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, phy_intr()
640 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, phy_intr()
651 writel((readl(dev->base + TXCFG) phy_intr()
654 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, phy_intr()
657 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, phy_intr()
677 writel(readl(dev->base + TXCFG) phy_intr()
680 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, phy_intr()
683 writel(readl(dev->base + TXCFG) phy_intr()
686 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), phy_intr()
692 writel(new_cfg, dev->base + CFG); phy_intr()
735 writel(0, dev->base + RXDP_HI); ns83820_setup_rx()
736 writel(dev->rx_info.phy_descs, dev->base + RXDP); ns83820_setup_rx()
744 writel(0x0001, dev->base + CCSR); ns83820_setup_rx()
745 writel(0, dev->base + RFCR); ns83820_setup_rx()
746 writel(0x7fc00000, dev->base + RFCR); ns83820_setup_rx()
747 writel(0xffc00000, dev->base + RFCR); ns83820_setup_rx()
766 writel(dev->IMR_cache, dev->base + IMR); ns83820_setup_rx()
767 writel(1, dev->base + IER); ns83820_setup_rx()
787 writel(dev->IMR_cache, dev->base + IMR); ns83820_cleanup_rx()
798 writel(0, dev->base + RXDP_HI); ns83820_cleanup_rx()
799 writel(0, dev->base + RXDP); ns83820_cleanup_rx()
945 writel(ihr, dev->base + IHR); rx_action()
949 writel(dev->IMR_cache, dev->base + IMR); rx_action()
962 writel(CR_TXE, dev->base + CR); kick_tx()
1314 writel(readl(dev->base + TXCFG) ns83820_set_settings()
1317 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, ns83820_set_settings()
1320 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, ns83820_set_settings()
1338 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, ns83820_set_settings()
1340 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); ns83820_set_settings()
1347 writel(0x00000000, dev->base + TBICR); ns83820_set_settings()
1386 writel(0, dev->base + IMR); ns83820_disable_interrupts()
1387 writel(0, dev->base + IER); ns83820_disable_interrupts()
1437 writel(dev->IMR_cache, dev->base + IMR); ns83820_do_isr()
1442 //writel(4, dev->base + IHR); ns83820_do_isr()
1459 writel(CR_RXE, dev->base + CR); ns83820_do_isr()
1494 writel(dev->IMR_cache, dev->base + IMR); ns83820_do_isr()
1508 writel(dev->IMR_cache, dev->base + IMR); ns83820_do_isr()
1522 writel(dev->ihr, dev->base + IHR); ns83820_do_isr()
1529 writel(which, dev->base + CR); ns83820_do_reset()
1631 writel(0, dev->base + PQCR); ns83820_open()
1648 writel(0, dev->base + TXDP_HI); ns83820_open()
1649 writel(desc, dev->base + TXDP); ns83820_open()
1674 writel(i*2, dev->base + RFCR); ns83820_getmac()
1711 writel(val & ~RFCR_RFEN, rfcr); ns83820_set_multicast()
1712 writel(val, rfcr); ns83820_set_multicast()
1728 writel(enable, dev->base + PTSCR); ns83820_run_bist()
1760 writel(dev->MEAR_cache, dev->base + MEAR); ns83820_mii_write_bit()
1771 writel(dev->MEAR_cache, dev->base + MEAR); ns83820_mii_write_bit()
1779 writel(dev->MEAR_cache, dev->base + MEAR); ns83820_mii_write_bit()
1793 writel(dev->MEAR_cache, dev->base + MEAR); ns83820_mii_read_bit()
1802 writel(dev->MEAR_cache, dev->base + MEAR); ns83820_mii_read_bit()
2040 writel(PTSCR_RBIST_RST, dev->base + PTSCR); ns83820_init_one()
2084 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR); ns83820_init_one()
2087 writel(readl(dev->base + TANAR) ns83820_init_one()
2092 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, ns83820_init_one()
2094 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); ns83820_init_one()
2100 writel(dev->CFG_cache, dev->base + CFG); ns83820_init_one()
2105 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); ns83820_init_one()
2107 writel(dev->CFG_cache, dev->base + CFG); ns83820_init_one()
2114 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c); ns83820_init_one()
2124 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 ns83820_init_one()
2129 writel(0x000, dev->base + IHR); ns83820_init_one()
2130 writel(0x100, dev->base + IHR); ns83820_init_one()
2131 writel(0x000, dev->base + IHR); ns83820_init_one()
2139 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD ns83820_init_one()
2145 writel(0, dev->base + PQCR); ns83820_init_one()
2165 writel(VRCR_INIT_VALUE, dev->base + VRCR); ns83820_init_one()
2176 writel(VTCR_INIT_VALUE, dev->base + VTCR); ns83820_init_one()
2179 /* writel(0, dev->base + PCR); */ ns83820_init_one()
2180 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | ns83820_init_one()
2185 writel(0, dev->base + WCSR); ns83820_init_one()
/linux-4.4.14/drivers/staging/comedi/drivers/
H A Dmite.c122 writel(0, mite->mite_io_addr + MITE_IODWBSR); mite_setup2()
125 writel(mite->daq_phys_addr | WENAB | mite_setup2()
128 writel(0, mite->mite_io_addr + MITE_IODWCR_1); mite_setup2()
130 writel(mite->daq_phys_addr | WENAB, mite_setup2()
143 writel(unknown_dma_burst_bits, mite_setup2()
156 writel(CHOR_DMARESET, mite->mite_io_addr + MITE_CHOR(i)); mite_setup2()
158 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE | mite_setup2()
258 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | mite_release_channel()
286 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); mite_dma_arm()
357 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); mite_prep_dma()
384 writel(chcr, mite->mite_io_addr + MITE_CHCR(mite_chan->channel)); mite_prep_dma()
402 writel(mcr, mite->mite_io_addr + MITE_MCR(mite_chan->channel)); mite_prep_dma()
421 writel(dcr, mite->mite_io_addr + MITE_DCR(mite_chan->channel)); mite_prep_dma()
424 writel(0, mite->mite_io_addr + MITE_DAR(mite_chan->channel)); mite_prep_dma()
428 writel(lkcr, mite->mite_io_addr + MITE_LKCR(mite_chan->channel)); mite_prep_dma()
431 writel(mite_chan->ring->descriptors_dma_addr, mite_prep_dma()
507 writel(chor, mite->mite_io_addr + MITE_CHOR(mite_chan->channel)); mite_dma_disarm()
591 writel(CHOR_CLRDONE, mite_get_status()
/linux-4.4.14/drivers/media/rc/
H A Dsunxi-cir.c113 writel(status | REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); sunxi_ir_irq()
261 writel(REG_CTL_MD, ir->base+SUNXI_IR_CTL_REG); sunxi_ir_probe()
264 writel(REG_CIR_NTHR(SUNXI_IR_RXNOISE)|REG_CIR_ITHR(SUNXI_IR_RXIDLE), sunxi_ir_probe()
268 writel(REG_RXCTL_RPPI, ir->base + SUNXI_IR_RXCTL_REG); sunxi_ir_probe()
271 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); sunxi_ir_probe()
277 writel(REG_RXINT_ROI_EN | REG_RXINT_RPEI_EN | sunxi_ir_probe()
283 writel(tmp | REG_CTL_GEN | REG_CTL_RXEN, ir->base + SUNXI_IR_CTL_REG); sunxi_ir_probe()
313 writel(0, ir->base + SUNXI_IR_RXINT_REG); sunxi_ir_remove()
315 writel(REG_RXSTA_CLEARALL, ir->base + SUNXI_IR_RXSTA_REG); sunxi_ir_remove()
317 writel(0, ir->base + SUNXI_IR_CTL_REG); sunxi_ir_remove()
H A Dst_rc.c115 writel(IRB_RX_OVERRUN_INT, st_rc_rx_interrupt()
153 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR); st_rc_rx_interrupt()
174 writel(1, dev->rx_base + IRB_RX_POLARITY_INV); st_rc_hardware_init()
177 writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM); st_rc_hardware_init()
187 writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD); st_rc_hardware_init()
204 writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN); st_rc_open()
205 writel(0x01, dev->rx_base + IRB_RX_EN); st_rc_open()
215 writel(0x00, dev->rx_base + IRB_RX_EN); st_rc_close()
216 writel(0x00, dev->rx_base + IRB_RX_INT_EN); st_rc_close()
349 writel(0x00, rc_dev->rx_base + IRB_RX_EN); st_rc_suspend()
350 writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN); st_rc_suspend()
371 writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN); st_rc_resume()
372 writel(0x01, rc_dev->rx_base + IRB_RX_EN); st_rc_resume()
/linux-4.4.14/drivers/mfd/
H A Dipaq-micro.c62 writel(val, micro->base + UTCR3); ipaq_micro_trigger_tx()
296 writel(tx->buf[tx->index], micro->base + UTDR); micro_tx_chars()
303 writel(val, micro->base + UTCR3); micro_tx_chars()
318 writel(0x01, micro->sdlc + 0x0); /* Select UART mode */ micro_reset_comm()
321 writel(0x0, micro->base + UTCR3); micro_reset_comm()
324 writel(UTCR0_8BitData | UTCR0_1StpBit, micro->base + UTCR0); micro_reset_comm()
327 writel(0x0, micro->base + UTCR1); micro_reset_comm()
328 writel(0x1, micro->base + UTCR2); micro_reset_comm()
331 writel(0xff, micro->base + UTSR0); micro_reset_comm()
334 writel(UTCR3_TXE | UTCR3_RXE | UTCR3_RIE, micro->base + UTCR3); micro_reset_comm()
337 writel(val, micro->base + UTCR3); micro_reset_comm()
351 writel(UTSR0_RID, micro->base + UTSR0); micro_serial_isr()
357 writel(status & (UTSR0_RBB | UTSR0_REB), micro_serial_isr()
/linux-4.4.14/drivers/scsi/
H A Dhptiop.c67 writel(req, &hba->u.itl.iop->outbound_queue); iop_wait_ready_itl()
113 writel(1, &p->context); hptiop_drain_outbound_queue_itl()
129 writel(1, plx + 0x11C60); iop_intr_itl()
137 writel(IOPMU_OUTBOUND_INT_MSG0, &iop->outbound_intstatus); iop_intr_itl()
163 writel(outbound_tail, &mu->outbound_tail); mv_outbound_read()
178 writel(head, &hba->u.mv.mu->inbound_head); mv_inbound_write()
179 writel(MVIOP_MU_INBOUND_INT_POSTQUEUE, mv_inbound_write()
217 writel(~status, &hba->u.mv.regs->outbound_doorbell); iop_intr_mv()
267 writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); iop_intr_mvfrey()
271 writel(status, &(hba->u.mvfrey.mu->f0_doorbell)); iop_intr_mvfrey()
282 writel(status, &(hba->u.mvfrey.mu->isr_cause)); iop_intr_mvfrey()
301 writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); iop_intr_mvfrey()
312 writel(readl(&req->flags) | IOP_REQUEST_FLAG_SYNC_REQUEST, &req->flags); iop_send_sync_request_itl()
313 writel(0, &req->context); iop_send_sync_request_itl()
314 writel((unsigned long)req - (unsigned long)hba->u.itl.iop, iop_send_sync_request_itl()
370 writel(msg, &hba->u.itl.iop->inbound_msgaddr0); hptiop_post_msg_itl()
376 writel(msg, &hba->u.mv.mu->inbound_msg); hptiop_post_msg_mv()
377 writel(MVIOP_MU_INBOUND_INT_MSG, &hba->u.mv.regs->inbound_doorbell); hptiop_post_msg_mv()
383 writel(msg, &(hba->u.mvfrey.mu->f0_to_cpu_msg_a)); hptiop_post_msg_mvfrey()
421 writel(0, &req->header.flags); iop_get_config_itl()
422 writel(IOP_REQUEST_TYPE_GET_CONFIG, &req->header.type); iop_get_config_itl()
423 writel(sizeof(struct hpt_iop_request_get_config), &req->header.size); iop_get_config_itl()
424 writel(IOP_RESULT_PENDING, &req->header.result); iop_get_config_itl()
432 writel(req32, &hba->u.itl.iop->outbound_queue); iop_get_config_itl()
498 writel(0, &req->header.flags); iop_set_config_itl()
499 writel(IOP_REQUEST_TYPE_SET_CONFIG, &req->header.type); iop_set_config_itl()
500 writel(sizeof(struct hpt_iop_request_set_config), &req->header.size); iop_set_config_itl()
501 writel(IOP_RESULT_PENDING, &req->header.result); iop_set_config_itl()
508 writel(req32, &hba->u.itl.iop->outbound_queue); iop_set_config_itl()
559 writel(~(IOPMU_OUTBOUND_INT_POSTQUEUE | IOPMU_OUTBOUND_INT_MSG0), hptiop_enable_intr_itl()
565 writel(MVIOP_MU_OUTBOUND_INT_POSTQUEUE | MVIOP_MU_OUTBOUND_INT_MSG, hptiop_enable_intr_mv()
571 writel(CPU_TO_F0_DRBL_MSG_BIT, &(hba->u.mvfrey.mu->f0_doorbell_enable)); hptiop_enable_intr_mvfrey()
572 writel(0x1, &(hba->u.mvfrey.mu->isr_enable)); hptiop_enable_intr_mvfrey()
573 writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); hptiop_enable_intr_mvfrey()
839 writel(tag, &hba->u.itl.iop->outbound_queue); hptiop_iop_request_callback_itl()
902 writel(_req->req_shifted_phy | size_bits, hptiop_post_req_itl()
905 writel(_req->req_shifted_phy | IOPMU_QUEUE_ADDR_HOST_BIT, hptiop_post_req_itl()
959 writel(hba->u.mvfrey.inlist_wptr, hptiop_post_req_mvfrey()
984 writel(cpu_to_le32(hba->u.mvfrey.inlist_phy & 0xffffffff), hptiop_reset_comm_mvfrey()
986 writel(cpu_to_le32((hba->u.mvfrey.inlist_phy >> 16) >> 16), hptiop_reset_comm_mvfrey()
989 writel(cpu_to_le32(hba->u.mvfrey.outlist_phy & 0xffffffff), hptiop_reset_comm_mvfrey()
991 writel(cpu_to_le32((hba->u.mvfrey.outlist_phy >> 16) >> 16), hptiop_reset_comm_mvfrey()
994 writel(cpu_to_le32(hba->u.mvfrey.outlist_cptr_phy & 0xffffffff), hptiop_reset_comm_mvfrey()
996 writel(cpu_to_le32((hba->u.mvfrey.outlist_cptr_phy >> 16) >> 16), hptiop_reset_comm_mvfrey()
1536 writel(int_mask | hptiop_disable_intr_itl()
1544 writel(0, &hba->u.mv.regs->outbound_intmask); hptiop_disable_intr_mv()
1550 writel(0, &(hba->u.mvfrey.mu->f0_doorbell_enable)); hptiop_disable_intr_mvfrey()
1552 writel(0, &(hba->u.mvfrey.mu->isr_enable)); hptiop_disable_intr_mvfrey()
1554 writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable)); hptiop_disable_intr_mvfrey()
/linux-4.4.14/drivers/nvmem/
H A Drockchip-efuse.c67 writel(EFUSE_LOAD | EFUSE_PGENB, base + REG_EFUSE_CTRL); rockchip_efuse_read()
70 writel(readl(base + REG_EFUSE_CTRL) & rockchip_efuse_read()
73 writel(readl(base + REG_EFUSE_CTRL) | rockchip_efuse_read()
77 writel(readl(base + REG_EFUSE_CTRL) | rockchip_efuse_read()
81 writel(readl(base + REG_EFUSE_CTRL) & rockchip_efuse_read()
90 writel(EFUSE_PGENB | EFUSE_CSB, base + REG_EFUSE_CTRL); rockchip_efuse_read()
/linux-4.4.14/drivers/clk/mvebu/
H A Dclk-cpu.c88 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); clk_cpu_off_set_rate()
94 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_off_set_rate()
99 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_off_set_rate()
104 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_off_set_rate()
143 writel(reg, cpuclk->pmu_dfs); clk_cpu_on_set_rate()
148 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET); clk_cpu_on_set_rate()
/linux-4.4.14/arch/arm/mach-omap1/
H A Dtime.c82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl); omap_mpu_set_autoreset()
89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl); omap_mpu_remove_autoreset()
101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl); omap_mpu_timer_start()
103 writel(load_val, &timer->load_tim); omap_mpu_timer_start()
105 writel(timerflags, &timer->cntl); omap_mpu_timer_start()
112 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl); omap_mpu_timer_stop()
/linux-4.4.14/sound/soc/davinci/
H A Ddavinci-vcif.c71 writel(w, davinci_vc->base + DAVINCI_VC_CTRL); davinci_vcif_start()
89 writel(w, davinci_vc->base + DAVINCI_VC_CTRL); davinci_vcif_stop()
105 writel(DAVINCI_VC_CTRL_MASK, davinci_vc->base + DAVINCI_VC_CTRL); davinci_vcif_hw_params()
107 writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTCLR); davinci_vcif_hw_params()
109 writel(DAVINCI_VC_INT_MASK, davinci_vc->base + DAVINCI_VC_INTEN); davinci_vcif_hw_params()
139 writel(w, davinci_vc->base + DAVINCI_VC_CTRL); davinci_vcif_hw_params()

Completed in 6398 milliseconds

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