519 	writel(reg | XGMAC_OMR_FTF, ioaddr + XGMAC_OMR);  in xgmac_dma_flush_tx_fifo()
602 	writel(value, ioaddr + XGMAC_CONTROL);  in xgmac_mac_enable()
606 	writel(value, ioaddr + XGMAC_DMA_CONTROL);  in xgmac_mac_enable()
613 	writel(value, ioaddr + XGMAC_DMA_CONTROL);  in xgmac_mac_disable()
617 	writel(value, ioaddr + XGMAC_CONTROL);  in xgmac_mac_disable()
627 		writel(data, ioaddr + XGMAC_ADDR_HIGH(num));  in xgmac_set_mac_addr()
629 		writel(data, ioaddr + XGMAC_ADDR_LOW(num));  in xgmac_set_mac_addr()
631 		writel(0, ioaddr + XGMAC_ADDR_HIGH(num));  in xgmac_set_mac_addr()
632 		writel(0, ioaddr + XGMAC_ADDR_LOW(num));  in xgmac_set_mac_addr()
671 		writel(flow, priv->base + XGMAC_FLOW_CTRL);  in xgmac_set_flow_ctrl()
675 		writel(reg, priv->base + XGMAC_OMR);  in xgmac_set_flow_ctrl()
677 		writel(0, priv->base + XGMAC_FLOW_CTRL);  in xgmac_set_flow_ctrl()
681 		writel(reg, priv->base + XGMAC_OMR);  in xgmac_set_flow_ctrl()
783 	writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);  in xgmac_dma_desc_rings_init()
784 	writel(priv->dma_rx_phy, priv->base + XGMAC_DMA_RX_BASE_ADDR);  in xgmac_dma_desc_rings_init()
922 	writel(0, priv->base + XGMAC_DMA_INTR_ENA);  in xgmac_tx_timeout_work()
927 	writel(reg & ~DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);  in xgmac_tx_timeout_work()
936 	writel(priv->dma_tx_phy, priv->base + XGMAC_DMA_TX_BASE_ADDR);  in xgmac_tx_timeout_work()
937 	writel(reg | DMA_CONTROL_ST, priv->base + XGMAC_DMA_CONTROL);  in xgmac_tx_timeout_work()
939 	writel(DMA_STATUS_TU | DMA_STATUS_TPS | DMA_STATUS_NIS | DMA_STATUS_AIS,  in xgmac_tx_timeout_work()
948 	writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_STATUS);  in xgmac_tx_timeout_work()
949 	writel(DMA_INTR_DEFAULT_MASK, priv->base + XGMAC_DMA_INTR_ENA);  in xgmac_tx_timeout_work()
964 	writel(value, ioaddr + XGMAC_DMA_BUS_MODE);  in xgmac_hw_init()
975 	writel(value, ioaddr + XGMAC_DMA_BUS_MODE);  in xgmac_hw_init()
977 	writel(0, ioaddr + XGMAC_DMA_INTR_ENA);  in xgmac_hw_init()
980 	writel(XGMAC_INT_STAT_PMTIM, ioaddr + XGMAC_INT_STAT);  in xgmac_hw_init()
983 	writel(0x0077000E, ioaddr + XGMAC_DMA_AXI_BUS);  in xgmac_hw_init()
989 	writel(ctrl, ioaddr + XGMAC_CONTROL);  in xgmac_hw_init()
991 	writel(DMA_CONTROL_OSF, ioaddr + XGMAC_DMA_CONTROL);  in xgmac_hw_init()
994 	writel(XGMAC_OMR_TSF | XGMAC_OMR_RFD | XGMAC_OMR_RFA |  in xgmac_hw_init()
999 	writel(1, ioaddr + XGMAC_MMC_CTRL);  in xgmac_hw_init()
1046 	writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);  in xgmac_open()
1047 	writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);  in xgmac_open()
1065 	writel(0, priv->base + XGMAC_DMA_INTR_ENA);  in xgmac_stop()
1144 	writel(1, priv->base + XGMAC_DMA_TX_POLL);  in xgmac_xmit()
1345 		writel(hash_filter[i], ioaddr + XGMAC_HASH(i));  in xgmac_set_rx_mode()
1347 	writel(value, ioaddr + XGMAC_FRAME_FILTER);  in xgmac_set_rx_mode()
1472 	writel(XGMAC_MMC_CTRL_CNT_FRZ, base + XGMAC_MMC_CTRL);  in xgmac_get_stats64()
1491 	writel(0, base + XGMAC_MMC_CTRL);  in xgmac_get_stats64()
1527 	writel(ctrl, ioaddr + XGMAC_CONTROL);  in xgmac_set_features()
1759 	writel(1, priv->base + XGMAC_ADDR_HIGH(31));  in xgmac_probe()
1765 	writel(0, priv->base + XGMAC_DMA_INTR_ENA);  in xgmac_probe()
1875 	writel(pmt, ioaddr + XGMAC_PMT);  in xgmac_pmt()
1889 	writel(0, priv->base + XGMAC_DMA_INTR_ENA);  in xgmac_suspend()
1895 		writel(value, priv->base + XGMAC_DMA_CONTROL);  in xgmac_suspend()
1917 	writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_STATUS);  in xgmac_resume()
1918 	writel(DMA_INTR_DEFAULT_MASK, ioaddr + XGMAC_DMA_INTR_ENA);  in xgmac_resume()