237 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));  in u300_gpio_set()
239 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));  in u300_gpio_set()
254 	writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_direction_input()
281 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_direction_output()
360 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));  in u300_gpio_config_set()
364 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));  in u300_gpio_config_set()
372 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_config_set()
380 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_config_set()
388 		writel(val, U300_PIN_REG(offset, pcr));  in u300_gpio_config_set()
418 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_toggle_trigger()
423 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_toggle_trigger()
453 		writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_gpio_irq_type()
459 		writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));  in u300_gpio_irq_type()
479 	writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));  in u300_gpio_irq_enable()
493 	writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));  in u300_gpio_irq_disable()
521 	writel(val, U300_PIN_REG(pinoffset, iev));  in u300_gpio_irq_handler()
680 	writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,  in u300_gpio_probe()
719 		writel(0x0, gpio->base + portno * gpio->stride + ifr);  in u300_gpio_probe()
754 	writel(0x00000000U, gpio->base + U300_GPIO_CR);  in u300_gpio_remove()