1/* 2 * U300 GPIO module. 3 * 4 * Copyright (C) 2007-2012 ST-Ericsson AB 5 * License terms: GNU General Public License (GPL) version 2 6 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0) 7 * Author: Linus Walleij <linus.walleij@linaro.org> 8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 9 */ 10#include <linux/module.h> 11#include <linux/interrupt.h> 12#include <linux/delay.h> 13#include <linux/errno.h> 14#include <linux/io.h> 15#include <linux/clk.h> 16#include <linux/err.h> 17#include <linux/platform_device.h> 18#include <linux/gpio.h> 19#include <linux/slab.h> 20#include <linux/pinctrl/consumer.h> 21#include <linux/pinctrl/pinconf-generic.h> 22#include "pinctrl-coh901.h" 23 24#define U300_GPIO_PORT_STRIDE (0x30) 25/* 26 * Control Register 32bit (R/W) 27 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores 28 * gives the number of GPIO pins. 29 * bit 8-2 (mask 0x000001FC) contains the core version ID. 30 */ 31#define U300_GPIO_CR (0x00) 32#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL) 33#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL) 34#define U300_GPIO_PXPDIR (0x04) 35#define U300_GPIO_PXPDOR (0x08) 36#define U300_GPIO_PXPCR (0x0C) 37#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL) 38#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL) 39#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL) 40#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL) 41#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL) 42#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL) 43#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL) 44#define U300_GPIO_PXPER (0x10) 45#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL) 46#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL) 47#define U300_GPIO_PXIEV (0x14) 48#define U300_GPIO_PXIEN (0x18) 49#define U300_GPIO_PXIFR (0x1C) 50#define U300_GPIO_PXICR (0x20) 51#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL) 52#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL) 53#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL) 54#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL) 55 56/* 8 bits per port, no version has more than 7 ports */ 57#define U300_GPIO_NUM_PORTS 7 58#define U300_GPIO_PINS_PER_PORT 8 59#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS) 60 61struct u300_gpio_port { 62 struct u300_gpio *gpio; 63 char name[8]; 64 int irq; 65 int number; 66 u8 toggle_edge_mode; 67}; 68 69struct u300_gpio { 70 struct gpio_chip chip; 71 struct u300_gpio_port ports[U300_GPIO_NUM_PORTS]; 72 struct clk *clk; 73 void __iomem *base; 74 struct device *dev; 75 u32 stride; 76 /* Register offsets */ 77 u32 pcr; 78 u32 dor; 79 u32 dir; 80 u32 per; 81 u32 icr; 82 u32 ien; 83 u32 iev; 84}; 85 86/* 87 * Macro to expand to read a specific register found in the "gpio" 88 * struct. It requires the struct u300_gpio *gpio variable to exist in 89 * its context. It calculates the port offset from the given pin 90 * offset, muliplies by the port stride and adds the register offset 91 * so it provides a pointer to the desired register. 92 */ 93#define U300_PIN_REG(pin, reg) \ 94 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg) 95 96/* 97 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO 98 * register. 99 */ 100#define U300_PIN_BIT(pin) \ 101 (1 << (pin & 0x07)) 102 103struct u300_gpio_confdata { 104 u16 bias_mode; 105 bool output; 106 int outval; 107}; 108 109#define U300_FLOATING_INPUT { \ 110 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \ 111 .output = false, \ 112} 113 114#define U300_PULL_UP_INPUT { \ 115 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \ 116 .output = false, \ 117} 118 119#define U300_OUTPUT_LOW { \ 120 .output = true, \ 121 .outval = 0, \ 122} 123 124#define U300_OUTPUT_HIGH { \ 125 .output = true, \ 126 .outval = 1, \ 127} 128 129/* Initial configuration */ 130static const struct __initconst u300_gpio_confdata 131bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = { 132 /* Port 0, pins 0-7 */ 133 { 134 U300_FLOATING_INPUT, 135 U300_OUTPUT_HIGH, 136 U300_FLOATING_INPUT, 137 U300_OUTPUT_LOW, 138 U300_OUTPUT_LOW, 139 U300_OUTPUT_LOW, 140 U300_OUTPUT_LOW, 141 U300_OUTPUT_LOW, 142 }, 143 /* Port 1, pins 0-7 */ 144 { 145 U300_OUTPUT_LOW, 146 U300_OUTPUT_LOW, 147 U300_OUTPUT_LOW, 148 U300_PULL_UP_INPUT, 149 U300_FLOATING_INPUT, 150 U300_OUTPUT_HIGH, 151 U300_OUTPUT_LOW, 152 U300_OUTPUT_LOW, 153 }, 154 /* Port 2, pins 0-7 */ 155 { 156 U300_FLOATING_INPUT, 157 U300_FLOATING_INPUT, 158 U300_FLOATING_INPUT, 159 U300_FLOATING_INPUT, 160 U300_OUTPUT_LOW, 161 U300_PULL_UP_INPUT, 162 U300_OUTPUT_LOW, 163 U300_PULL_UP_INPUT, 164 }, 165 /* Port 3, pins 0-7 */ 166 { 167 U300_PULL_UP_INPUT, 168 U300_OUTPUT_LOW, 169 U300_FLOATING_INPUT, 170 U300_FLOATING_INPUT, 171 U300_FLOATING_INPUT, 172 U300_FLOATING_INPUT, 173 U300_FLOATING_INPUT, 174 U300_FLOATING_INPUT, 175 }, 176 /* Port 4, pins 0-7 */ 177 { 178 U300_FLOATING_INPUT, 179 U300_FLOATING_INPUT, 180 U300_FLOATING_INPUT, 181 U300_FLOATING_INPUT, 182 U300_FLOATING_INPUT, 183 U300_FLOATING_INPUT, 184 U300_FLOATING_INPUT, 185 U300_FLOATING_INPUT, 186 }, 187 /* Port 5, pins 0-7 */ 188 { 189 U300_FLOATING_INPUT, 190 U300_FLOATING_INPUT, 191 U300_FLOATING_INPUT, 192 U300_FLOATING_INPUT, 193 U300_FLOATING_INPUT, 194 U300_FLOATING_INPUT, 195 U300_FLOATING_INPUT, 196 U300_FLOATING_INPUT, 197 }, 198 /* Port 6, pind 0-7 */ 199 { 200 U300_FLOATING_INPUT, 201 U300_FLOATING_INPUT, 202 U300_FLOATING_INPUT, 203 U300_FLOATING_INPUT, 204 U300_FLOATING_INPUT, 205 U300_FLOATING_INPUT, 206 U300_FLOATING_INPUT, 207 U300_FLOATING_INPUT, 208 } 209}; 210 211/** 212 * to_u300_gpio() - get the pointer to u300_gpio 213 * @chip: the gpio chip member of the structure u300_gpio 214 */ 215static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip) 216{ 217 return container_of(chip, struct u300_gpio, chip); 218} 219 220static int u300_gpio_get(struct gpio_chip *chip, unsigned offset) 221{ 222 struct u300_gpio *gpio = to_u300_gpio(chip); 223 224 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset); 225} 226 227static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 228{ 229 struct u300_gpio *gpio = to_u300_gpio(chip); 230 unsigned long flags; 231 u32 val; 232 233 local_irq_save(flags); 234 235 val = readl(U300_PIN_REG(offset, dor)); 236 if (value) 237 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); 238 else 239 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor)); 240 241 local_irq_restore(flags); 242} 243 244static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 245{ 246 struct u300_gpio *gpio = to_u300_gpio(chip); 247 unsigned long flags; 248 u32 val; 249 250 local_irq_save(flags); 251 val = readl(U300_PIN_REG(offset, pcr)); 252 /* Mask out this pin, note 2 bits per setting */ 253 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); 254 writel(val, U300_PIN_REG(offset, pcr)); 255 local_irq_restore(flags); 256 return 0; 257} 258 259static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 260 int value) 261{ 262 struct u300_gpio *gpio = to_u300_gpio(chip); 263 unsigned long flags; 264 u32 oldmode; 265 u32 val; 266 267 local_irq_save(flags); 268 val = readl(U300_PIN_REG(offset, pcr)); 269 /* 270 * Drive mode must be set by the special mode set function, set 271 * push/pull mode by default if no mode has been selected. 272 */ 273 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK << 274 ((offset & 0x07) << 1)); 275 /* mode = 0 means input, else some mode is already set */ 276 if (oldmode == 0) { 277 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << 278 ((offset & 0x07) << 1)); 279 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 280 << ((offset & 0x07) << 1)); 281 writel(val, U300_PIN_REG(offset, pcr)); 282 } 283 u300_gpio_set(chip, offset, value); 284 local_irq_restore(flags); 285 return 0; 286} 287 288/* Returning -EINVAL means "supported but not available" */ 289int u300_gpio_config_get(struct gpio_chip *chip, 290 unsigned offset, 291 unsigned long *config) 292{ 293 struct u300_gpio *gpio = to_u300_gpio(chip); 294 enum pin_config_param param = (enum pin_config_param) *config; 295 bool biasmode; 296 u32 drmode; 297 298 /* One bit per pin, clamp to bool range */ 299 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset)); 300 301 /* Mask out the two bits for this pin and shift to bits 0,1 */ 302 drmode = readl(U300_PIN_REG(offset, pcr)); 303 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1)); 304 drmode >>= ((offset & 0x07) << 1); 305 306 switch (param) { 307 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 308 *config = 0; 309 if (biasmode) 310 return 0; 311 else 312 return -EINVAL; 313 break; 314 case PIN_CONFIG_BIAS_PULL_UP: 315 *config = 0; 316 if (!biasmode) 317 return 0; 318 else 319 return -EINVAL; 320 break; 321 case PIN_CONFIG_DRIVE_PUSH_PULL: 322 *config = 0; 323 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL) 324 return 0; 325 else 326 return -EINVAL; 327 break; 328 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 329 *config = 0; 330 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN) 331 return 0; 332 else 333 return -EINVAL; 334 break; 335 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 336 *config = 0; 337 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE) 338 return 0; 339 else 340 return -EINVAL; 341 break; 342 default: 343 break; 344 } 345 return -ENOTSUPP; 346} 347 348int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset, 349 enum pin_config_param param) 350{ 351 struct u300_gpio *gpio = to_u300_gpio(chip); 352 unsigned long flags; 353 u32 val; 354 355 local_irq_save(flags); 356 switch (param) { 357 case PIN_CONFIG_BIAS_DISABLE: 358 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 359 val = readl(U300_PIN_REG(offset, per)); 360 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); 361 break; 362 case PIN_CONFIG_BIAS_PULL_UP: 363 val = readl(U300_PIN_REG(offset, per)); 364 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per)); 365 break; 366 case PIN_CONFIG_DRIVE_PUSH_PULL: 367 val = readl(U300_PIN_REG(offset, pcr)); 368 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 369 << ((offset & 0x07) << 1)); 370 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL 371 << ((offset & 0x07) << 1)); 372 writel(val, U300_PIN_REG(offset, pcr)); 373 break; 374 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 375 val = readl(U300_PIN_REG(offset, pcr)); 376 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 377 << ((offset & 0x07) << 1)); 378 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN 379 << ((offset & 0x07) << 1)); 380 writel(val, U300_PIN_REG(offset, pcr)); 381 break; 382 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 383 val = readl(U300_PIN_REG(offset, pcr)); 384 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK 385 << ((offset & 0x07) << 1)); 386 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE 387 << ((offset & 0x07) << 1)); 388 writel(val, U300_PIN_REG(offset, pcr)); 389 break; 390 default: 391 local_irq_restore(flags); 392 dev_err(gpio->dev, "illegal configuration requested\n"); 393 return -EINVAL; 394 } 395 local_irq_restore(flags); 396 return 0; 397} 398 399static struct gpio_chip u300_gpio_chip = { 400 .label = "u300-gpio-chip", 401 .owner = THIS_MODULE, 402 .request = gpiochip_generic_request, 403 .free = gpiochip_generic_free, 404 .get = u300_gpio_get, 405 .set = u300_gpio_set, 406 .direction_input = u300_gpio_direction_input, 407 .direction_output = u300_gpio_direction_output, 408}; 409 410static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset) 411{ 412 u32 val; 413 414 val = readl(U300_PIN_REG(offset, icr)); 415 /* Set mode depending on state */ 416 if (u300_gpio_get(&gpio->chip, offset)) { 417 /* High now, let's trigger on falling edge next then */ 418 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 419 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n", 420 offset); 421 } else { 422 /* Low now, let's trigger on rising edge next then */ 423 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 424 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n", 425 offset); 426 } 427} 428 429static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger) 430{ 431 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 432 struct u300_gpio *gpio = to_u300_gpio(chip); 433 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; 434 int offset = d->hwirq; 435 u32 val; 436 437 if ((trigger & IRQF_TRIGGER_RISING) && 438 (trigger & IRQF_TRIGGER_FALLING)) { 439 /* 440 * The GPIO block can only trigger on falling OR rising edges, 441 * not both. So we need to toggle the mode whenever the pin 442 * goes from one state to the other with a special state flag 443 */ 444 dev_dbg(gpio->dev, 445 "trigger on both rising and falling edge on pin %d\n", 446 offset); 447 port->toggle_edge_mode |= U300_PIN_BIT(offset); 448 u300_toggle_trigger(gpio, offset); 449 } else if (trigger & IRQF_TRIGGER_RISING) { 450 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n", 451 offset); 452 val = readl(U300_PIN_REG(offset, icr)); 453 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 454 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); 455 } else if (trigger & IRQF_TRIGGER_FALLING) { 456 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n", 457 offset); 458 val = readl(U300_PIN_REG(offset, icr)); 459 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr)); 460 port->toggle_edge_mode &= ~U300_PIN_BIT(offset); 461 } 462 463 return 0; 464} 465 466static void u300_gpio_irq_enable(struct irq_data *d) 467{ 468 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 469 struct u300_gpio *gpio = to_u300_gpio(chip); 470 struct u300_gpio_port *port = &gpio->ports[d->hwirq >> 3]; 471 int offset = d->hwirq; 472 u32 val; 473 unsigned long flags; 474 475 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n", 476 d->hwirq, port->name, offset); 477 local_irq_save(flags); 478 val = readl(U300_PIN_REG(offset, ien)); 479 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); 480 local_irq_restore(flags); 481} 482 483static void u300_gpio_irq_disable(struct irq_data *d) 484{ 485 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 486 struct u300_gpio *gpio = to_u300_gpio(chip); 487 int offset = d->hwirq; 488 u32 val; 489 unsigned long flags; 490 491 local_irq_save(flags); 492 val = readl(U300_PIN_REG(offset, ien)); 493 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien)); 494 local_irq_restore(flags); 495} 496 497static struct irq_chip u300_gpio_irqchip = { 498 .name = "u300-gpio-irqchip", 499 .irq_enable = u300_gpio_irq_enable, 500 .irq_disable = u300_gpio_irq_disable, 501 .irq_set_type = u300_gpio_irq_type, 502}; 503 504static void u300_gpio_irq_handler(struct irq_desc *desc) 505{ 506 unsigned int irq = irq_desc_get_irq(desc); 507 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 508 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 509 struct u300_gpio *gpio = to_u300_gpio(chip); 510 struct u300_gpio_port *port = &gpio->ports[irq - chip->base]; 511 int pinoffset = port->number << 3; /* get the right stride */ 512 unsigned long val; 513 514 chained_irq_enter(parent_chip, desc); 515 516 /* Read event register */ 517 val = readl(U300_PIN_REG(pinoffset, iev)); 518 /* Mask relevant bits */ 519 val &= 0xFFU; /* 8 bits per port */ 520 /* ACK IRQ (clear event) */ 521 writel(val, U300_PIN_REG(pinoffset, iev)); 522 523 /* Call IRQ handler */ 524 if (val != 0) { 525 int irqoffset; 526 527 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) { 528 int offset = pinoffset + irqoffset; 529 int pin_irq = irq_find_mapping(chip->irqdomain, offset); 530 531 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n", 532 pin_irq, offset); 533 generic_handle_irq(pin_irq); 534 /* 535 * Triggering IRQ on both rising and falling edge 536 * needs mockery 537 */ 538 if (port->toggle_edge_mode & U300_PIN_BIT(offset)) 539 u300_toggle_trigger(gpio, offset); 540 } 541 } 542 543 chained_irq_exit(parent_chip, desc); 544} 545 546static void __init u300_gpio_init_pin(struct u300_gpio *gpio, 547 int offset, 548 const struct u300_gpio_confdata *conf) 549{ 550 /* Set mode: input or output */ 551 if (conf->output) { 552 u300_gpio_direction_output(&gpio->chip, offset, conf->outval); 553 554 /* Deactivate bias mode for output */ 555 u300_gpio_config_set(&gpio->chip, offset, 556 PIN_CONFIG_BIAS_HIGH_IMPEDANCE); 557 558 /* Set drive mode for output */ 559 u300_gpio_config_set(&gpio->chip, offset, 560 PIN_CONFIG_DRIVE_PUSH_PULL); 561 562 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n", 563 offset, conf->outval); 564 } else { 565 u300_gpio_direction_input(&gpio->chip, offset); 566 567 /* Always set output low on input pins */ 568 u300_gpio_set(&gpio->chip, offset, 0); 569 570 /* Set bias mode for input */ 571 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode); 572 573 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n", 574 offset, conf->bias_mode); 575 } 576} 577 578static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio) 579{ 580 int i, j; 581 582 /* Write default config and values to all pins */ 583 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) { 584 for (j = 0; j < 8; j++) { 585 const struct u300_gpio_confdata *conf; 586 int offset = (i*8) + j; 587 588 conf = &bs335_gpio_config[i][j]; 589 u300_gpio_init_pin(gpio, offset, conf); 590 } 591 } 592} 593 594/* 595 * Here we map a GPIO in the local gpio_chip pin space to a pin in 596 * the local pinctrl pin space. The pin controller used is 597 * pinctrl-u300. 598 */ 599struct coh901_pinpair { 600 unsigned int offset; 601 unsigned int pin_base; 602}; 603 604#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b } 605 606static struct coh901_pinpair coh901_pintable[] = { 607 COH901_PINRANGE(10, 426), 608 COH901_PINRANGE(11, 180), 609 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */ 610 COH901_PINRANGE(13, 179), 611 COH901_PINRANGE(14, 178), 612 COH901_PINRANGE(16, 194), 613 COH901_PINRANGE(17, 193), 614 COH901_PINRANGE(18, 192), 615 COH901_PINRANGE(19, 191), 616 COH901_PINRANGE(20, 186), 617 COH901_PINRANGE(21, 185), 618 COH901_PINRANGE(22, 184), 619 COH901_PINRANGE(23, 183), 620 COH901_PINRANGE(24, 182), 621 COH901_PINRANGE(25, 181), 622}; 623 624static int __init u300_gpio_probe(struct platform_device *pdev) 625{ 626 struct u300_gpio *gpio; 627 struct resource *memres; 628 int err = 0; 629 int portno; 630 u32 val; 631 u32 ifr; 632 int i; 633 634 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL); 635 if (gpio == NULL) 636 return -ENOMEM; 637 638 gpio->chip = u300_gpio_chip; 639 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT; 640 gpio->chip.dev = &pdev->dev; 641 gpio->chip.base = 0; 642 gpio->dev = &pdev->dev; 643 644 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0); 645 gpio->base = devm_ioremap_resource(&pdev->dev, memres); 646 if (IS_ERR(gpio->base)) 647 return PTR_ERR(gpio->base); 648 649 gpio->clk = devm_clk_get(gpio->dev, NULL); 650 if (IS_ERR(gpio->clk)) { 651 err = PTR_ERR(gpio->clk); 652 dev_err(gpio->dev, "could not get GPIO clock\n"); 653 return err; 654 } 655 656 err = clk_prepare_enable(gpio->clk); 657 if (err) { 658 dev_err(gpio->dev, "could not enable GPIO clock\n"); 659 return err; 660 } 661 662 dev_info(gpio->dev, 663 "initializing GPIO Controller COH 901 571/3\n"); 664 gpio->stride = U300_GPIO_PORT_STRIDE; 665 gpio->pcr = U300_GPIO_PXPCR; 666 gpio->dor = U300_GPIO_PXPDOR; 667 gpio->dir = U300_GPIO_PXPDIR; 668 gpio->per = U300_GPIO_PXPER; 669 gpio->icr = U300_GPIO_PXICR; 670 gpio->ien = U300_GPIO_PXIEN; 671 gpio->iev = U300_GPIO_PXIEV; 672 ifr = U300_GPIO_PXIFR; 673 674 val = readl(gpio->base + U300_GPIO_CR); 675 dev_info(gpio->dev, "COH901571/3 block version: %d, " \ 676 "number of cores: %d totalling %d pins\n", 677 ((val & 0x000001FC) >> 2), 678 ((val & 0x0000FE00) >> 9), 679 ((val & 0x0000FE00) >> 9) * 8); 680 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE, 681 gpio->base + U300_GPIO_CR); 682 u300_gpio_init_coh901571(gpio); 683 684#ifdef CONFIG_OF_GPIO 685 gpio->chip.of_node = pdev->dev.of_node; 686#endif 687 err = gpiochip_add(&gpio->chip); 688 if (err) { 689 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err); 690 goto err_no_chip; 691 } 692 693 err = gpiochip_irqchip_add(&gpio->chip, 694 &u300_gpio_irqchip, 695 0, 696 handle_simple_irq, 697 IRQ_TYPE_EDGE_FALLING); 698 if (err) { 699 dev_err(gpio->dev, "no GPIO irqchip\n"); 700 goto err_no_irqchip; 701 } 702 703 /* Add each port with its IRQ separately */ 704 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) { 705 struct u300_gpio_port *port = &gpio->ports[portno]; 706 707 snprintf(port->name, 8, "gpio%d", portno); 708 port->number = portno; 709 port->gpio = gpio; 710 711 port->irq = platform_get_irq(pdev, portno); 712 713 gpiochip_set_chained_irqchip(&gpio->chip, 714 &u300_gpio_irqchip, 715 port->irq, 716 u300_gpio_irq_handler); 717 718 /* Turns off irq force (test register) for this port */ 719 writel(0x0, gpio->base + portno * gpio->stride + ifr); 720 } 721 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno); 722 723 /* 724 * Add pinctrl pin ranges, the pin controller must be registered 725 * at this point 726 */ 727 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) { 728 struct coh901_pinpair *p = &coh901_pintable[i]; 729 730 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300", 731 p->offset, p->pin_base, 1); 732 if (err) 733 goto err_no_range; 734 } 735 736 platform_set_drvdata(pdev, gpio); 737 738 return 0; 739 740err_no_range: 741err_no_irqchip: 742 gpiochip_remove(&gpio->chip); 743err_no_chip: 744 clk_disable_unprepare(gpio->clk); 745 dev_err(&pdev->dev, "module ERROR:%d\n", err); 746 return err; 747} 748 749static int __exit u300_gpio_remove(struct platform_device *pdev) 750{ 751 struct u300_gpio *gpio = platform_get_drvdata(pdev); 752 753 /* Turn off the GPIO block */ 754 writel(0x00000000U, gpio->base + U300_GPIO_CR); 755 756 gpiochip_remove(&gpio->chip); 757 clk_disable_unprepare(gpio->clk); 758 return 0; 759} 760 761static const struct of_device_id u300_gpio_match[] = { 762 { .compatible = "stericsson,gpio-coh901" }, 763 {}, 764}; 765 766static struct platform_driver u300_gpio_driver = { 767 .driver = { 768 .name = "u300-gpio", 769 .of_match_table = u300_gpio_match, 770 }, 771 .remove = __exit_p(u300_gpio_remove), 772}; 773 774static int __init u300_gpio_init(void) 775{ 776 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe); 777} 778 779static void __exit u300_gpio_exit(void) 780{ 781 platform_driver_unregister(&u300_gpio_driver); 782} 783 784arch_initcall(u300_gpio_init); 785module_exit(u300_gpio_exit); 786 787MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>"); 788MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver"); 789MODULE_LICENSE("GPL"); 790