Lines Matching refs:writel
291 writel(x, fbi->reg_base + LCD_CFG_SCLK_DIV); in set_clock_divider()
326 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0); in set_dma_control0()
348 writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL1); in set_dma_control1()
361 writel(addr, fbi->reg_base + LCD_CFG_GRA_START_ADDR0); in set_graphics_start()
386 writel(x, fbi->reg_base + LCD_SPU_DUMB_CTRL); in set_dumb_panel_control()
399 writel((y << 16) | x, fbi->reg_base + LCD_SPUT_V_H_TOTAL); in set_dumb_screen_dimensions()
426 writel(x & ~1, fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
431 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
451 writel(x, fbi->reg_base + LCD_CFG_GRA_PITCH); in pxa168fb_set_par()
452 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
454 writel((var->yres << 16) | var->xres, in pxa168fb_set_par()
463 writel((var->left_margin << 16) | var->right_margin, in pxa168fb_set_par()
465 writel((var->upper_margin << 16) | var->lower_margin, in pxa168fb_set_par()
472 writel(x | 1, fbi->reg_base + LCD_SPU_DUMB_CTRL); in pxa168fb_set_par()
511 writel(val, fbi->reg_base + LCD_SPU_SRAM_WRDAT); in pxa168fb_setcolreg()
512 writel(0x8300 | regno, fbi->reg_base + LCD_SPU_SRAM_CTRL); in pxa168fb_setcolreg()
543 writel(isr & (~GRA_FRAME_IRQ0_ENA_MASK), in pxa168fb_handle_irq()
722 writel(0, fbi->reg_base + LCD_SPU_BLANKCOLOR); in pxa168fb_probe()
723 writel(mi->io_pin_allocation_mode, fbi->reg_base + SPU_IOPAD_CONTROL); in pxa168fb_probe()
724 writel(0, fbi->reg_base + LCD_CFG_GRA_START_ADDR1); in pxa168fb_probe()
725 writel(0, fbi->reg_base + LCD_SPU_GRA_OVSA_HPXL_VLN); in pxa168fb_probe()
726 writel(0, fbi->reg_base + LCD_SPU_SRAM_PARA0); in pxa168fb_probe()
727 writel(CFG_CSB_256x32(0x1)|CFG_CSB_256x24(0x1)|CFG_CSB_256x8(0x1), in pxa168fb_probe()
752 writel(GRA_FRAME_IRQ0_ENA(0x1), fbi->reg_base + SPU_IRQ_ENA); in pxa168fb_probe()
794 writel(data, fbi->reg_base + LCD_SPU_DMA_CTRL0); in pxa168fb_remove()
800 writel(GRA_FRAME_IRQ0_ENA(0x0), fbi->reg_base + SPU_IRQ_ENA); in pxa168fb_remove()