43 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
53 	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);  in sxgbe_mtl_init()
59 	writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG);  in sxgbe_mtl_dma_dm_rxqueue()
60 	writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG);  in sxgbe_mtl_dma_dm_rxqueue()
61 	writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG);  in sxgbe_mtl_dma_dm_rxqueue()
73 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_txfifosize()
85 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_set_rxfifosize()
94 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_enable_txqueue()
103 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_disable_txqueue()
115 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_active()
124 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_enable()
136 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fc_deactive()
146 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_enable()
156 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fep_disable()
166 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_enable()
176 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_mtl_fup_disable()
208 	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));  in sxgbe_set_tx_mtl_mode()
230 	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));  in sxgbe_set_rx_mtl_mode()