72 	writel(readl(&app_reg->slv_armisc) | (1 << AXI_OP_DBI_ACCESS_ID),  in enable_dbi_access()
74 	writel(readl(&app_reg->slv_awmisc) | (1 << AXI_OP_DBI_ACCESS_ID),  in enable_dbi_access()
82 	writel(readl(&app_reg->slv_armisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),  in disable_dbi_access()
84 	writel(readl(&app_reg->slv_awmisc) & ~(1 << AXI_OP_DBI_ACCESS_ID),  in disable_dbi_access()
123 		writel(val, va_address);  in spear_dbi_write_reg()
247 		writel(readl(&app_reg->app_ctrl_0) | (1 << APP_LTSSM_ENABLE_ID),  in pcie_gadget_link_store()
250 		writel(readl(&app_reg->app_ctrl_0)  in pcie_gadget_link_store()
345 		writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID),  in pcie_gadget_inta_store()
348 		writel(readl(&app_reg->app_ctrl_0) & ~(1 << SYS_INT_ID),  in pcie_gadget_inta_store()
383 	writel(ven_msi, &app_reg->ven_msi_1);  in pcie_gadget_send_msi_store()
386 	writel(ven_msi, &app_reg->ven_msi_1);  in pcie_gadget_send_msi_store()
513 	writel(address, &app_reg->pim0_mem_addr_start);  in pcie_gadget_bar0_address_store()
569 	writel(data, (ulong)config->va_bar0_address + config->bar0_rw_offset);  in pcie_gadget_bar0_data_store()
612 	writel(config->base, &app_reg->in0_mem_addr_start);  in spear13xx_pcie_device_init()
613 	writel(app_reg->in0_mem_addr_start + IN0_MEM_SIZE,  in spear13xx_pcie_device_init()
615 	writel(app_reg->in0_mem_addr_limit + 1, &app_reg->in1_mem_addr_start);  in spear13xx_pcie_device_init()
616 	writel(app_reg->in1_mem_addr_start + IN1_MEM_SIZE,  in spear13xx_pcie_device_init()
618 	writel(app_reg->in1_mem_addr_limit + 1, &app_reg->in_io_addr_start);  in spear13xx_pcie_device_init()
619 	writel(app_reg->in_io_addr_start + IN_IO_SIZE,  in spear13xx_pcie_device_init()
621 	writel(app_reg->in_io_addr_limit + 1, &app_reg->in_cfg0_addr_start);  in spear13xx_pcie_device_init()
622 	writel(app_reg->in_cfg0_addr_start + IN_CFG0_SIZE,  in spear13xx_pcie_device_init()
624 	writel(app_reg->in_cfg0_addr_limit + 1, &app_reg->in_cfg1_addr_start);  in spear13xx_pcie_device_init()
625 	writel(app_reg->in_cfg1_addr_start + IN_CFG1_SIZE,  in spear13xx_pcie_device_init()
627 	writel(app_reg->in_cfg1_addr_limit + 1, &app_reg->in_msg_addr_start);  in spear13xx_pcie_device_init()
628 	writel(app_reg->in_msg_addr_start + IN_MSG_SIZE,  in spear13xx_pcie_device_init()
631 	writel(app_reg->in0_mem_addr_start, &app_reg->pom0_mem_addr_start);  in spear13xx_pcie_device_init()
632 	writel(app_reg->in1_mem_addr_start, &app_reg->pom1_mem_addr_start);  in spear13xx_pcie_device_init()
633 	writel(app_reg->in_io_addr_start, &app_reg->pom_io_addr_start);  in spear13xx_pcie_device_init()
644 	writel(SPEAR13XX_SYSRAM1_BASE, &app_reg->pim0_mem_addr_start);  in spear13xx_pcie_device_init()
645 	writel(0, &app_reg->pim1_mem_addr_start);  in spear13xx_pcie_device_init()
646 	writel(INBOUND_ADDR_MASK + 1, &app_reg->mem0_addr_offset_limit);  in spear13xx_pcie_device_init()
648 	writel(0x0, &app_reg->pim_io_addr_start);  in spear13xx_pcie_device_init()
649 	writel(0x0, &app_reg->pim_io_addr_start);  in spear13xx_pcie_device_init()
650 	writel(0x0, &app_reg->pim_rom_addr_start);  in spear13xx_pcie_device_init()
652 	writel(DEVICE_TYPE_EP | (1 << MISCTRL_EN_ID)  in spear13xx_pcie_device_init()
656 	writel(0, &app_reg->int_mask);  in spear13xx_pcie_device_init()