298 		writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK);  in cas_disable_irq()
315 			writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN,  in cas_disable_irq()
320 			writel(INTRN_MASK_CLEAR_ALL, cp->regs +  in cas_disable_irq()
338 		writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK);  in cas_enable_irq()
354 			writel(INTRN_MASK_RX_EN, cp->regs +  in cas_enable_irq()
390 	writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT,  in cas_entropy_reset()
413 	writel(cmd, cp->regs + REG_MIF_FRAME);  in cas_phy_read()
435 	writel(cmd, cp->regs + REG_MIF_FRAME);  in cas_phy_write()
688 	writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF,  in cas_mif_poll()
690 	writel(cfg, cp->regs + REG_MIF_CFG);  in cas_mif_poll()
769 		writel(val, cp->regs + REG_PCS_MII_CTRL);  in cas_begin_auto_negotiation()
880 		writel(PCS_DATAPATH_MODE_MII,  in cas_phy_init()
916 			writel((cp->phy_type & CAS_PHY_MII_MDIO0) ?  in cas_phy_init()
958 		writel(PCS_DATAPATH_MODE_SERDES,  in cas_phy_init()
963 			writel(0, cp->regs + REG_SATURN_PCFG);  in cas_phy_init()
968 		writel(val, cp->regs + REG_PCS_MII_CTRL);  in cas_phy_init()
984 		writel(0x0, cp->regs + REG_PCS_CFG);  in cas_phy_init()
991 		writel(val, cp->regs + REG_PCS_MII_ADVERT);  in cas_phy_init()
994 		writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG);  in cas_phy_init()
997 		writel(PCS_SERDES_CTRL_SYNCD_EN,  in cas_phy_init()
1177 		writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR);  in cas_load_firmware()
1181 		writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);  in cas_load_firmware()
1190 		writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);  in cas_load_firmware()
1196 		writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);  in cas_load_firmware()
1215 	writel(val, cp->regs + REG_RX_CFG);  in cas_init_rx_dma()
1219 	writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);  in cas_init_rx_dma()
1220 	writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);  in cas_init_rx_dma()
1221 	writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);  in cas_init_rx_dma()
1229 		writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);  in cas_init_rx_dma()
1230 		writel((desc_dma + val) & 0xffffffff, cp->regs +  in cas_init_rx_dma()
1232 		writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs +  in cas_init_rx_dma()
1239 	writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);  in cas_init_rx_dma()
1240 	writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);  in cas_init_rx_dma()
1247 			writel((desc_dma + val) >> 32, cp->regs +  in cas_init_rx_dma()
1249 			writel((desc_dma + val) & 0xffffffff, cp->regs +  in cas_init_rx_dma()
1259 	writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR);  in cas_init_rx_dma()
1266 			writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1,  in cas_init_rx_dma()
1270 			writel(INTR_RX_DONE_ALT,  in cas_init_rx_dma()
1279 	writel(val, cp->regs + REG_RX_PAUSE_THRESH);  in cas_init_rx_dma()
1283 		writel(i, cp->regs + REG_RX_TABLE_ADDR);  in cas_init_rx_dma()
1284 		writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW);  in cas_init_rx_dma()
1285 		writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID);  in cas_init_rx_dma()
1286 		writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI);  in cas_init_rx_dma()
1290 	writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR);  in cas_init_rx_dma()
1291 	writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR);  in cas_init_rx_dma()
1297 	writel(val, cp->regs + REG_RX_BLANK);  in cas_init_rx_dma()
1299 	writel(0x0, cp->regs + REG_RX_BLANK);  in cas_init_rx_dma()
1309 	writel(val, cp->regs + REG_RX_AE_THRESH);  in cas_init_rx_dma()
1312 		writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);  in cas_init_rx_dma()
1318 	writel(0x0, cp->regs + REG_RX_RED);  in cas_init_rx_dma()
1348 	writel(val, cp->regs + REG_RX_PAGE_SIZE);  in cas_init_rx_dma()
1357 	writel(val, cp->regs + REG_HP_CFG);  in cas_init_rx_dma()
1463 	writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1475 	writel(0, cp->regs + REG_RX_CFG);
1489 	writel(SW_RESET_RX, cp->regs + REG_SW_RESET);
1509 	writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1510 	writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);
1512 	writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
2209 		writel(entry, cp->regs + REG_RX_KICK);  in cas_post_page()
2212 		writel(entry, cp->regs + REG_PLUS_RX_KICK1);  in cas_post_page()
2270 		writel(cluster, cp->regs + REG_RX_KICK);  in cas_post_rxds_ringN()
2273 		writel(cluster, cp->regs + REG_PLUS_RX_KICK1);  in cas_post_rxds_ringN()
2426 		writel(last, cp->regs + REG_RX_COMP_TAIL);  in cas_post_rxcs_ringN()
2428 		writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring));  in cas_post_rxcs_ringN()
2860 	writel(entry, cp->regs + REG_TX_KICKN(ring));  in cas_xmit_tx_ringN()
2895 	writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI);  in cas_init_tx_dma()
2896 	writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW);  in cas_init_tx_dma()
2913 		writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i));  in cas_init_tx_dma()
2914 		writel((desc_dma + off) & 0xffffffff, cp->regs +  in cas_init_tx_dma()
2920 	writel(val, cp->regs + REG_TX_CFG);  in cas_init_tx_dma()
2926 	writel(0x800, cp->regs + REG_TX_MAXBURST_0);  in cas_init_tx_dma()
2927 	writel(0x1600, cp->regs + REG_TX_MAXBURST_1);  in cas_init_tx_dma()
2928 	writel(0x2400, cp->regs + REG_TX_MAXBURST_2);  in cas_init_tx_dma()
2929 	writel(0x4800, cp->regs + REG_TX_MAXBURST_3);  in cas_init_tx_dma()
2931 	writel(0x800, cp->regs + REG_TX_MAXBURST_0);  in cas_init_tx_dma()
2932 	writel(0x800, cp->regs + REG_TX_MAXBURST_1);  in cas_init_tx_dma()
2933 	writel(0x800, cp->regs + REG_TX_MAXBURST_2);  in cas_init_tx_dma()
2934 	writel(0x800, cp->regs + REG_TX_MAXBURST_3);  in cas_init_tx_dma()
2958 			writel((ha->addr[4] << 8) | ha->addr[5],  in cas_process_mc_list()
2960 			writel((ha->addr[2] << 8) | ha->addr[3],  in cas_process_mc_list()
2962 			writel((ha->addr[0] << 8) | ha->addr[1],  in cas_process_mc_list()
2976 		writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i));  in cas_process_mc_list()
2990 			writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i));  in cas_setup_multicast()
3004 	writel(0, cp->regs + REG_MAC_COLL_NORMAL);  in cas_clear_mac_err()
3005 	writel(0, cp->regs + REG_MAC_COLL_FIRST);  in cas_clear_mac_err()
3006 	writel(0, cp->regs + REG_MAC_COLL_EXCESS);  in cas_clear_mac_err()
3007 	writel(0, cp->regs + REG_MAC_COLL_LATE);  in cas_clear_mac_err()
3008 	writel(0, cp->regs + REG_MAC_TIMER_DEFER);  in cas_clear_mac_err()
3009 	writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK);  in cas_clear_mac_err()
3010 	writel(0, cp->regs + REG_MAC_RECV_FRAME);  in cas_clear_mac_err()
3011 	writel(0, cp->regs + REG_MAC_LEN_ERR);  in cas_clear_mac_err()
3012 	writel(0, cp->regs + REG_MAC_ALIGN_ERR);  in cas_clear_mac_err()
3013 	writel(0, cp->regs + REG_MAC_FCS_ERR);  in cas_clear_mac_err()
3014 	writel(0, cp->regs + REG_MAC_RX_CODE_ERR);  in cas_clear_mac_err()
3023 	writel(0x1, cp->regs + REG_MAC_TX_RESET);  in cas_mac_reset()
3024 	writel(0x1, cp->regs + REG_MAC_RX_RESET);  in cas_mac_reset()
3059 	writel(CAWR_RR_DIS, cp->regs + REG_CAWR);  in cas_init_mac()
3066 		writel(INF_BURST_EN, cp->regs + REG_INF_BURST);  in cas_init_mac()
3069 	writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE);  in cas_init_mac()
3071 	writel(0x00, cp->regs + REG_MAC_IPG0);  in cas_init_mac()
3072 	writel(0x08, cp->regs + REG_MAC_IPG1);  in cas_init_mac()
3073 	writel(0x04, cp->regs + REG_MAC_IPG2);  in cas_init_mac()
3076 	writel(0x40, cp->regs + REG_MAC_SLOT_TIME);  in cas_init_mac()
3079 	writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN);  in cas_init_mac()
3085 	writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) |  in cas_init_mac()
3095 		writel(0x41, cp->regs + REG_MAC_PA_SIZE);  in cas_init_mac()
3097 		writel(0x07, cp->regs + REG_MAC_PA_SIZE);  in cas_init_mac()
3098 	writel(0x04, cp->regs + REG_MAC_JAM_SIZE);  in cas_init_mac()
3099 	writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT);  in cas_init_mac()
3100 	writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE);  in cas_init_mac()
3102 	writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED);  in cas_init_mac()
3104 	writel(0, cp->regs + REG_MAC_ADDR_FILTER0);  in cas_init_mac()
3105 	writel(0, cp->regs + REG_MAC_ADDR_FILTER1);  in cas_init_mac()
3106 	writel(0, cp->regs + REG_MAC_ADDR_FILTER2);  in cas_init_mac()
3107 	writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK);  in cas_init_mac()
3108 	writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK);  in cas_init_mac()
3112 		writel(0x0, cp->regs + REG_MAC_ADDRN(i));  in cas_init_mac()
3114 	writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0));  in cas_init_mac()
3115 	writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1));  in cas_init_mac()
3116 	writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2));  in cas_init_mac()
3118 	writel(0x0001, cp->regs + REG_MAC_ADDRN(42));  in cas_init_mac()
3119 	writel(0xc200, cp->regs + REG_MAC_ADDRN(43));  in cas_init_mac()
3120 	writel(0x0180, cp->regs + REG_MAC_ADDRN(44));  in cas_init_mac()
3132 	writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK);  in cas_init_mac()
3133 	writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK);  in cas_init_mac()
3138 	writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK);  in cas_init_mac()
3205 	writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD,  in cas_get_vpd_info()
3367 	writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN);  in cas_get_vpd_info()
3450 	writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);  in cas_check_invariants()
3488 	writel(val, cp->regs + REG_TX_CFG);  in cas_start_dma()
3490 	writel(val, cp->regs + REG_RX_CFG);  in cas_start_dma()
3494 	writel(val, cp->regs + REG_MAC_TX_CFG);  in cas_start_dma()
3496 	writel(val, cp->regs + REG_MAC_RX_CFG);  in cas_start_dma()
3527 	writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK);  in cas_start_dma()
3528 	writel(0, cp->regs + REG_RX_COMP_TAIL);  in cas_start_dma()
3532 			writel(RX_DESC_RINGN_SIZE(1) - 4,  in cas_start_dma()
3536 			writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i));  in cas_start_dma()
3638 	writel(val, cp->regs + REG_MAC_XIF_CFG);  in cas_set_link_modes()
3659 		writel(val | MAC_TX_CFG_CARRIER_EXTEND,  in cas_set_link_modes()
3664 		writel(val | MAC_RX_CFG_CARRIER_EXTEND,  in cas_set_link_modes()
3667 		writel(0x200, cp->regs + REG_MAC_SLOT_TIME);  in cas_set_link_modes()
3674 		writel(val, cp->regs + REG_MAC_TX_CFG);  in cas_set_link_modes()
3689 		writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,  in cas_set_link_modes()
3691 		writel(0x40, cp->regs + REG_MAC_SLOT_TIME);  in cas_set_link_modes()
3715 	writel(val, cp->regs + REG_MAC_CTRL_CFG);  in cas_set_link_modes()
3745 	writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN);  in cas_hard_reset()
3763 		writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK),  in cas_global_reset()
3766 		writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET);  in cas_global_reset()
3783 	writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE |  in cas_global_reset()
3790 	writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO |  in cas_global_reset()
3798 	writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE);  in cas_global_reset()
3813 	writel(val, cp->regs + REG_TX_CFG);  in cas_reset()
3817 	writel(val, cp->regs + REG_RX_CFG);  in cas_reset()
4502 	writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);  in cas_set_multicast()
4512 	writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);  in cas_set_multicast()
4522 	writel(rxcfg, cp->regs + REG_MAC_RX_CFG);  in cas_set_multicast()