507 	writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);  in pdc20621_dma_prep()
542 	writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);  in pdc20621_nodata_prep()
574 	writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));  in __pdc20621_push_hdma()
577 	writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);  in __pdc20621_push_hdma()
667 		writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));  in pdc20621_packet_start()
670 		writel(port_ofs + PDC_DIMM_ATA_PKT,  in pdc20621_packet_start()
750 			writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));  in pdc20621_host_intr()
752 			writel(port_ofs + PDC_DIMM_ATA_PKT,  in pdc20621_host_intr()
863 	writel(tmp, mmio + PDC_CTLSTAT);  in pdc_freeze()
880 	writel(tmp, mmio + PDC_CTLSTAT);  in pdc_thaw()
900 		writel(tmp, mmio);  in pdc_reset_port()
904 	writel(tmp, mmio);  in pdc_reset_port()
1014 	writel(0x01, mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1016 	writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1028 		writel(0x01, mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1030 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1039 		writel(0x01, mmio + PDC_GENERAL_CTLR);  in pdc20621_get_from_dimm()
1041 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_get_from_dimm()
1066 	writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1073 	writel(0x01, mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1079 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1082 		writel(0x01, mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1090 		writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);  in pdc20621_put_to_dimm()
1093 		writel(0x01, mmio + PDC_GENERAL_CTLR);  in pdc20621_put_to_dimm()
1114 	writel(i2creg, mmio + PDC_I2C_ADDR_DATA);  in pdc20621_i2c_read()
1118 	writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,  in pdc20621_i2c_read()
1214 	writel(data, mmio + PDC_DIMM0_CONTROL);  in pdc20621_prog_dimm0()
1237 	writel(data, mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1249 		writel(data, mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1257 	writel(data, mmio + PDC_SDRAM_CONTROL);  in pdc20621_prog_dimm_global()
1289 	writel(0xffffffff, mmio + PDC_TIME_PERIOD);  in pdc20621_dimm_init()
1294 	writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);  in pdc20621_dimm_init()
1333 	writel(pci_status, mmio + PDC_CTL_STATUS);  in pdc20621_dimm_init()
1424 	writel(tmp, mmio + PDC_20621_DIMM_WINDOW);  in pdc_20621_init()
1431 	writel(tmp, mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()
1438 	writel(tmp, mmio + PDC_HDMA_CTLSTAT);  in pdc_20621_init()