1006 			writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);  in setup_hw_rings()
1008 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysA…  in setup_hw_rings()
1011 			writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);  in setup_hw_rings()
1012 			writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);  in setup_hw_rings()
1015 …writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPh…  in setup_hw_rings()
1016 …writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingP…  in setup_hw_rings()
1063 		writel(powerstate, base + NvRegPowerState2);  in nv_txrx_gate()
1104 	writel(mask, base + NvRegIrqMask);  in nv_enable_hw_interrupts()
1113 		writel(mask, base + NvRegIrqMask);  in nv_disable_hw_interrupts()
1116 			writel(0, base + NvRegMSIIrqMask);  in nv_disable_hw_interrupts()
1117 		writel(0, base + NvRegIrqMask);  in nv_disable_hw_interrupts()
1146 	writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);  in mii_rw()
1150 		writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);  in mii_rw()
1156 		writel(value, base + NvRegMIIData);  in mii_rw()
1159 	writel(reg, base + NvRegMIIControl);  in mii_rw()
1232 	writel(powerstate, base + NvRegPowerState2);  in init_realtek_8211c()
1236 	writel(powerstate, base + NvRegPowerState2);  in init_realtek_8211c()
1538 		writel(rx_ctrl, base + NvRegReceiverControl);  in nv_start_rx()
1541 	writel(np->linkspeed, base + NvRegLinkSpeed);  in nv_start_rx()
1546 	writel(rx_ctrl, base + NvRegReceiverControl);  in nv_start_rx()
1560 	writel(rx_ctrl, base + NvRegReceiverControl);  in nv_stop_rx()
1568 		writel(0, base + NvRegLinkSpeed);  in nv_stop_rx()
1580 	writel(tx_ctrl, base + NvRegTransmitterControl);  in nv_start_tx()
1594 	writel(tx_ctrl, base + NvRegTransmitterControl);  in nv_stop_tx()
1602 		writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,  in nv_stop_tx()
1623 	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_txrx_reset()
1626 	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_txrx_reset()
1636 	writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_mac_reset()
1644 	writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);  in nv_mac_reset()
1647 	writel(0, base + NvRegMacReset);  in nv_mac_reset()
1652 	writel(temp1, base + NvRegMacAddrA);  in nv_mac_reset()
1653 	writel(temp2, base + NvRegMacAddrB);  in nv_mac_reset()
1654 	writel(temp3, base + NvRegTransmitPoll);  in nv_mac_reset()
1656 	writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);  in nv_mac_reset()
2091 	writel(reg, base + NvRegSlotTime);  in nv_legacybackoff_reseed()
2168 	writel(temp, base + NvRegBackOffControl);  in nv_gear_backoff_reseed()
2177 		writel(temp, base + NvRegBackOffControl);  in nv_gear_backoff_reseed()
2327 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_start_xmit()
2504 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_start_xmit_optimized()
2522 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_tx_flip_ownership()
3049 		writel(np->rx_buf_sz, base + NvRegOffloadConfig);  in nv_change_mtu()
3051 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH…  in nv_change_mtu()
3054 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_change_mtu()
3077 	writel(mac[0], base + NvRegMacAddrA);  in nv_copy_mac_to_hw()
3078 	writel(mac[1], base + NvRegMacAddrB);  in nv_copy_mac_to_hw()
3173 	writel(addr[0], base + NvRegMulticastAddrA);  in nv_set_multicast()
3174 	writel(addr[1], base + NvRegMulticastAddrB);  in nv_set_multicast()
3175 	writel(mask[0], base + NvRegMulticastMaskA);  in nv_set_multicast()
3176 	writel(mask[1], base + NvRegMulticastMaskB);  in nv_set_multicast()
3177 	writel(pff, base + NvRegPacketFilterFlags);  in nv_set_multicast()
3192 			writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);  in nv_update_pause()
3195 			writel(pff, base + NvRegPacketFilterFlags);  in nv_update_pause()
3207 …writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFr…  in nv_update_pause()
3209 			writel(pause_enable,  base + NvRegTxPauseFrame);  in nv_update_pause()
3210 			writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);  in nv_update_pause()
3213 			writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);  in nv_update_pause()
3214 			writel(regmisc, base + NvRegMisc1);  in nv_update_pause()
3241 		writel(phyreg, base + NvRegSlotTime);  in nv_force_linkspeed()
3253 	writel(phyreg, base + NvRegPhyInterface);  in nv_force_linkspeed()
3264 	writel(txreg, base + NvRegTxDeferral);  in nv_force_linkspeed()
3275 	writel(txreg, base + NvRegTxWatermark);  in nv_force_linkspeed()
3277 	writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),  in nv_force_linkspeed()
3280 	writel(np->linkspeed, base + NvRegLinkSpeed);  in nv_force_linkspeed()
3425 		writel(phyreg, base + NvRegSlotTime);  in nv_update_linkspeed()
3436 	writel(phyreg, base + NvRegPhyInterface);  in nv_update_linkspeed()
3458 	writel(txreg, base + NvRegTxDeferral);  in nv_update_linkspeed()
3468 	writel(txreg, base + NvRegTxWatermark);  in nv_update_linkspeed()
3470 	writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),  in nv_update_linkspeed()
3473 	writel(np->linkspeed, base + NvRegLinkSpeed);  in nv_update_linkspeed()
3544 	writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);  in nv_link_irq()
3559 		writel(0, base + NvRegMSIIrqMask);  in nv_msi_workaround()
3560 		writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);  in nv_msi_workaround()
3600 		writel(np->events, base + NvRegIrqStatus);  in nv_nic_irq()
3603 		writel(np->events, base + NvRegMSIXIrqStatus);  in nv_nic_irq()
3614 		writel(0, base + NvRegIrqMask);  in nv_nic_irq()
3633 		writel(np->events, base + NvRegIrqStatus);  in nv_nic_irq_optimized()
3636 		writel(np->events, base + NvRegMSIXIrqStatus);  in nv_nic_irq_optimized()
3647 		writel(0, base + NvRegIrqMask);  in nv_nic_irq_optimized()
3665 		writel(events, base + NvRegMSIXIrqStatus);  in nv_nic_irq_tx()
3677 			writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);  in nv_nic_irq_tx()
3761 		writel(np->irqmask, base + NvRegIrqMask);  in nv_napi_poll()
3777 		writel(events, base + NvRegMSIXIrqStatus);  in nv_nic_irq_rx()
3794 			writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);  in nv_nic_irq_rx()
3822 		writel(events, base + NvRegMSIXIrqStatus);  in nv_nic_irq_other()
3846 			writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);  in nv_nic_irq_other()
3860 			writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);  in nv_nic_irq_other()
3887 		writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);  in nv_nic_irq_test()
3890 		writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);  in nv_nic_irq_test()
3919 	writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);  in set_msix_vector_map()
3926 	writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);  in set_msix_vector_map()
3993 				writel(0, base + NvRegMSIXMap0);  in nv_request_irq()
3994 				writel(0, base + NvRegMSIXMap1);  in nv_request_irq()
4012 				writel(0, base + NvRegMSIXMap0);  in nv_request_irq()
4013 				writel(0, base + NvRegMSIXMap1);  in nv_request_irq()
4033 			writel(0, base + NvRegMSIMap0);  in nv_request_irq()
4034 			writel(0, base + NvRegMSIMap1);  in nv_request_irq()
4036 			writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);  in nv_request_irq()
4133 			writel(np->rx_buf_sz, base + NvRegOffloadConfig);  in nv_do_nic_poll()
4135 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH…  in nv_do_nic_poll()
4138 			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_do_nic_poll()
4142 				writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);  in nv_do_nic_poll()
4144 				writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);  in nv_do_nic_poll()
4154 	writel(mask, base + NvRegIrqMask);  in nv_do_nic_poll()
4240 		writel(flags, base + NvRegWakeUpFlags);  in nv_set_wol()
4665 		writel(np->rx_buf_sz, base + NvRegOffloadConfig);  in nv_set_ringparam()
4667 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH…  in nv_set_ringparam()
4670 		writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_set_ringparam()
4846 	writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_vlan_mode()
4873 			writel(np->txrxctl_bits, base + NvRegTxRxControl);  in nv_set_features()
4949 		writel(orig_read, base + nv_registers_test[i].reg);  in nv_register_test()
4958 		writel(orig_read, base + nv_registers_test[i].reg);  in nv_register_test()
4990 	writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);  in nv_interrupt_test()
4991 	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);  in nv_interrupt_test()
5007 		writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);  in nv_interrupt_test()
5009 		writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);  in nv_interrupt_test()
5018 		writel(save_poll_interval, base + NvRegPollingInterval);  in nv_interrupt_test()
5019 		writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);  in nv_interrupt_test()
5055 	writel(NVREG_MISC1_FORCE, base + NvRegMisc1);  in nv_loopback_test()
5056 	writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);  in nv_loopback_test()
5059 	writel(np->rx_buf_sz, base + NvRegOffloadConfig);  in nv_loopback_test()
5061 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH…  in nv_loopback_test()
5095 	writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_loopback_test()
5146 		writel(misc1_flags, base + NvRegMisc1);  in nv_loopback_test()
5147 		writel(filter_flags, base + NvRegPacketFilterFlags);  in nv_loopback_test()
5177 				writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);  in nv_self_test()
5179 				writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);  in nv_self_test()
5218 			writel(np->rx_buf_sz, base + NvRegOffloadConfig);  in nv_self_test()
5220 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH…  in nv_self_test()
5223 			writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);  in nv_self_test()
5288 		writel(tx_ctrl, base + NvRegTransmitterControl);  in nv_mgmt_acquire_sema()
5313 			writel(tx_ctrl, base + NvRegTransmitterControl);  in nv_mgmt_release_sema()
5328 	writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);  in nv_mgmt_get_version()
5329 	writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);  in nv_mgmt_get_version()
5364 	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);  in nv_open()
5365 	writel(0, base + NvRegMulticastAddrB);  in nv_open()
5366 	writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);  in nv_open()
5367 	writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);  in nv_open()
5368 	writel(0, base + NvRegPacketFilterFlags);  in nv_open()
5370 	writel(0, base + NvRegTransmitterControl);  in nv_open()
5371 	writel(0, base + NvRegReceiverControl);  in nv_open()
5373 	writel(0, base + NvRegAdapterControl);  in nv_open()
5376 		writel(NVREG_TX_PAUSEFRAME_DISABLE,  base + NvRegTxPauseFrame);  in nv_open()
5382 	writel(0, base + NvRegLinkSpeed);  in nv_open()
5383 …writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll…  in nv_open()
5385 	writel(0, base + NvRegUnknownSetupReg6);  in nv_open()
5391 …writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSH…  in nv_open()
5394 	writel(np->linkspeed, base + NvRegLinkSpeed);  in nv_open()
5396 		writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);  in nv_open()
5398 		writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);  in nv_open()
5399 	writel(np->txrxctl_bits, base + NvRegTxRxControl);  in nv_open()
5400 	writel(np->vlanctl_bits, base + NvRegVlanControl);  in nv_open()
5402 	writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);  in nv_open()
5409 	writel(0, base + NvRegMIIMask);  in nv_open()
5410 	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);  in nv_open()
5411 	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);  in nv_open()
5413 	writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);  in nv_open()
5414 	writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);  in nv_open()
5415 	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);  in nv_open()
5416 	writel(np->rx_buf_sz, base + NvRegOffloadConfig);  in nv_open()
5418 	writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);  in nv_open()
5423 		writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);  in nv_open()
5427 			writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);  in nv_open()
5429 			writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);  in nv_open()
5433 	writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);  in nv_open()
5434 	writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);  in nv_open()
5437 			writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);  in nv_open()
5439 			writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);  in nv_open()
5441 		writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);  in nv_open()
5442 	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);  in nv_open()
5443 	writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,  in nv_open()
5445 	writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);  in nv_open()
5446 	writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);  in nv_open()
5448 		writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);  in nv_open()
5452 		writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);  in nv_open()
5456 	writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);  in nv_open()
5460 	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);  in nv_open()
5461 	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);  in nv_open()
5471 	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);  in nv_open()
5472 	writel(0, base + NvRegMulticastAddrB);  in nv_open()
5473 	writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);  in nv_open()
5474 	writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);  in nv_open()
5475 	writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);  in nv_open()
5482 		writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);  in nv_open()
5554 		writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);  in nv_close()
5811 		writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);  in nv_probe()
5834 	writel(0, base + NvRegWakeUpFlags);  in nv_probe()
5846 		writel(powerstate, base + NvRegPowerState2);  in nv_probe()
5902 	writel(0, base + NvRegMIIMask);  in nv_probe()
5907 		writel(phystate, base + NvRegAdapterControl);  in nv_probe()
5909 	writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);  in nv_probe()
6027 		writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);  in nv_probe()
6073 	writel(np->orig_mac[0], base + NvRegMacAddrA);  in nv_restore_mac_addr()
6074 	writel(np->orig_mac[1], base + NvRegMacAddrB);  in nv_restore_mac_addr()
6075 	writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,  in nv_restore_mac_addr()
6132 		writel(np->saved_config_space[i], base+i*sizeof(u32));  in nv_resume()