97 		writel(hwirq, main_int_base +  in armada_370_xp_irq_mask()
100 		writel(hwirq, per_cpu_int_base +  in armada_370_xp_irq_mask()
109 		writel(hwirq, main_int_base +  in armada_370_xp_irq_unmask()
112 		writel(hwirq, per_cpu_int_base +  in armada_370_xp_irq_unmask()
242 	writel(reg, per_cpu_int_base +  in armada_370_xp_msi_init()
246 	writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_370_xp_msi_init()
275 	writel(reg, main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq));  in armada_xp_set_affinity()
298 		writel(hw, per_cpu_int_base +  in armada_370_xp_mpic_irq_map()
301 		writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);  in armada_370_xp_mpic_irq_map()
328 		writel(i, per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);  in armada_xp_mpic_smp_cpu_init()
331 	writel(0, per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);  in armada_xp_mpic_smp_cpu_init()
334 	writel(IPI_DOORBELL_MASK, per_cpu_int_base +  in armada_xp_mpic_smp_cpu_init()
338 	writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_xp_mpic_smp_cpu_init()
346 	writel(ARMADA_370_XP_INT_CAUSE_PERF(cpuid),  in armada_xp_mpic_perf_init()
368 	writel((map << 8) | irq, main_int_base +  in armada_mpic_send_doorbell()
419 	writel(~msimask, per_cpu_int_base +  in armada_370_xp_handle_msi_irq()
509 			writel(~ipimask, per_cpu_int_base +  in armada_370_xp_handle_irq()
548 			writel(irq, per_cpu_int_base +  in armada_370_xp_mpic_resume()
551 			writel(irq, main_int_base +  in armada_370_xp_mpic_resume()
560 	writel(doorbell_mask_reg,  in armada_370_xp_mpic_resume()
563 		writel(0, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_370_xp_mpic_resume()
565 		writel(1, per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);  in armada_370_xp_mpic_resume()
602 		writel(i, main_int_base + ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS);  in armada_370_xp_mpic_of_init()