Lines Matching refs:writel
144 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
172 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
211 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
214 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
229 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
261 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
268 writel(reg_val_GCR | SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
298 writel(reg_val_MCR | (mcfg->tx_multichannel_enable ? in configure_multichannel()
301 writel(mcfg->tx_channel_0_enable, in configure_multichannel()
303 writel(mcfg->tx_channel_1_enable, in configure_multichannel()
305 writel(mcfg->tx_channel_2_enable, in configure_multichannel()
307 writel(mcfg->tx_channel_3_enable, in configure_multichannel()
319 writel(reg_val_MCR | (mcfg->rx_multichannel_enable ? in configure_multichannel()
322 writel(mcfg->rx_channel_0_enable, in configure_multichannel()
324 writel(mcfg->rx_channel_1_enable, in configure_multichannel()
326 writel(mcfg->rx_channel_2_enable, in configure_multichannel()
328 writel(mcfg->rx_channel_3_enable, in configure_multichannel()
338 writel(reg_val_MCR | in configure_multichannel()
342 writel(mcfg->comparison_mask, in configure_multichannel()
344 writel(mcfg->comparison_value, in configure_multichannel()
388 writel(reg_val_DMACR, msp->registers + MSP_DMACR); in enable_msp()
390 writel(config->iodelay, msp->registers + MSP_IODLY); in enable_msp()
394 writel(reg_val_GCR | FRAME_GEN_ENABLE, msp->registers + MSP_GCR); in enable_msp()
405 writel(reg_val_GCR | RX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_rx()
413 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_rx()
422 writel(reg_val_GCR | TX_ENABLE, msp->registers + MSP_GCR); in flush_fifo_tx()
423 writel(MSP_ITCR_ITEN | MSP_ITCR_TESTFIFO, msp->registers + MSP_ITCR); in flush_fifo_tx()
430 writel(0x0, msp->registers + MSP_ITCR); in flush_fifo_tx()
431 writel(reg_val_GCR, msp->registers + MSP_GCR); in flush_fifo_tx()
485 writel(new_reg, msp->registers + MSP_GCR); in ux500_msp_i2s_open()
509 writel(reg_val_GCR & ~RX_ENABLE, msp->registers + MSP_GCR); in disable_msp_rx()
511 writel(reg_val_DMACR & ~RX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_rx()
513 writel(reg_val_IMSC & in disable_msp_rx()
525 writel(reg_val_GCR & ~TX_ENABLE, msp->registers + MSP_GCR); in disable_msp_tx()
527 writel(reg_val_DMACR & ~TX_DMA_ENABLE, msp->registers + MSP_DMACR); in disable_msp_tx()
529 writel(reg_val_IMSC & in disable_msp_tx()
547 writel(reg_val_GCR | LOOPBACK_MASK, in disable_msp()
554 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
561 writel((readl(msp->registers + MSP_GCR) & in disable_msp()
594 writel(reg_val_GCR | enable_bit, msp->registers + MSP_GCR); in ux500_msp_i2s_trigger()
623 writel((readl(msp->registers + MSP_GCR) & in ux500_msp_i2s_close()
627 writel(0, msp->registers + MSP_GCR); in ux500_msp_i2s_close()
628 writel(0, msp->registers + MSP_TCF); in ux500_msp_i2s_close()
629 writel(0, msp->registers + MSP_RCF); in ux500_msp_i2s_close()
630 writel(0, msp->registers + MSP_DMACR); in ux500_msp_i2s_close()
631 writel(0, msp->registers + MSP_SRG); in ux500_msp_i2s_close()
632 writel(0, msp->registers + MSP_MCR); in ux500_msp_i2s_close()
633 writel(0, msp->registers + MSP_RCM); in ux500_msp_i2s_close()
634 writel(0, msp->registers + MSP_RCV); in ux500_msp_i2s_close()
635 writel(0, msp->registers + MSP_TCE0); in ux500_msp_i2s_close()
636 writel(0, msp->registers + MSP_TCE1); in ux500_msp_i2s_close()
637 writel(0, msp->registers + MSP_TCE2); in ux500_msp_i2s_close()
638 writel(0, msp->registers + MSP_TCE3); in ux500_msp_i2s_close()
639 writel(0, msp->registers + MSP_RCE0); in ux500_msp_i2s_close()
640 writel(0, msp->registers + MSP_RCE1); in ux500_msp_i2s_close()
641 writel(0, msp->registers + MSP_RCE2); in ux500_msp_i2s_close()
642 writel(0, msp->registers + MSP_RCE3); in ux500_msp_i2s_close()