1/*
2 * drivers/clocksource/arm_global_timer.c
3 *
4 * Copyright (C) 2013 STMicroelectronics (R&D) Limited.
5 * Author: Stuart Menefy <stuart.menefy@st.com>
6 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/clocksource.h>
16#include <linux/clockchips.h>
17#include <linux/cpu.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/io.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <linux/sched_clock.h>
25
26#include <asm/cputype.h>
27
28#define GT_COUNTER0	0x00
29#define GT_COUNTER1	0x04
30
31#define GT_CONTROL	0x08
32#define GT_CONTROL_TIMER_ENABLE		BIT(0)  /* this bit is NOT banked */
33#define GT_CONTROL_COMP_ENABLE		BIT(1)	/* banked */
34#define GT_CONTROL_IRQ_ENABLE		BIT(2)	/* banked */
35#define GT_CONTROL_AUTO_INC		BIT(3)	/* banked */
36
37#define GT_INT_STATUS	0x0c
38#define GT_INT_STATUS_EVENT_FLAG	BIT(0)
39
40#define GT_COMP0	0x10
41#define GT_COMP1	0x14
42#define GT_AUTO_INC	0x18
43
44/*
45 * We are expecting to be clocked by the ARM peripheral clock.
46 *
47 * Note: it is assumed we are using a prescaler value of zero, so this is
48 * the units for all operations.
49 */
50static void __iomem *gt_base;
51static unsigned long gt_clk_rate;
52static int gt_ppi;
53static struct clock_event_device __percpu *gt_evt;
54
55/*
56 * To get the value from the Global Timer Counter register proceed as follows:
57 * 1. Read the upper 32-bit timer counter register
58 * 2. Read the lower 32-bit timer counter register
59 * 3. Read the upper 32-bit timer counter register again. If the value is
60 *  different to the 32-bit upper value read previously, go back to step 2.
61 *  Otherwise the 64-bit timer counter value is correct.
62 */
63static u64 notrace _gt_counter_read(void)
64{
65	u64 counter;
66	u32 lower;
67	u32 upper, old_upper;
68
69	upper = readl_relaxed(gt_base + GT_COUNTER1);
70	do {
71		old_upper = upper;
72		lower = readl_relaxed(gt_base + GT_COUNTER0);
73		upper = readl_relaxed(gt_base + GT_COUNTER1);
74	} while (upper != old_upper);
75
76	counter = upper;
77	counter <<= 32;
78	counter |= lower;
79	return counter;
80}
81
82static u64 gt_counter_read(void)
83{
84	return _gt_counter_read();
85}
86
87/**
88 * To ensure that updates to comparator value register do not set the
89 * Interrupt Status Register proceed as follows:
90 * 1. Clear the Comp Enable bit in the Timer Control Register.
91 * 2. Write the lower 32-bit Comparator Value Register.
92 * 3. Write the upper 32-bit Comparator Value Register.
93 * 4. Set the Comp Enable bit and, if necessary, the IRQ enable bit.
94 */
95static void gt_compare_set(unsigned long delta, int periodic)
96{
97	u64 counter = gt_counter_read();
98	unsigned long ctrl;
99
100	counter += delta;
101	ctrl = GT_CONTROL_TIMER_ENABLE;
102	writel(ctrl, gt_base + GT_CONTROL);
103	writel(lower_32_bits(counter), gt_base + GT_COMP0);
104	writel(upper_32_bits(counter), gt_base + GT_COMP1);
105
106	if (periodic) {
107		writel(delta, gt_base + GT_AUTO_INC);
108		ctrl |= GT_CONTROL_AUTO_INC;
109	}
110
111	ctrl |= GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE;
112	writel(ctrl, gt_base + GT_CONTROL);
113}
114
115static int gt_clockevent_shutdown(struct clock_event_device *evt)
116{
117	unsigned long ctrl;
118
119	ctrl = readl(gt_base + GT_CONTROL);
120	ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
121		  GT_CONTROL_AUTO_INC);
122	writel(ctrl, gt_base + GT_CONTROL);
123	return 0;
124}
125
126static int gt_clockevent_set_periodic(struct clock_event_device *evt)
127{
128	gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
129	return 0;
130}
131
132static int gt_clockevent_set_next_event(unsigned long evt,
133					struct clock_event_device *unused)
134{
135	gt_compare_set(evt, 0);
136	return 0;
137}
138
139static irqreturn_t gt_clockevent_interrupt(int irq, void *dev_id)
140{
141	struct clock_event_device *evt = dev_id;
142
143	if (!(readl_relaxed(gt_base + GT_INT_STATUS) &
144				GT_INT_STATUS_EVENT_FLAG))
145		return IRQ_NONE;
146
147	/**
148	 * ERRATA 740657( Global Timer can send 2 interrupts for
149	 * the same event in single-shot mode)
150	 * Workaround:
151	 *	Either disable single-shot mode.
152	 *	Or
153	 *	Modify the Interrupt Handler to avoid the
154	 *	offending sequence. This is achieved by clearing
155	 *	the Global Timer flag _after_ having incremented
156	 *	the Comparator register	value to a higher value.
157	 */
158	if (clockevent_state_oneshot(evt))
159		gt_compare_set(ULONG_MAX, 0);
160
161	writel_relaxed(GT_INT_STATUS_EVENT_FLAG, gt_base + GT_INT_STATUS);
162	evt->event_handler(evt);
163
164	return IRQ_HANDLED;
165}
166
167static int gt_clockevents_init(struct clock_event_device *clk)
168{
169	int cpu = smp_processor_id();
170
171	clk->name = "arm_global_timer";
172	clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
173		CLOCK_EVT_FEAT_PERCPU;
174	clk->set_state_shutdown = gt_clockevent_shutdown;
175	clk->set_state_periodic = gt_clockevent_set_periodic;
176	clk->set_state_oneshot = gt_clockevent_shutdown;
177	clk->set_next_event = gt_clockevent_set_next_event;
178	clk->cpumask = cpumask_of(cpu);
179	clk->rating = 300;
180	clk->irq = gt_ppi;
181	clockevents_config_and_register(clk, gt_clk_rate,
182					1, 0xffffffff);
183	enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
184	return 0;
185}
186
187static void gt_clockevents_stop(struct clock_event_device *clk)
188{
189	gt_clockevent_shutdown(clk);
190	disable_percpu_irq(clk->irq);
191}
192
193static cycle_t gt_clocksource_read(struct clocksource *cs)
194{
195	return gt_counter_read();
196}
197
198static struct clocksource gt_clocksource = {
199	.name	= "arm_global_timer",
200	.rating	= 300,
201	.read	= gt_clocksource_read,
202	.mask	= CLOCKSOURCE_MASK(64),
203	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
204};
205
206#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
207static u64 notrace gt_sched_clock_read(void)
208{
209	return _gt_counter_read();
210}
211#endif
212
213static void __init gt_clocksource_init(void)
214{
215	writel(0, gt_base + GT_CONTROL);
216	writel(0, gt_base + GT_COUNTER0);
217	writel(0, gt_base + GT_COUNTER1);
218	/* enables timer on all the cores */
219	writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
220
221#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
222	sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
223#endif
224	clocksource_register_hz(&gt_clocksource, gt_clk_rate);
225}
226
227static int gt_cpu_notify(struct notifier_block *self, unsigned long action,
228			 void *hcpu)
229{
230	switch (action & ~CPU_TASKS_FROZEN) {
231	case CPU_STARTING:
232		gt_clockevents_init(this_cpu_ptr(gt_evt));
233		break;
234	case CPU_DYING:
235		gt_clockevents_stop(this_cpu_ptr(gt_evt));
236		break;
237	}
238
239	return NOTIFY_OK;
240}
241static struct notifier_block gt_cpu_nb = {
242	.notifier_call = gt_cpu_notify,
243};
244
245static void __init global_timer_of_register(struct device_node *np)
246{
247	struct clk *gt_clk;
248	int err = 0;
249
250	/*
251	 * In A9 r2p0 the comparators for each processor with the global timer
252	 * fire when the timer value is greater than or equal to. In previous
253	 * revisions the comparators fired when the timer value was equal to.
254	 */
255	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9
256	    && (read_cpuid_id() & 0xf0000f) < 0x200000) {
257		pr_warn("global-timer: non support for this cpu version.\n");
258		return;
259	}
260
261	gt_ppi = irq_of_parse_and_map(np, 0);
262	if (!gt_ppi) {
263		pr_warn("global-timer: unable to parse irq\n");
264		return;
265	}
266
267	gt_base = of_iomap(np, 0);
268	if (!gt_base) {
269		pr_warn("global-timer: invalid base address\n");
270		return;
271	}
272
273	gt_clk = of_clk_get(np, 0);
274	if (!IS_ERR(gt_clk)) {
275		err = clk_prepare_enable(gt_clk);
276		if (err)
277			goto out_unmap;
278	} else {
279		pr_warn("global-timer: clk not found\n");
280		err = -EINVAL;
281		goto out_unmap;
282	}
283
284	gt_clk_rate = clk_get_rate(gt_clk);
285	gt_evt = alloc_percpu(struct clock_event_device);
286	if (!gt_evt) {
287		pr_warn("global-timer: can't allocate memory\n");
288		err = -ENOMEM;
289		goto out_clk;
290	}
291
292	err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
293				 "gt", gt_evt);
294	if (err) {
295		pr_warn("global-timer: can't register interrupt %d (%d)\n",
296			gt_ppi, err);
297		goto out_free;
298	}
299
300	err = register_cpu_notifier(&gt_cpu_nb);
301	if (err) {
302		pr_warn("global-timer: unable to register cpu notifier.\n");
303		goto out_irq;
304	}
305
306	/* Immediately configure the timer on the boot CPU */
307	gt_clocksource_init();
308	gt_clockevents_init(this_cpu_ptr(gt_evt));
309
310	return;
311
312out_irq:
313	free_percpu_irq(gt_ppi, gt_evt);
314out_free:
315	free_percpu(gt_evt);
316out_clk:
317	clk_disable_unprepare(gt_clk);
318out_unmap:
319	iounmap(gt_base);
320	WARN(err, "ARM Global timer register failed (%d)\n", err);
321}
322
323/* Only tested on r2p2 and r3p0  */
324CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
325			global_timer_of_register);
326