302 			writel(s->port.x_char,  in mxs_auart_tx_chars()
309 			writel(xmit->buf[xmit->tail],  in mxs_auart_tx_chars()
319 		writel(AUART_INTR_TXIEN,  in mxs_auart_tx_chars()
322 		writel(AUART_INTR_TXIEN,  in mxs_auart_tx_chars()
371 	writel(stat, s->port.membase + AUART_STAT);  in mxs_auart_rx_char()
385 	writel(stat, s->port.membase + AUART_STAT);  in mxs_auart_rx_chars()
431 	writel(ctrl, u->membase + AUART_CTRL2);  in mxs_auart_set_mctrl()
546 	writel(stat, s->port.membase + AUART_STAT);  in dma_rx_callback()
609 	writel(AUART_CTRL2_TXDMAE | AUART_CTRL2_RXDMAE | AUART_CTRL2_DMAONERR,  in mxs_auart_dma_exit()
764 	writel(ctrl, u->membase + AUART_LINECTRL);  in mxs_auart_settermios()
765 	writel(ctrl2, u->membase + AUART_CTRL2);  in mxs_auart_settermios()
774 			writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN,  in mxs_auart_settermios()
810 	writel(istat & (AUART_INTR_RTIS  in mxs_auart_irq_handle()
830 		writel(AUART_INTR_CTSMIS,  in mxs_auart_irq_handle()
854 	writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_CLR);  in mxs_auart_reset_deassert()
862 	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);  in mxs_auart_reset_deassert()
875 	writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);  in mxs_auart_reset_assert()
876 	writel(AUART_CTRL0_SFTRST, u->membase + AUART_CTRL0_SET);  in mxs_auart_reset_assert()
899 		writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_CLR);  in mxs_auart_startup()
906 	writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_SET);  in mxs_auart_startup()
908 	writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,  in mxs_auart_startup()
918 	writel(AUART_LINECTRL_FEN, u->membase + AUART_LINECTRL_SET);  in mxs_auart_startup()
937 		writel(AUART_CTRL2_UARTEN, u->membase + AUART_CTRL2_CLR);  in mxs_auart_shutdown()
938 		writel(AUART_INTR_RXIEN | AUART_INTR_RTIEN | AUART_INTR_CTSMIEN,  in mxs_auart_shutdown()
940 		writel(AUART_CTRL0_CLKGATE, u->membase + AUART_CTRL0_SET);  in mxs_auart_shutdown()
962 	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_SET);  in mxs_auart_start_tx()
969 	writel(AUART_CTRL2_TXE, u->membase + AUART_CTRL2_CLR);  in mxs_auart_stop_tx()
974 	writel(AUART_CTRL2_RXE, u->membase + AUART_CTRL2_CLR);  in mxs_auart_stop_rx()
980 		writel(AUART_LINECTRL_BRK,  in mxs_auart_break_ctl()
983 		writel(AUART_LINECTRL_BRK,  in mxs_auart_break_ctl()
1020 	writel(ch, port->membase + AUART_DATA);  in mxs_auart_console_putchar()
1043 	writel(AUART_CTRL0_CLKGATE,  in auart_console_write()
1045 	writel(AUART_CTRL2_UARTEN | AUART_CTRL2_TXE,  in auart_console_write()
1064 		writel(old_ctrl0, port->membase + AUART_CTRL0);  in auart_console_write()
1065 		writel(old_ctrl2, port->membase + AUART_CTRL2);  in auart_console_write()