584 	writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);  in db8500_prcmu_enable_dsipll()
586 	writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);  in db8500_prcmu_enable_dsipll()
589 	writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);  in db8500_prcmu_enable_dsipll()
590 	writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);  in db8500_prcmu_enable_dsipll()
592 	writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);  in db8500_prcmu_enable_dsipll()
595 	writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);  in db8500_prcmu_enable_dsipll()
597 	writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);  in db8500_prcmu_enable_dsipll()
605 	writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);  in db8500_prcmu_enable_dsipll()
612 	writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);  in db8500_prcmu_disable_dsipll()
614 	writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);  in db8500_prcmu_disable_dsipll()
628 	writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT);  in db8500_prcmu_set_display_clocks()
629 	writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT);  in db8500_prcmu_set_display_clocks()
630 	writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT);  in db8500_prcmu_set_display_clocks()
633 	writel(0, PRCM_SEM);  in db8500_prcmu_set_display_clocks()
650 	writel(value, (prcmu_base + reg));  in db8500_prcmu_write()
662 	writel(val, (prcmu_base + reg));  in db8500_prcmu_write_masked()
775 	writel((bits | (val & ~mask)), PRCM_CLKOCR);  in prcmu_config_clkout()
801 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_power_state()
837 		writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));  in config_wakeups()
838 		writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));  in config_wakeups()
840 		writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in config_wakeups()
912 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_arm_opp()
999 		writel(val, prcmu_base + clock_reg[i]);  in request_even_slower_clocks()
1004 	writel(0, PRCM_SEM);  in request_even_slower_clocks()
1039 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_ape_opp()
1101 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_request_ape_opp_100_voltage()
1131 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in prcmu_release_usb_wakeup_state()
1162 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in request_pll()
1218 	writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);  in db8500_prcmu_set_epod()
1276 	writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));  in prcmu_configure_auto_pm()
1277 	writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));  in prcmu_configure_auto_pm()
1311 	writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);  in request_sysclk()
1337 	writel(val, PRCM_TCR);  in request_timclk()
1360 	writel(val, prcmu_base + clk_mgt[clock].offset);  in request_clock()
1363 	writel(0, PRCM_SEM);  in request_clock()
1377 		writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);  in request_sga_clock()
1384 		writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);  in request_sga_clock()
1404 	writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |  in request_plldsi()
1413 	writel(val, PRCM_PLLDSI_ENABLE);  in request_plldsi()
1424 			writel(PRCM_APE_RESETN_DSIPLL_RESETN,  in request_plldsi()
1427 			writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |  in request_plldsi()
1431 			writel(val, PRCM_PLLDSI_ENABLE);  in request_plldsi()
1435 		writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);  in request_plldsi()
1448 	writel(val, PRCM_DSI_PLLOUT_SEL);  in request_dsiclk()
1458 	writel(val, PRCM_DSITVCLK_DIV);  in request_dsiescclk()
1869 	writel(val, prcmu_base + clk_mgt[clock].offset);  in set_clock_rate()
1872 	writel(0, PRCM_SEM);  in set_clock_rate()
1937 	writel(pll_freq, PRCM_PLLDSI_FREQ);  in set_plldsi_rate()
1957 	writel(val, PRCM_DSI_PLLOUT_SEL);  in set_dsiclk_rate()
1969 	writel(val, PRCM_DSITVCLK_DIV);  in set_dsiescclk_rate()
2005 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_esram0_deep_sleep()
2023 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotdog()
2044 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in db8500_prcmu_config_hotmon()
2062 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in config_hot_period()
2098 	writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);  in prcmu_a9wdog()
2180 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_read()
2230 	writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);  in prcmu_abb_write_masked()
2285 	writel(val, PRCM_HOSTACCESS_REQ);  in prcmu_ac_wake_req()
2290 	writel(val, PRCM_HOSTACCESS_REQ);  in prcmu_ac_wake_req()
2317 	writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),  in prcmu_ac_sleep_req()
2346 	writel(1, PRCM_APE_SOFTRST);  in db8500_prcmu_system_reset()
2371 	writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);  in db8500_prcmu_modem_reset()
2392 	writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);  in ack_dbb_wakeup()
2437 	writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);  in read_mailbox_0()
2450 	writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);  in read_mailbox_1()
2458 	writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);  in read_mailbox_2()
2465 	writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);  in read_mailbox_3()
2492 	writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);  in read_mailbox_4()
2504 	writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);  in read_mailbox_5()
2511 	writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);  in read_mailbox_6()
2517 	writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);  in read_mailbox_7()
2765 	writel(val, (PRCM_A9PL_FORCE_CLKEN));  in init_prcm_registers()
3167 	writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);  in db8500_prcmu_probe()