755 	writel(csr, &adapter->regs->rxdma.csr);  in et131x_rx_dma_enable()
773 	writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,  in et131x_rx_dma_disable()
791 	writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),  in et131x_tx_dma_enable()
815 	writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET  |  in et1310_config_mac_regs1()
823 	writel(ipg, &macregs->ipg);  in et1310_config_mac_regs1()
827 	writel(0x00A1F037, &macregs->hfdp);  in et1310_config_mac_regs1()
830 	writel(0, &macregs->if_ctrl);  in et1310_config_mac_regs1()
832 	writel(ET_MAC_MIIMGMT_CLK_RST, &macregs->mii_mgmt_cfg);  in et1310_config_mac_regs1()
847 	writel(station1, &macregs->station_addr_1);  in et1310_config_mac_regs1()
848 	writel(station2, &macregs->station_addr_2);  in et1310_config_mac_regs1()
857 	writel(adapter->registry_jumbo_packet + 4, &macregs->max_fm_len);  in et1310_config_mac_regs1()
860 	writel(0, &macregs->cfg1);  in et1310_config_mac_regs1()
894 	writel(cfg1, &mac->cfg1);  in et1310_config_mac_regs2()
914 	writel(ifctrl, &mac->if_ctrl);  in et1310_config_mac_regs2()
915 	writel(cfg2, &mac->cfg2);  in et1310_config_mac_regs2()
930 	writel(ctl, &adapter->regs->txmac.ctl);  in et1310_config_mac_regs2()
988 		writel(hash1, &rxmac->multi_hash1);  in et1310_setup_device_for_multicast()
989 		writel(hash2, &rxmac->multi_hash2);  in et1310_setup_device_for_multicast()
990 		writel(hash3, &rxmac->multi_hash3);  in et1310_setup_device_for_multicast()
991 		writel(hash4, &rxmac->multi_hash4);  in et1310_setup_device_for_multicast()
1029 		writel(uni_pf1, &rxmac->uni_pf_addr1);  in et1310_setup_device_for_unicast()
1030 		writel(uni_pf2, &rxmac->uni_pf_addr2);  in et1310_setup_device_for_unicast()
1031 		writel(uni_pf3, &rxmac->uni_pf_addr3);  in et1310_setup_device_for_unicast()
1045 	writel(0x8, &rxmac->ctrl);  in et1310_config_rxmac_regs()
1048 	writel(0, &rxmac->crc0);  in et1310_config_rxmac_regs()
1049 	writel(0, &rxmac->crc12);  in et1310_config_rxmac_regs()
1050 	writel(0, &rxmac->crc34);  in et1310_config_rxmac_regs()
1057 		writel(0, wolw);  in et1310_config_rxmac_regs()
1064 	writel(sa_lo, &rxmac->sa_lo);  in et1310_config_rxmac_regs()
1068 	writel(sa_hi, &rxmac->sa_hi);  in et1310_config_rxmac_regs()
1071 	writel(0, &rxmac->pf_ctrl);  in et1310_config_rxmac_regs()
1078 		writel(0, &rxmac->uni_pf_addr1);  in et1310_config_rxmac_regs()
1079 		writel(0, &rxmac->uni_pf_addr2);  in et1310_config_rxmac_regs()
1080 		writel(0, &rxmac->uni_pf_addr3);  in et1310_config_rxmac_regs()
1104 		writel(0x41, &rxmac->mcif_ctrl_max_seg);  in et1310_config_rxmac_regs()
1106 		writel(0, &rxmac->mcif_ctrl_max_seg);  in et1310_config_rxmac_regs()
1108 	writel(0, &rxmac->mcif_water_mark);  in et1310_config_rxmac_regs()
1109 	writel(0, &rxmac->mif_ctrl);  in et1310_config_rxmac_regs()
1110 	writel(0, &rxmac->space_avail);  in et1310_config_rxmac_regs()
1126 		writel(0x30038, &rxmac->mif_ctrl);  in et1310_config_rxmac_regs()
1128 		writel(0x30030, &rxmac->mif_ctrl);  in et1310_config_rxmac_regs()
1136 	writel(pf_ctrl, &rxmac->pf_ctrl);  in et1310_config_rxmac_regs()
1137 	writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);  in et1310_config_rxmac_regs()
1149 		writel(0, &txmac->cf_param);  in et1310_config_txmac_regs()
1151 		writel(0x40, &txmac->cf_param);  in et1310_config_txmac_regs()
1162 		writel(0, reg);  in et1310_config_macstat_regs()
1168 	writel(0xFFFFBE32, &macstat->carry_reg1_mask);  in et1310_config_macstat_regs()
1169 	writel(0xFFFE7E8B, &macstat->carry_reg2_mask);  in et1310_config_macstat_regs()
1189 	writel(0, &mac->mii_mgmt_cmd);  in et131x_phy_mii_read()
1192 	writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);  in et131x_phy_mii_read()
1194 	writel(0x1, &mac->mii_mgmt_cmd);  in et131x_phy_mii_read()
1220 	writel(0, &mac->mii_mgmt_cmd);  in et131x_phy_mii_read()
1225 	writel(mii_addr, &mac->mii_mgmt_addr);  in et131x_phy_mii_read()
1226 	writel(mii_cmd, &mac->mii_mgmt_cmd);  in et131x_phy_mii_read()
1258 	writel(0, &mac->mii_mgmt_cmd);  in et131x_mii_write()
1261 	writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);  in et131x_mii_write()
1264 	writel(value, &mac->mii_mgmt_ctrl);  in et131x_mii_write()
1288 	writel(0, &mac->mii_mgmt_cmd);  in et131x_mii_write()
1293 	writel(mii_addr, &mac->mii_mgmt_addr);  in et131x_mii_write()
1294 	writel(mii_cmd, &mac->mii_mgmt_cmd);  in et131x_mii_write()
1384 	writel(carry_reg1, &adapter->regs->macstat.carry_reg1);  in et1310_handle_macstat_interrupt()
1385 	writel(carry_reg2, &adapter->regs->macstat.carry_reg2);  in et1310_handle_macstat_interrupt()
1502 	writel(0, &regs->rxq_start_addr);  in et131x_configure_global_regs()
1503 	writel(INTERNAL_MEM_SIZE - 1, &regs->txq_end_addr);  in et131x_configure_global_regs()
1511 		writel(PARM_RX_MEM_END_DEF, &regs->rxq_end_addr);  in et131x_configure_global_regs()
1512 		writel(PARM_RX_MEM_END_DEF + 1, &regs->txq_start_addr);  in et131x_configure_global_regs()
1515 		writel(INTERNAL_MEM_RX_OFFSET, &regs->rxq_end_addr);  in et131x_configure_global_regs()
1516 		writel(INTERNAL_MEM_RX_OFFSET + 1, &regs->txq_start_addr);  in et131x_configure_global_regs()
1523 		writel(0x01b3, &regs->rxq_end_addr);  in et131x_configure_global_regs()
1524 		writel(0x01b4, &regs->txq_start_addr);  in et131x_configure_global_regs()
1528 	writel(0, &regs->loopback);  in et131x_configure_global_regs()
1530 	writel(0, &regs->msi_config);  in et131x_configure_global_regs()
1535 	writel(0, &regs->watchdog_timer);  in et131x_configure_global_regs()
1552 	writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);  in et131x_config_rx_dma_regs()
1553 	writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);  in et131x_config_rx_dma_regs()
1558 	writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);  in et131x_config_rx_dma_regs()
1559 	writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);  in et131x_config_rx_dma_regs()
1560 	writel(rx_local->psr_entries - 1, &rx_dma->psr_num_des);  in et131x_config_rx_dma_regs()
1561 	writel(0, &rx_dma->psr_full_offset);  in et131x_config_rx_dma_regs()
1564 	writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,  in et131x_config_rx_dma_regs()
1604 		writel(upper_32_bits(fbr->ring_physaddr), base_hi);  in et131x_config_rx_dma_regs()
1605 		writel(lower_32_bits(fbr->ring_physaddr), base_lo);  in et131x_config_rx_dma_regs()
1606 		writel(fbr->num_entries - 1, num_des);  in et131x_config_rx_dma_regs()
1607 		writel(ET_DMA10_WRAP, full_offset);  in et131x_config_rx_dma_regs()
1613 		writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,  in et131x_config_rx_dma_regs()
1622 	writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);  in et131x_config_rx_dma_regs()
1629 	writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);  in et131x_config_rx_dma_regs()
1645 	writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);  in et131x_config_tx_dma_regs()
1646 	writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);  in et131x_config_tx_dma_regs()
1649 	writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);  in et131x_config_tx_dma_regs()
1652 	writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);  in et131x_config_tx_dma_regs()
1653 	writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);  in et131x_config_tx_dma_regs()
1657 	writel(0, &txdma->service_request);  in et131x_config_tx_dma_regs()
1669 	writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);  in et131x_adapter_setup()
1692 	writel(reg, &adapter->regs->mac.cfg1);  in et131x_soft_reset()
1695 	writel(reg, &adapter->regs->global.sw_reset);  in et131x_soft_reset()
1699 	writel(reg, &adapter->regs->mac.cfg1);  in et131x_soft_reset()
1700 	writel(0, &adapter->regs->mac.cfg1);  in et131x_soft_reset()
1712 	writel(mask, &adapter->regs->global.int_mask);  in et131x_enable_interrupts()
1717 	writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);  in et131x_disable_interrupts()
1723 	writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,  in et131x_tx_dma_disable()
1797 	writel(pmcsr, &adapter->regs->global.pm_csr);  in et1310_enable_phy_coma()
1801 	writel(pmcsr, &adapter->regs->global.pm_csr);  in et1310_enable_phy_coma()
1813 	writel(pmcsr, &adapter->regs->global.pm_csr);  in et1310_disable_phy_coma()
2120 		writel(0, &adapter->regs->rxdma.max_pkt_time);  in et131x_set_rx_dma_timer()
2121 		writel(1, &adapter->regs->rxdma.num_pkt_done);  in et131x_set_rx_dma_timer()
2161 		writel(free_buff_ring, offset);  in nic_return_rfd()
2234 	writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);  in nic_rx_pkts()
2339 		writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,  in et131x_handle_recv_pkts()
2575 	writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);  in nic_send_packet()
2581 		writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,  in nic_send_packet()
3437 			writel(0, &adapter->regs->global.watchdog_timer);  in et131x_isr()
3485 				writel(3, &iomem->txmac.bp_ctrl);  in et131x_isr()
3748 		writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);  in et131x_set_packet_filter()
3749 		writel(ctrl, &adapter->regs->rxmac.ctrl);  in et131x_set_packet_filter()
4008 	writel(ET_PMCSR_INIT,  &adapter->regs->global.pm_csr);  in et131x_pci_setup()