215 		writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);  in set_pts()
220 		writel(val, base + TEGRA_USB_PORTSC1);  in set_pts()
235 		writel(val, base + TEGRA_USB_HOSTPC1_DEVLC);  in set_phcd()
242 		writel(val, base + TEGRA_USB_PORTSC1);  in set_phcd()
280 		writel(val, base + UTMIP_BIAS_CFG0);  in utmip_pad_power_on()
305 		writel(val, base + UTMIP_BIAS_CFG0);  in utmip_pad_power_off()
335 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
341 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_disable()
357 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
363 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_clk_enable()
380 	writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
385 		writel(val, base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
390 	writel(val, base + UTMIP_TX_CFG0);  in utmi_phy_power_on()
396 	writel(val, base + UTMIP_HSRX_CFG0);  in utmi_phy_power_on()
401 	writel(val, base + UTMIP_HSRX_CFG1);  in utmi_phy_power_on()
406 	writel(val, base + UTMIP_DEBOUNCE_CFG0);  in utmi_phy_power_on()
410 	writel(val, base + UTMIP_MISC_CFG0);  in utmi_phy_power_on()
418 		writel(val, base + UTMIP_MISC_CFG1);  in utmi_phy_power_on()
425 		writel(val, base + UTMIP_PLL_CFG1);  in utmi_phy_power_on()
431 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
435 		writel(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
439 		writel(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_on()
462 	writel(val, base + UTMIP_XCVR_CFG0);  in utmi_phy_power_on()
468 	writel(val, base + UTMIP_XCVR_CFG1);  in utmi_phy_power_on()
473 	writel(val, base + UTMIP_BIAS_CFG1);  in utmi_phy_power_on()
480 	writel(val, base + UTMIP_SPARE_CFG0);  in utmi_phy_power_on()
485 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
490 	writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
496 		writel(val, base + USB1_LEGACY_CTRL);  in utmi_phy_power_on()
500 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_on()
512 		writel(val, base + USB_USBMODE);  in utmi_phy_power_on()
532 		writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_off()
537 	writel(val, base + USB_SUSP_CTRL);  in utmi_phy_power_off()
541 	writel(val, base + UTMIP_BAT_CHRG_CFG0);  in utmi_phy_power_off()
546 	writel(val, base + UTMIP_XCVR_CFG0);  in utmi_phy_power_off()
551 	writel(val, base + UTMIP_XCVR_CFG1);  in utmi_phy_power_off()
563 	writel(val, base + UTMIP_TX_CFG0);  in utmi_phy_preresume()
573 	writel(val, base + UTMIP_TX_CFG0);  in utmi_phy_postresume()
588 	writel(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
593 	writel(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_start()
604 	writel(val, base + UTMIP_MISC_CFG0);  in utmi_phy_restore_end()
633 	writel(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
637 	writel(val, base + ULPI_TIMING_CTRL_0);  in ulpi_phy_power_on()
641 	writel(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
644 	writel(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
649 	writel(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
655 	writel(val, base + ULPI_TIMING_CTRL_1);  in ulpi_phy_power_on()
672 	writel(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()
677 	writel(val, base + USB_SUSP_CTRL);  in ulpi_phy_power_on()