142 		writel(QUP_RESET_STATE, qup->base + QUP_STATE);  in qup_i2c_interrupt()
151 		writel(qup_err, qup->base + QUP_ERROR_FLAGS);  in qup_i2c_interrupt()
157 		writel(QUP_RESET_STATE, qup->base + QUP_STATE);  in qup_i2c_interrupt()
162 		writel(QUP_IN_SVC_FLAG, qup->base + QUP_OPERATIONAL);  in qup_i2c_interrupt()
165 		writel(QUP_OUT_SVC_FLAG, qup->base + QUP_OPERATIONAL);  in qup_i2c_interrupt()
217 	writel(state, qup->base + QUP_STATE);  in qup_i2c_change_state()
254 		writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);  in qup_i2c_set_write_mode()
255 		writel(total, qup->base + QUP_MX_WRITE_CNT);  in qup_i2c_set_write_mode()
258 		writel(QUP_OUTPUT_BLK_MODE | QUP_REPACK_EN,  in qup_i2c_set_write_mode()
260 		writel(total, qup->base + QUP_MX_OUTPUT_CNT);  in qup_i2c_set_write_mode()
298 			writel(val, qup->base + QUP_OUT_FIFO_BASE);  in qup_i2c_issue_write()
321 	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);  in qup_i2c_write_one()
336 			writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_write_one()
363 		writel(QUP_REPACK_EN, qup->base + QUP_IO_MODE);  in qup_i2c_set_read_mode()
364 		writel(len, qup->base + QUP_MX_READ_CNT);  in qup_i2c_set_read_mode()
367 		writel(QUP_INPUT_BLK_MODE | QUP_REPACK_EN,  in qup_i2c_set_read_mode()
369 		writel(len, qup->base + QUP_MX_INPUT_CNT);  in qup_i2c_set_read_mode()
383 	writel(val, qup->base + QUP_OUT_FIFO_BASE);  in qup_i2c_issue_read()
426 	writel(qup->clk_ctl, qup->base + QUP_I2C_CLK_CTL);  in qup_i2c_read_one()
441 			writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_read_one()
474 	writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_xfer()
480 	writel(I2C_MINI_CORE | I2C_N_VAL, qup->base + QUP_CONFIG);  in qup_i2c_xfer()
549 	writel(config, qup->base + QUP_CONFIG);  in qup_i2c_disable_clocks()
611 	writel(1, qup->base + QUP_SW_RESET);  in qup_i2c_probe()