Lines Matching refs:writel
307 writel(readl(sspi->base + sspi->regs->usp_mode1) & in sirfsoc_usp_hwinit()
309 writel(readl(sspi->base + sspi->regs->usp_mode1) | in sirfsoc_usp_hwinit()
337 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u8()
366 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u16()
396 writel(data, sspi->base + sspi->regs->txfifo_data); in spi_sirfsoc_tx_word_u32()
409 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
410 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
422 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
425 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_irq()
428 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
441 writel(0x0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_irq()
444 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_irq()
447 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_irq()
468 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_cmd_transfer()
469 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_cmd_transfer()
477 writel(cmd, sspi->base + sspi->regs->spi_cmd); in spi_sirfsoc_cmd_transfer()
478 writel(SIRFSOC_SPI_FRM_END_INT_EN, in spi_sirfsoc_cmd_transfer()
480 writel(SIRFSOC_SPI_CMD_TX_EN, in spi_sirfsoc_cmd_transfer()
497 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
498 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
501 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_dma_transfer()
503 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_dma_transfer()
505 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_dma_transfer()
508 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
509 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
510 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_dma_transfer()
513 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
514 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
515 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_dma_transfer()
518 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_dma_transfer()
523 writel(readl(sspi->base + sspi->regs->spi_ctrl) | in spi_sirfsoc_dma_transfer()
527 writel(sspi->left_tx_word - 1, in spi_sirfsoc_dma_transfer()
529 writel(sspi->left_tx_word - 1, in spi_sirfsoc_dma_transfer()
535 writel(sspi->left_tx_word * sspi->word_width, in spi_sirfsoc_dma_transfer()
537 writel(sspi->left_tx_word * sspi->word_width, in spi_sirfsoc_dma_transfer()
543 writel(readl(sspi->base + sspi->regs->spi_ctrl), in spi_sirfsoc_dma_transfer()
545 writel(0, sspi->base + sspi->regs->tx_dma_io_len); in spi_sirfsoc_dma_transfer()
546 writel(0, sspi->base + sspi->regs->rx_dma_io_len); in spi_sirfsoc_dma_transfer()
570 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, in spi_sirfsoc_dma_transfer()
574 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_dma_transfer()
576 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_dma_transfer()
593 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
599 writel(0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_dma_transfer()
600 writel(0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_dma_transfer()
602 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
605 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_dma_transfer()
617 writel(SIRFSOC_SPI_FIFO_RESET, in spi_sirfsoc_pio_transfer()
619 writel(SIRFSOC_SPI_FIFO_RESET, in spi_sirfsoc_pio_transfer()
623 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
624 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
625 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_pio_transfer()
626 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_pio_transfer()
628 writel(min((sspi->left_tx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
631 writel(min((sspi->left_rx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
636 writel(0x0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
637 writel(0x0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
638 writel(~0UL, sspi->base + sspi->regs->usp_int_en_clr); in spi_sirfsoc_pio_transfer()
639 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_pio_transfer()
641 writel(min((sspi->left_tx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
644 writel(min((sspi->left_rx_word * sspi->word_width), in spi_sirfsoc_pio_transfer()
649 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_pio_transfer()
651 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_pio_transfer()
653 writel(0, sspi->base + sspi->regs->int_en); in spi_sirfsoc_pio_transfer()
654 writel(readl(sspi->base + sspi->regs->int_st), in spi_sirfsoc_pio_transfer()
656 writel(readl(sspi->base + sspi->regs->spi_ctrl) | in spi_sirfsoc_pio_transfer()
661 writel(min(sspi->left_tx_word, data_units) - 1, in spi_sirfsoc_pio_transfer()
663 writel(min(sspi->left_rx_word, data_units) - 1, in spi_sirfsoc_pio_transfer()
671 writel(SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN | in spi_sirfsoc_pio_transfer()
676 writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, in spi_sirfsoc_pio_transfer()
680 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_pio_transfer()
682 writel(SIRFSOC_SPI_FIFO_START, in spi_sirfsoc_pio_transfer()
690 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_pio_transfer()
699 writel(0, sspi->base + sspi->regs->tx_rx_en); in spi_sirfsoc_pio_transfer()
700 writel(0, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_pio_transfer()
701 writel(0, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_pio_transfer()
754 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_chipselect()
774 writel(regval, in spi_sirfsoc_chipselect()
835 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, sspi->fifo_size - 2) << in spi_sirfsoc_config_mode()
842 writel((SIRFSOC_SPI_FIFO_LEVEL_CHK_MASK(sspi, 2) << in spi_sirfsoc_config_mode()
856 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_config_mode()
863 writel(usp_mode1, sspi->base + sspi->regs->usp_mode1); in spi_sirfsoc_config_mode()
920 writel(txfifo_ctrl, sspi->base + sspi->regs->txfifo_ctrl); in spi_sirfsoc_setup_transfer()
921 writel(rxfifo_ctrl, sspi->base + sspi->regs->rxfifo_ctrl); in spi_sirfsoc_setup_transfer()
945 writel(tx_frm_ctl | (((usp_mode2 >> 10) & in spi_sirfsoc_setup_transfer()
949 writel(rx_frm_ctl | (((usp_mode2 >> 12) & in spi_sirfsoc_setup_transfer()
953 writel(readl(sspi->base + sspi->regs->usp_mode2) | in spi_sirfsoc_setup_transfer()
963 writel(regval, sspi->base + sspi->regs->spi_ctrl); in spi_sirfsoc_setup_transfer()
969 writel(readl(sspi->base + sspi->regs->spi_ctrl) | in spi_sirfsoc_setup_transfer()
975 writel(readl(sspi->base + sspi->regs->spi_ctrl) & in spi_sirfsoc_setup_transfer()
982 writel(0, sspi->base + sspi->regs->tx_dma_io_ctrl); in spi_sirfsoc_setup_transfer()
983 writel(SIRFSOC_SPI_RX_DMA_FLUSH, in spi_sirfsoc_setup_transfer()
987 writel(SIRFSOC_SPI_IO_MODE_SEL, in spi_sirfsoc_setup_transfer()
989 writel(SIRFSOC_SPI_IO_MODE_SEL, in spi_sirfsoc_setup_transfer()
1214 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_resume()
1215 writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_resume()
1216 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->txfifo_op); in spi_sirfsoc_resume()
1217 writel(SIRFSOC_SPI_FIFO_START, sspi->base + sspi->regs->rxfifo_op); in spi_sirfsoc_resume()