192 		writel(*status & mask, host->base + REG_CLEAR);  in moxart_wait_for_status()
209 	writel(RSP_TIMEOUT  | RSP_CRC_OK |  in moxart_send_command()
211 	writel(cmd->arg, host->base + REG_ARGUMENT);  in moxart_send_command()
225 	writel(cmdctrl | CMD_EN, host->base + REG_COMMAND);  in moxart_send_command()
390 	writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL);  in moxart_prepare_data()
391 	writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR);  in moxart_prepare_data()
392 	writel(host->rate, host->base + REG_DATA_TIMER);  in moxart_prepare_data()
393 	writel(host->data_len, host->base + REG_DATA_LENGTH);  in moxart_prepare_data()
394 	writel(datactrl, host->base + REG_DATA_CONTROL);  in moxart_prepare_data()
421 			writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);  in moxart_request()
430 			writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK);  in moxart_request()
481 		writel(MASK_INTR_PIO, host->base + REG_CLEAR);  in moxart_irq()
482 		writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK);  in moxart_irq()
511 		writel(ctrl, host->base + REG_CLOCK_CONTROL);  in moxart_set_ios()
515 		writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON,  in moxart_set_ios()
523 		writel(SD_POWER_ON | (u32) power,  in moxart_set_ios()
529 		writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH);  in moxart_set_ios()
532 		writel(BUS_WIDTH_8, host->base + REG_BUS_WIDTH);  in moxart_set_ios()
535 		writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH);  in moxart_set_ios()
660 	writel(0, host->base + REG_INTERRUPT_MASK);  in moxart_probe()
662 	writel(CMD_SDC_RESET, host->base + REG_COMMAND);  in moxart_probe()
701 		writel(0, host->base + REG_INTERRUPT_MASK);  in moxart_remove()
702 		writel(0, host->base + REG_POWER_CONTROL);  in moxart_remove()
703 		writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF,  in moxart_remove()