176 		writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |  in bcm_kona_i2c_send_cmd_to_ctrl()
182 		writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |  in bcm_kona_i2c_send_cmd_to_ctrl()
189 		writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |  in bcm_kona_i2c_send_cmd_to_ctrl()
196 		writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |  in bcm_kona_i2c_send_cmd_to_ctrl()
208 	writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,  in bcm_kona_i2c_enable_clock()
214 	writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,  in bcm_kona_i2c_disable_clock()
228 		writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,  in bcm_kona_i2c_isr()
231 	writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);  in bcm_kona_i2c_isr()
264 	writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);  in bcm_kona_send_i2c_cmd()
276 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_send_i2c_cmd()
300 	writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);  in bcm_kona_i2c_read_fifo_single()
303 	writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |  in bcm_kona_i2c_read_fifo_single()
311 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_read_fifo_single()
368 	writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);  in bcm_kona_i2c_write_byte()
371 	writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);  in bcm_kona_i2c_write_byte()
377 	writel(data, dev->base + DAT_OFFSET);  in bcm_kona_i2c_write_byte()
383 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_write_byte()
412 	writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,  in bcm_kona_i2c_write_fifo_single()
420 		writel(buf[k], (dev->base + DAT_OFFSET));  in bcm_kona_i2c_write_fifo_single()
432 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_write_fifo_single()
518 	writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,  in bcm_kona_i2c_enable_autosense()
524 	writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,  in bcm_kona_i2c_config_timing()
527 	writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |  in bcm_kona_i2c_config_timing()
533 	writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |  in bcm_kona_i2c_config_timing()
541 	writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |  in bcm_kona_i2c_config_timing_hs()
547 	writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |  in bcm_kona_i2c_config_timing_hs()
552 	writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,  in bcm_kona_i2c_config_timing_hs()
620 	writel(0, dev->base + PADCTL_OFFSET);  in bcm_kona_i2c_xfer()
696 	writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);  in bcm_kona_i2c_xfer()
805 	writel(0, dev->base + TOUT_OFFSET);  in bcm_kona_i2c_probe()
811 	writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,  in bcm_kona_i2c_probe()
815 	writel(0, dev->base + IER_OFFSET);  in bcm_kona_i2c_probe()
818 	writel(ISR_CMDBUSY_MASK |  in bcm_kona_i2c_probe()
846 	writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);  in bcm_kona_i2c_probe()