101 	writel(reg, flow->base + DP_COM_CONF);  in ipu_dp_set_global_alpha()
105 		writel(reg | ((u32) alpha << 24),  in ipu_dp_set_global_alpha()
109 		writel(reg | DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);  in ipu_dp_set_global_alpha()
112 		writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF);  in ipu_dp_set_global_alpha()
128 	writel((x_pos << 16) | y_pos, flow->base + DP_FG_POS);  in ipu_dp_set_window_pos()
147 		writel(reg, flow->base + DP_COM_CONF);  in ipu_dp_csc_init()
152 		writel(0x099 | (0x12d << 16), flow->base + DP_CSC_A_0);  in ipu_dp_csc_init()
153 		writel(0x03a | (0x3a9 << 16), flow->base + DP_CSC_A_1);  in ipu_dp_csc_init()
154 		writel(0x356 | (0x100 << 16), flow->base + DP_CSC_A_2);  in ipu_dp_csc_init()
155 		writel(0x100 | (0x329 << 16), flow->base + DP_CSC_A_3);  in ipu_dp_csc_init()
156 		writel(0x3d6 | (0x0000 << 16) | (2 << 30),  in ipu_dp_csc_init()
158 		writel(0x200 | (2 << 14) | (0x200 << 16) | (2 << 30),  in ipu_dp_csc_init()
161 		writel(0x095 | (0x000 << 16), flow->base + DP_CSC_A_0);  in ipu_dp_csc_init()
162 		writel(0x0cc | (0x095 << 16), flow->base + DP_CSC_A_1);  in ipu_dp_csc_init()
163 		writel(0x3ce | (0x398 << 16), flow->base + DP_CSC_A_2);  in ipu_dp_csc_init()
164 		writel(0x095 | (0x0ff << 16), flow->base + DP_CSC_A_3);  in ipu_dp_csc_init()
165 		writel(0x000 | (0x3e42 << 16) | (1 << 30),  in ipu_dp_csc_init()
167 		writel(0x10a | (1 << 14) | (0x3dd6 << 16) | (1 << 30),  in ipu_dp_csc_init()
173 	writel(reg, flow->base + DP_COM_CONF);  in ipu_dp_csc_init()
248 	writel(reg, flow->base + DP_COM_CONF);  in ipu_dp_enable_channel()
275 	writel(reg, flow->base + DP_COM_CONF);  in ipu_dp_disable_channel()
277 	writel(0, flow->base + DP_FG_POS);  in ipu_dp_disable_channel()