Lines Matching refs:writel
184 writel(val, tegra->sata_regs + SATA_CONFIGURATION_0); in tegra_ahci_controller_init()
197 writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra_ahci_controller_init()
207 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra_ahci_controller_init()
218 writel(val, tegra->sata_regs + SCFG_OFFSET + in tegra_ahci_controller_init()
221 writel(T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ, in tegra_ahci_controller_init()
223 writel(T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1, in tegra_ahci_controller_init()
226 writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX); in tegra_ahci_controller_init()
232 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); in tegra_ahci_controller_init()
234 writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC); in tegra_ahci_controller_init()
238 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA); in tegra_ahci_controller_init()
245 writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1); in tegra_ahci_controller_init()
249 writel(0x10000 << SATA_FPCI_BAR5_START_SHIFT, in tegra_ahci_controller_init()
252 writel(0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT, in tegra_ahci_controller_init()
259 writel(val, tegra->sata_regs + SATA_INTR_MASK); in tegra_ahci_controller_init()