305 	writel(ucr->ucr1, port->membase + UCR1);  in imx_port_ucrs_restore()
306 	writel(ucr->ucr2, port->membase + UCR2);  in imx_port_ucrs_restore()
307 	writel(ucr->ucr3, port->membase + UCR3);  in imx_port_ucrs_restore()
372 	writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);  in imx_stop_tx()
382 		writel(temp, port->membase + UCR2);  in imx_stop_tx()
386 		writel(temp, port->membase + UCR4);  in imx_stop_tx()
408 	writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);  in imx_stop_rx()
412 	writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);  in imx_stop_rx()
433 		writel(sport->port.x_char, sport->port.membase + URTX0);  in imx_transmit_buffer()
453 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
455 			writel(temp, sport->port.membase + UCR1);  in imx_transmit_buffer()
464 		writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);  in imx_transmit_buffer()
490 	writel(temp, sport->port.membase + UCR1);  in dma_tx_callback()
564 	writel(temp, sport->port.membase + UCR1);  in imx_dma_tx()
588 		writel(temp, port->membase + UCR2);  in imx_start_tx()
592 		writel(temp, port->membase + UCR4);  in imx_start_tx()
597 		writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);  in imx_start_tx()
607 			writel(temp, sport->port.membase + UCR1);  in imx_start_tx()
626 	writel(USR1_RTSD, sport->port.membase + USR1);  in imx_rtsint()
663 			writel(USR2_BRCD, sport->port.membase + USR2);  in imx_rxint()
735 		writel(temp, sport->port.membase + UCR1);  in imx_dma_rxint()
739 		writel(temp, sport->port.membase + UCR2);  in imx_dma_rxint()
774 		writel(USR1_AWAKE, sport->port.membase + USR1);  in imx_int()
778 		writel(USR2_ORE, sport->port.membase + USR2);  in imx_int()
831 		writel(temp, sport->port.membase + UCR2);  in imx_set_mctrl()
837 	writel(temp, sport->port.membase + uts_reg(sport));  in imx_set_mctrl()
855 	writel(temp, sport->port.membase + UCR1);  in imx_break_ctl()
871 	writel(temp, sport->port.membase + UCR1);  in imx_rx_dma_done()
875 	writel(temp, sport->port.membase + UCR2);  in imx_rx_dma_done()
981 	writel(val, sport->port.membase + UFCR);  in imx_setup_ufcr()
1068 	writel(temp, sport->port.membase + UCR1);  in imx_enable_dma()
1072 	writel(temp, sport->port.membase + UCR2);  in imx_enable_dma()
1086 	writel(temp, sport->port.membase + UCR1);  in imx_disable_dma()
1091 	writel(temp, sport->port.membase + UCR2);  in imx_disable_dma()
1127 	writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);  in imx_startup()
1140 	writel(temp, sport->port.membase + UCR2);  in imx_startup()
1148 	writel(USR1_RTSD, sport->port.membase + USR1);  in imx_startup()
1149 	writel(USR2_ORE, sport->port.membase + USR2);  in imx_startup()
1157 	writel(temp, sport->port.membase + UCR1);  in imx_startup()
1161 	writel(temp, sport->port.membase + UCR4);  in imx_startup()
1167 	writel(temp, sport->port.membase + UCR2);  in imx_startup()
1172 		writel(temp, sport->port.membase + UCR3);  in imx_startup()
1213 	writel(temp, sport->port.membase + UCR2);  in imx_shutdown()
1229 	writel(temp, sport->port.membase + UCR1);  in imx_shutdown()
1253 		writel(temp, sport->port.membase + UCR1);  in imx_flush_buffer()
1270 	writel(temp, sport->port.membase + UCR2);  in imx_flush_buffer()
1276 	writel(ubir, sport->port.membase + UBIR);  in imx_flush_buffer()
1277 	writel(ubmr, sport->port.membase + UBMR);  in imx_flush_buffer()
1278 	writel(uts, sport->port.membase + IMX21_UTS);  in imx_flush_buffer()
1384 	writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),  in imx_set_termios()
1392 	writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),  in imx_set_termios()
1423 	writel(ufcr, sport->port.membase + UFCR);  in imx_set_termios()
1425 	writel(num, sport->port.membase + UBIR);  in imx_set_termios()
1426 	writel(denom, sport->port.membase + UBMR);  in imx_set_termios()
1429 		writel(sport->port.uartclk / div / 1000,  in imx_set_termios()
1432 	writel(old_ucr1, sport->port.membase + UCR1);  in imx_set_termios()
1435 	writel(ucr2 | old_ucr2, sport->port.membase + UCR2);  in imx_set_termios()
1514 	writel(temp, sport->port.membase + UCR1);  in imx_poll_init()
1518 	writel(temp, sport->port.membase + UCR2);  in imx_poll_init()
1576 		writel(temp, sport->port.membase + UCR2);  in imx_rs485_config()
1617 	writel(ch, sport->port.membase + URTX0);  in imx_console_putchar()
1660 	writel(ucr1, sport->port.membase + UCR1);  in imx_console_write()
1662 	writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);  in imx_console_write()
2020 	writel(sport->saved_reg[4], sport->port.membase + UFCR);  in serial_imx_restore_context()
2021 	writel(sport->saved_reg[5], sport->port.membase + UESC);  in serial_imx_restore_context()
2022 	writel(sport->saved_reg[6], sport->port.membase + UTIM);  in serial_imx_restore_context()
2023 	writel(sport->saved_reg[7], sport->port.membase + UBIR);  in serial_imx_restore_context()
2024 	writel(sport->saved_reg[8], sport->port.membase + UBMR);  in serial_imx_restore_context()
2025 	writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);  in serial_imx_restore_context()
2026 	writel(sport->saved_reg[0], sport->port.membase + UCR1);  in serial_imx_restore_context()
2027 	writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);  in serial_imx_restore_context()
2028 	writel(sport->saved_reg[2], sport->port.membase + UCR3);  in serial_imx_restore_context()
2029 	writel(sport->saved_reg[3], sport->port.membase + UCR4);  in serial_imx_restore_context()
2058 	writel(val, sport->port.membase + UCR3);  in serial_imx_enable_wakeup()
2065 	writel(val, sport->port.membase + UCR1);  in serial_imx_enable_wakeup()