120 	writel(1, vtg->regs + VTG_DRST_AUTOC);  in vtg_reset()
143 	writel(video_top_field_start, regs + VTG_VID_TFO);  in vtg_set_output_window()
144 	writel(video_top_field_stop, regs + VTG_VID_TFS);  in vtg_set_output_window()
145 	writel(video_bottom_field_start, regs + VTG_VID_BFO);  in vtg_set_output_window()
146 	writel(video_bottom_field_stop, regs + VTG_VID_BFS);  in vtg_set_output_window()
158 	writel(mode->htotal, vtg->regs + VTG_CLKLN);  in vtg_set_mode()
161 	writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);  in vtg_set_mode()
169 	writel(tmp, vtg->regs + VTG_H_HD_1);  in vtg_set_mode()
173 	writel(tmp, vtg->regs + VTG_TOP_V_VD_1);  in vtg_set_mode()
174 	writel(tmp, vtg->regs + VTG_BOT_V_VD_1);  in vtg_set_mode()
178 	writel(tmp, vtg->regs + VTG_TOP_V_HD_1);  in vtg_set_mode()
179 	writel(tmp, vtg->regs + VTG_BOT_V_HD_1);  in vtg_set_mode()
183 	writel(tmp, vtg->regs + VTG_H_HD_2);  in vtg_set_mode()
187 	writel(tmp, vtg->regs + VTG_TOP_V_VD_2);  in vtg_set_mode()
188 	writel(tmp, vtg->regs + VTG_BOT_V_VD_2);  in vtg_set_mode()
189 	writel(0, vtg->regs + VTG_TOP_V_HD_2);  in vtg_set_mode()
190 	writel(0, vtg->regs + VTG_BOT_V_HD_2);  in vtg_set_mode()
195 	writel(tmp, vtg->regs + VTG_H_HD_3);  in vtg_set_mode()
199 	writel(tmp, vtg->regs + VTG_TOP_V_VD_3);  in vtg_set_mode()
200 	writel(tmp, vtg->regs + VTG_BOT_V_VD_3);  in vtg_set_mode()
204 	writel(tmp, vtg->regs + VTG_TOP_V_HD_3);  in vtg_set_mode()
205 	writel(tmp, vtg->regs + VTG_BOT_V_HD_3);  in vtg_set_mode()
209 	writel(tmp, vtg->regs + VTG_H_HD_4);  in vtg_set_mode()
213 	writel(tmp, vtg->regs + VTG_TOP_V_VD_4);  in vtg_set_mode()
214 	writel(tmp, vtg->regs + VTG_BOT_V_VD_4);  in vtg_set_mode()
215 	writel(0, vtg->regs + VTG_TOP_V_HD_4);  in vtg_set_mode()
216 	writel(0, vtg->regs + VTG_BOT_V_HD_4);  in vtg_set_mode()
219 	writel(type, vtg->regs + VTG_MODE);  in vtg_set_mode()
225 	writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);  in vtg_enable_irq()
226 	writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);  in vtg_enable_irq()
227 	writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);  in vtg_enable_irq()
319 	writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);  in vtg_irq()