122 	writel(val & ~CR_TIE,  port->membase + UART_CR);  in netx_stop_tx()
129 	writel(val & ~CR_RIE,  port->membase + UART_CR);  in netx_stop_rx()
136 	writel(val | CR_MSIE, port->membase + UART_CR);  in netx_enable_ms()
144 		writel(port->x_char, port->membase + UART_DR);  in netx_transmit_buffer()
158 		writel(xmit->buf[xmit->tail], port->membase + UART_DR);  in netx_transmit_buffer()
172 	writel(  in netx_start_tx()
209 			writel(0, port->membase + UART_SR);  in netx_rxint()
264 		writel(0, port->membase + UART_IIR);  in netx_int()
289 		writel(val | RTS_CR_RTS, port->membase + UART_RTS_CR);  in netx_set_mctrl()
303 	writel(line_cr, port->membase + UART_LINE_CR);  in netx_break_ctl()
319 	writel(readl(port->membase + UART_LINE_CR) | LINE_CR_FEN,  in netx_startup()
322 	writel(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE | CR_UART_EN,  in netx_startup()
331 	writel(0, port->membase + UART_CR) ;  in netx_shutdown()
385 	writel(old_cr & ~(CR_MSIE | CR_RIE | CR_TIE | CR_RTIE),  in netx_set_termios()
392 	writel(old_cr & ~CR_UART_EN, port->membase + UART_CR);  in netx_set_termios()
399 	writel((quot>>8) & 0xff, port->membase + UART_BAUDDIV_MSB);  in netx_set_termios()
400 	writel(quot & 0xff, port->membase + UART_BAUDDIV_LSB);  in netx_set_termios()
401 	writel(line_cr, port->membase + UART_LINE_CR);  in netx_set_termios()
403 	writel(rts_cr, port->membase + UART_RTS_CR);  in netx_set_termios()
427 	writel(old_cr, port->membase + UART_CR);  in netx_set_termios()
532 	writel(ch, port->membase + UART_DR);  in netx_console_putchar()
542 	writel(cr_save | CR_UART_EN, port->membase + UART_CR);  in netx_console_write()
547 	writel(cr_save, port->membase + UART_CR);  in netx_console_write()
687 	writel(1, port->membase + UART_RXFIFO_IRQLEVEL);  in serial_netx_probe()