Lines Matching refs:writel
283 writel(tmp, &dev->regs->irqmsk); in udc_mask_unused_interrupts()
286 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk); in udc_mask_unused_interrupts()
303 writel(tmp, &dev->regs->ep_irqmsk); in udc_enable_ep0_interrupts()
324 writel(tmp, &dev->regs->irqmsk); in udc_enable_dev_setup_interrupts()
401 writel(tmp, &dev->ep[ep->num].regs->ctl); in udc_ep_enable()
408 writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); in udc_ep_enable()
424 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); in udc_ep_enable()
432 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
443 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); in udc_ep_enable()
472 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_ep_enable()
477 writel(tmp, &dev->regs->ep_irqmsk); in udc_ep_enable()
486 writel(tmp, &ep->regs->ctl); in udc_ep_enable()
511 writel(tmp, &ep->regs->ctl); in ep_init()
517 writel(tmp, ®s->ep_irqmsk); in ep_init()
523 writel(tmp, &ep->regs->ctl); in ep_init()
527 writel(tmp, &ep->regs->sts); in ep_init()
532 writel(tmp, &ep->regs->ctl); in ep_init()
536 writel(0, &ep->regs->desptr); in ep_init()
722 writel(*(buf + i), ep->txfifo); in udc_txfifo_write()
731 writel(0, &ep->regs->confirm); in udc_txfifo_write()
1004 writel(tmp, &ep->regs->ctl); in prep_dma()
1099 writel(tmp, &dev->regs->ctl); in udc_set_rde()
1162 writel(tmp, &dev->regs->ctl); in udc_queue()
1170 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_queue()
1201 writel(tmp, &dev->regs->ctl); in udc_queue()
1216 writel(req->td_phys, &ep->regs->desptr); in udc_queue()
1222 writel(tmp, &ep->regs->ctl); in udc_queue()
1231 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1237 writel(tmp, &dev->regs->ep_irqmsk); in udc_queue()
1332 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE), in udc_dequeue()
1344 writel(ep->bna_dummy_req->td_phys, in udc_dequeue()
1347 writel(tmp, &udc->regs->ctl); in udc_dequeue()
1390 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1412 writel(tmp, &ep->regs->ctl); in udc_set_halt()
1456 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()
1458 writel(tmp, &dev->regs->ctl); in udc_remote_wakeup()
1530 writel(tmp, &dev->regs->ctl); in udc_basic_init()
1539 writel(tmp, &dev->regs->cfg); in udc_basic_init()
1569 writel(tmp, &dev->regs->cfg); in startup_registers()
1633 writel(reg, &dev->ep[tmp].regs->ctl); in udc_setup_endpoints()
1740 writel(tmp, &dev->regs->cfg); in udc_tasklet_disconnect()
1757 writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts); in udc_soft_reset()
1759 writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts); in udc_soft_reset()
1762 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_soft_reset()
1784 writel(tmp, &udc->regs->ctl); in udc_timer_function()
1841 writel(tmp, &ep->regs->ctl); in udc_handle_halt_state()
1892 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1906 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); in activate_control_endpoints()
1916 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1926 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); in activate_control_endpoints()
1936 writel(tmp, &dev->csr->ne[0]); in activate_control_endpoints()
1942 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma, in activate_control_endpoints()
1944 writel(dev->ep[UDC_EP0OUT_IX].td_phys, in activate_control_endpoints()
1963 writel(tmp, &dev->regs->ctl); in activate_control_endpoints()
1969 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in activate_control_endpoints()
1976 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in activate_control_endpoints()
2015 writel(tmp, &dev->regs->ctl); in amd5536_udc_start()
2056 writel(tmp, &dev->regs->ctl); in amd5536_udc_stop()
2075 writel(reg, &dev->ep[tmp].regs->ctl); in udc_process_cnak_queue()
2086 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_process_cnak_queue()
2141 writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts); in udc_data_out_isr()
2155 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_out_isr()
2272 writel(req->td_phys, in udc_data_out_isr()
2285 writel(ep->bna_dummy_req->td_phys, in udc_data_out_isr()
2329 writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts); in udc_data_out_isr()
2358 writel(epsts, &ep->regs->sts); in udc_data_in_isr()
2370 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts); in udc_data_in_isr()
2409 writel(tmp, &dev->regs->ep_irqmsk); in udc_data_in_isr()
2460 writel(req->td_phys, &ep->regs->desptr); in udc_data_in_isr()
2472 writel(tmp, &ep->regs->ctl); in udc_data_in_isr()
2481 writel(tmp, in udc_data_in_isr()
2486 writel(epsts, &ep->regs->sts); in udc_data_in_isr()
2509 writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts); in udc_control_out_isr()
2515 writel(AMD_BIT(UDC_EPSTS_BNA), in udc_control_out_isr()
2536 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2542 writel(UDC_EPSTS_OUT_CLEAR, in udc_control_out_isr()
2571 writel(ep->bna_dummy_req->td_phys, in udc_control_out_isr()
2622 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2629 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); in udc_control_out_isr()
2638 writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); in udc_control_out_isr()
2645 writel(UDC_EPSTS_OUT_CLEAR, in udc_control_out_isr()
2652 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts); in udc_control_out_isr()
2674 writel(dev->ep[UDC_EP0OUT_IX].td_phys, in udc_control_out_isr()
2721 writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts); in udc_control_in_isr()
2730 writel(AMD_BIT(UDC_EPSTS_TDC), in udc_control_in_isr()
2739 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2747 writel(tmp, &ep->regs->ctl); in udc_control_in_isr()
2756 writel(req->td_phys, &ep->regs->desptr); in udc_control_in_isr()
2768 writel(tmp, in udc_control_in_isr()
2800 writel(AMD_BIT(UDC_EPSTS_IN), in udc_control_in_isr()
2857 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2863 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2916 writel(tmp, &dev->csr->ne[udc_csr_epix]); in udc_dev_isr()
2922 writel(tmp, &ep->regs->ctl); in udc_dev_isr()
2972 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); in udc_dev_isr()
2973 writel(tmp, &dev->regs->cfg); in udc_dev_isr()
2984 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
3028 writel(tmp, &dev->regs->irqmsk); in udc_dev_isr()
3068 writel(ep_irq, &dev->regs->ep_irqsts); in udc_irq()
3084 writel(reg, &dev->regs->irqsts); in udc_irq()
3145 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); in udc_pci_remove()
3275 writel(reg, &dev->regs->ctl); in udc_probe()