Lines Matching refs:writel
313 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_unlock_lut()
314 writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_unlock_lut()
319 writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY); in fsl_qspi_lock_lut()
320 writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR); in fsl_qspi_lock_lut()
330 writel(reg, q->iobase + QUADSPI_FR); in fsl_qspi_irq_handler()
351 writel(0, base + QUADSPI_LUT_BASE + i * 4); in fsl_qspi_init_lut()
367 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
369 writel(LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), in fsl_qspi_init_lut()
374 writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
388 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
390 writel(LUT0(FSL_WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1)); in fsl_qspi_init_lut()
394 writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(FSL_READ, PAD1, 0x1), in fsl_qspi_init_lut()
403 writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), in fsl_qspi_init_lut()
408 writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE), in fsl_qspi_init_lut()
413 writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(FSL_READ, PAD1, 0x8), in fsl_qspi_init_lut()
418 writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(FSL_WRITE, PAD1, 0x2), in fsl_qspi_init_lut()
423 writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(FSL_READ, PAD1, 0x1), in fsl_qspi_init_lut()
428 writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
432 writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
436 writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base)); in fsl_qspi_init_lut()
493 writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR); in fsl_qspi_runcmd()
494 writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS, in fsl_qspi_runcmd()
496 writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR); in fsl_qspi_runcmd()
510 writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR); in fsl_qspi_runcmd()
524 writel(reg, base + QUADSPI_MCR); in fsl_qspi_runcmd()
566 writel(reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
575 writel(reg, q->iobase + QUADSPI_MCR); in fsl_qspi_invalid()
590 writel(tmp | QUADSPI_MCR_CLR_TXF_MASK, q->iobase + QUADSPI_MCR); in fsl_qspi_nor_write()
595 writel(tmp, q->iobase + QUADSPI_TBDR); in fsl_qspi_nor_write()
602 writel(tmp, q->iobase + QUADSPI_TBDR); in fsl_qspi_nor_write()
618 writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD); in fsl_qspi_set_map_addr()
619 writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD); in fsl_qspi_set_map_addr()
620 writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD); in fsl_qspi_set_map_addr()
621 writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD); in fsl_qspi_set_map_addr()
643 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); in fsl_qspi_init_abh_read()
644 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); in fsl_qspi_init_abh_read()
645 writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); in fsl_qspi_init_abh_read()
650 writel(QUADSPI_BUF3CR_ALLMST_MASK | ((q->devtype_data->ahb_buf_size / 8) in fsl_qspi_init_abh_read()
654 writel(0, base + QUADSPI_BUF0IND); in fsl_qspi_init_abh_read()
655 writel(0, base + QUADSPI_BUF1IND); in fsl_qspi_init_abh_read()
656 writel(0, base + QUADSPI_BUF2IND); in fsl_qspi_init_abh_read()
660 writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT, in fsl_qspi_init_abh_read()
716 writel(QUADSPI_MCR_SWRSTSD_MASK | QUADSPI_MCR_SWRSTHD_MASK, in fsl_qspi_nor_setup()
724 writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK, in fsl_qspi_nor_setup()
728 writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK in fsl_qspi_nor_setup()
734 writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK, in fsl_qspi_nor_setup()
738 writel(0xffffffff, q->iobase + QUADSPI_FR); in fsl_qspi_nor_setup()
741 writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER); in fsl_qspi_nor_setup()
1106 writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR); in fsl_qspi_remove()
1107 writel(0x0, q->iobase + QUADSPI_RSER); in fsl_qspi_remove()