$base (reference) in projects: linux-4.1.27

Searched refs:base (Results 1 – 200 of 4083) sorted by relevance

/linux-4.1.27/arch/arm/mach-imx/
D	clk-imx6q.c	127 void __iomem *base; in imx6q_clocks_init() local 140 base = of_iomap(np, 0); in imx6q_clocks_init() 141 WARN_ON(!base); in imx6q_clocks_init() 151 …clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() 152 …clk[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() 153 …clk[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() 154 …clk[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() 155 …clk[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() 156 …clk[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() 157 …clk[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_s… in imx6q_clocks_init() [all …]
D	clk-imx6sx.c	142 void __iomem *base; in imx6sx_clocks_init() local 158 base = of_iomap(np, 0); in imx6sx_clocks_init() 159 WARN_ON(!base); in imx6sx_clocks_init() 161 …clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() 162 …clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() 163 …clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() 164 …clks[IMX6SX_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() 165 …clks[IMX6SX_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() 166 …clks[IMX6SX_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() 167 …clks[IMX6SX_PLL7_BYPASS_SRC] = imx_clk_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init() [all …]
D	clk-imx6sl.c	191 void __iomem *base; in imx6sl_clocks_init() local 202 base = of_iomap(np, 0); in imx6sl_clocks_init() 203 WARN_ON(!base); in imx6sl_clocks_init() 204 anatop_base = base; in imx6sl_clocks_init() 206 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init() 207 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init() 208 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init() 209 …clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init() 210 …clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init() 211 …clks[IMX6SL_PLL6_BYPASS_SRC] = imx_clk_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init() [all …]
D	clk-imx35.c	74 void __iomem *base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR); in mx35_clocks_init() local 79 pdr0 = __raw_readl(base + MXC_CCM_PDR0); in mx35_clocks_init() 92 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL); in mx35_clocks_init() 93 clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL); in mx35_clocks_init() 118 clk[arm_per_div] = imx_clk_divider("arm_per_div", "arm", base + MX35_CCM_PDR4, 16, 6); in mx35_clocks_init() 119 clk[ahb_per_div] = imx_clk_divider("ahb_per_div", "ahb", base + MXC_CCM_PDR0, 12, 3); in mx35_clocks_init() 120 …clk[ipg_per] = imx_clk_mux("ipg_per", base + MXC_CCM_PDR0, 26, 1, ipg_per_sel, ARRAY_SIZE(ipg_per_… in mx35_clocks_init() 122 clk[uart_sel] = imx_clk_mux("uart_sel", base + MX35_CCM_PDR3, 14, 1, std_sel, ARRAY_SIZE(std_sel)); in mx35_clocks_init() 123 clk[uart_div] = imx_clk_divider("uart_div", "uart_sel", base + MX35_CCM_PDR4, 10, 6); in mx35_clocks_init() 125 …clk[esdhc_sel] = imx_clk_mux("esdhc_sel", base + MX35_CCM_PDR4, 9, 1, std_sel, ARRAY_SIZE(std_sel)… in mx35_clocks_init() [all …]
D	clk-imx31.c	53 void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR); in mx31_clocks_init() local 59 clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL); in mx31_clocks_init() 60 clk[spll] = imx_clk_pllv1("spll", "ckih", base + MXC_CCM_SRPCTL); in mx31_clocks_init() 61 clk[upll] = imx_clk_pllv1("upll", "ckih", base + MXC_CCM_UPCTL); in mx31_clocks_init() 62 …clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_… in mx31_clocks_init() 63 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3); in mx31_clocks_init() 64 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3); in mx31_clocks_init() 65 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3); in mx31_clocks_init() 66 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2); in mx31_clocks_init() 67 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5); in mx31_clocks_init() [all …]
/linux-4.1.27/drivers/scsi/
D	aha1740.h	`18 #define HID0(base) (base + 0x0) argument 19 #define HID1(base) (base + 0x1) argument 20 #define HID2(base) (base + 0x2) argument 21 #define HID3(base) (base + 0x3) argument 22 #define EBCNTRL(base) (base + 0x4) argument 23 #define PORTADR(base) (base + 0x40) argument 24 #define BIOSADR(base) (base + 0x41) argument 25 #define INTDEF(base) (base + 0x42) argument 26 #define SCSIDEF(base) (base + 0x43) argument 27 #define BUSDEF(base) (base + 0x44) argument [all …]`
D	nsp32_io.h	12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument 16 outb(val, (base + index)); in nsp32_write1() 19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument 22 return inb(base + index); in nsp32_read1() 25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument 29 outw(val, (base + index)); in nsp32_write2() 32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument 35 return inw(base + index); in nsp32_read2() 38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument 42 outl(val, (base + index)); in nsp32_write4() [all …]
D	sym53c416.c	213 int base; member 232 static void sym53c416_set_transfer_counter(int base, unsigned int len) in sym53c416_set_transfer_counter() argument 235 outb(len & 0x0000FF, base + TC_LOW); in sym53c416_set_transfer_counter() 236 outb((len & 0x00FF00) >> 8, base + TC_MID); in sym53c416_set_transfer_counter() 237 outb((len & 0xFF0000) >> 16, base + TC_HIGH); in sym53c416_set_transfer_counter() 243 static __inline__ unsigned int sym53c416_read(int base, unsigned char buffer, unsigned int len) in sym53c416_read() argument 255 bytes_left = inb(base + PIO_FIFO_CNT); / Number of bytes in the PIO FIFO / in sym53c416_read() 258 insl(base + PIO_FIFO_1, buffer, bytes_left >> 2); in sym53c416_read() 266 (buffer++) = inb(base + PIO_FIFO_1); in sym53c416_read() 272 while(time_before(jiffies, i) && (inb(base + PIO_INT_REG) & EMPTY) && timeout) in sym53c416_read() [all …]
D	eata_pio.c	106 seq_printf(m, "Base IO : %#.4x\n", (u32) shost->base); in eata_pio_show_info() 164 unsigned long base; in eata_pio_int_handler() local 175 if (inb(sh->base + HA_RSTATUS) & HA_SBUSY) in eata_pio_int_handler() 185 base = cmd->device->host->base; in eata_pio_int_handler() 188 stat = inb(base + HA_RSTATUS); in eata_pio_int_handler() 200 insw(base + HA_RDATA, cmd->SCp.ptr, x); in eata_pio_int_handler() 204 zwickel = inw(base + HA_RDATA); in eata_pio_int_handler() 212 zwickel = inw(base + HA_RDATA); in eata_pio_int_handler() 223 outw(zwickel, base + HA_RDATA); in eata_pio_int_handler() 228 outsw(base + HA_RDATA, cmd->SCp.ptr, x); in eata_pio_int_handler() [all …]
D	nsp32_debug.c	228 static void nsp32_print_register(int base) in nsp32_print_register() argument 233 printk("Phase=0x%x, ", nsp32_read1(base, SCSI_BUS_MONITOR)); in nsp32_print_register() 234 printk("OldPhase=0x%x, ", nsp32_index_read1(base, OLD_SCSI_PHASE)); in nsp32_print_register() 235 printk("syncreg=0x%x, ", nsp32_read1(base, SYNC_REG)); in nsp32_print_register() 236 printk("ackwidth=0x%x, ", nsp32_read1(base, ACK_WIDTH)); in nsp32_print_register() 237 printk("sgtpaddr=0x%lx, ", nsp32_read4(base, SGT_ADR)); in nsp32_print_register() 238 printk("scsioutlatch=0x%x, ", nsp32_read1(base, SCSI_OUT_LATCH_TARGET_ID)); in nsp32_print_register() 239 printk("msgout=0x%lx, ", nsp32_read4(base, SCSI_MSG_OUT)); in nsp32_print_register() 240 printk("miscrd=0x%x, ", nsp32_index_read2(base, MISC_WR)); in nsp32_print_register() 241 printk("seltimeout=0x%x, ", nsp32_read2(base, SEL_TIME_OUT)); in nsp32_print_register() [all …]
D	a100u2w.c	144 if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set / in wait_chip_ready() 156 if (inb(host->base + ORC_HSTUS) & RREADY) / Wait READY set / in wait_firmware_ready() 169 if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) / Wait SCSIRST done / in wait_scsi_reset_done() 182 if (!(inb(host->base + ORC_HCTRL) & HDO)) / Wait HDO off / in wait_HDO_off() 195 if ((data = inb(host->base + ORC_HSTUS)) & HDI) in wait_hdi_set() 208 outb(ORC_CMD_VERSION, host->base + ORC_HDATA); in orc_read_fwrev() 209 outb(HDO, host->base + ORC_HCTRL); in orc_read_fwrev() 215 version = inb(host->base + ORC_HDATA); in orc_read_fwrev() 216 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ in orc_read_fwrev() 220 version \|= inb(host->base + ORC_HDATA) << 8; in orc_read_fwrev() [all …]
D	t128.c	98 static struct base { struct 170 unsigned long base; in t128_detect() local 175 base = 0; in t128_detect() 179 base = overrides[current_override].address; in t128_detect() 182 base = 0; in t128_detect() 184 for (; !base && (current_base < NO_BASES); ++current_base) { in t128_detect() 197 base = bases[current_base].address; in t128_detect() 207 printk("scsi-t128 : base = %08x\n", (unsigned int) base); in t128_detect() 210 if (!base) in t128_detect() 218 instance->base = base; in t128_detect() [all …]
D	nsp32.c	439 unsigned int base = SCpnt->host->io_port; 447 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK); 458 unsigned int base = SCpnt->device->host->io_port; in nsp32_selection_autopara() local 472 phase = nsp32_read1(base, SCSI_BUS_MONITOR); in nsp32_selection_autopara() 570 nsp32_write4(base, SGT_ADR, data->auto_paddr); in nsp32_selection_autopara() 571 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER \| in nsp32_selection_autopara() 577 ret = nsp32_arbitration(SCpnt, base); in nsp32_selection_autopara() 589 unsigned int base = SCpnt->device->host->io_port; in nsp32_selection_autoscsi() local 604 nsp32_write2(base, IRQ_CONTROL, IRQ_CONTROL_ALL_IRQ_MASK); in nsp32_selection_autoscsi() 609 phase = nsp32_read1(base, SCSI_BUS_MONITOR); in nsp32_selection_autoscsi() [all …]
/linux-4.1.27/drivers/video/fbdev/omap2/dss/
D	hdmi5_core.c	52 void __iomem *base = core->base; in hdmi_core_ddc_init() local 67 REG_FLD_MOD(base, HDMI_CORE_I2CM_SOFTRSTZ, 0, 0, 0); in hdmi_core_ddc_init() 68 if (hdmi_wait_for_bit_change(base, HDMI_CORE_I2CM_SOFTRSTZ, in hdmi_core_ddc_init() 73 REG_FLD_MOD(base, HDMI_CORE_I2CM_DIV, 0, 3, 3); in hdmi_core_ddc_init() 77 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init() 79 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init() 84 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR, in hdmi_core_ddc_init() 86 REG_FLD_MOD(base, HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR, in hdmi_core_ddc_init() 91 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR, in hdmi_core_ddc_init() 93 REG_FLD_MOD(base, HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR, in hdmi_core_ddc_init() [all …]
D	hdmi_wp.c	24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r)) in hdmi_wp_dump() 48 return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_get_irqstatus() 53 hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus); in hdmi_wp_set_irqstatus() 55 hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS); in hdmi_wp_set_irqstatus() 60 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask); in hdmi_wp_set_irqenable() 65 hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask); in hdmi_wp_clear_irqenable() 72 if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_wp_set_phy_pwr() 76 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_wp_set_phy_pwr() 79 if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val) in hdmi_wp_set_phy_pwr() 92 REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_wp_set_pll_pwr() [all …]
/linux-4.1.27/drivers/isdn/hardware/avm/
D	avmcard.h	219 static inline unsigned char b1outp(unsigned int base, in b1outp() argument 223 outb(value, base + offset); in b1outp() 224 return inb(base + B1_ANALYSE); in b1outp() 228 static inline int b1_rx_full(unsigned int base) in b1_rx_full() argument 230 return inb(base + B1_INSTAT) & 0x1; in b1_rx_full() 233 static inline unsigned char b1_get_byte(unsigned int base) in b1_get_byte() argument 236 while (!b1_rx_full(base) && time_before(jiffies, stop)); in b1_get_byte() 237 if (b1_rx_full(base)) in b1_get_byte() 238 return inb(base + B1_READ); in b1_get_byte() 239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); in b1_get_byte() [all …]
/linux-4.1.27/arch/mips/alchemy/common/
D	usb.c	97 static inline void __au1300_usb_phyctl(void __iomem base, int enable) in __au1300_usb_phyctl() argument 101 r = __raw_readl(base + USB_DWC_CTRL2); in __au1300_usb_phyctl() 102 s = __raw_readl(base + USB_DWC_CTRL3); in __au1300_usb_phyctl() 111 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl() 117 __raw_writel(r, base + USB_DWC_CTRL2); in __au1300_usb_phyctl() 122 static inline void __au1300_ohci_control(void __iomem base, int enable, int id) in __au1300_ohci_control() argument 127 __raw_writel(1, base + USB_DWC_CTRL7); /* start OHCI clock / in __au1300_ohci_control() 130 r = __raw_readl(base + USB_DWC_CTRL3); / enable OHCI block / in __au1300_ohci_control() 133 __raw_writel(r, base + USB_DWC_CTRL3); in __au1300_ohci_control() 136 __au1300_usb_phyctl(base, enable); / power up the PHYs */ in __au1300_ohci_control() [all …]
D	irq.c	291 void __iomem base = (void __iomem )KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_unmask() local 293 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic0_unmask() 294 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic0_unmask() 301 void __iomem base = (void __iomem )KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_unmask() local 303 __raw_writel(1 << bit, base + IC_MASKSET); in au1x_ic1_unmask() 304 __raw_writel(1 << bit, base + IC_WAKESET); in au1x_ic1_unmask() 311 void __iomem base = (void __iomem )KSEG1ADDR(AU1000_IC0_PHYS_ADDR); in au1x_ic0_mask() local 313 __raw_writel(1 << bit, base + IC_MASKCLR); in au1x_ic0_mask() 314 __raw_writel(1 << bit, base + IC_WAKECLR); in au1x_ic0_mask() 321 void __iomem base = (void __iomem )KSEG1ADDR(AU1000_IC1_PHYS_ADDR); in au1x_ic1_mask() local [all …]
D	vss.c	24 void __iomem base = (void __iomem )VSS_ADDR(block); in __enable_block() local 26 __raw_writel(3, base + VSS_CLKRST); /* enable clock, assert reset / in __enable_block() 29 __raw_writel(0x01fffffe, base + VSS_GATE); / maximum setup time / in __enable_block() 33 __raw_writel(0x01, base + VSS_FTR); in __enable_block() 35 __raw_writel(0x03, base + VSS_FTR); in __enable_block() 37 __raw_writel(0x07, base + VSS_FTR); in __enable_block() 39 __raw_writel(0x0f, base + VSS_FTR); in __enable_block() 42 __raw_writel(0x01ffffff, base + VSS_GATE); / start FSM too / in __enable_block() 45 __raw_writel(2, base + VSS_CLKRST); / deassert reset / in __enable_block() 48 __raw_writel(0x1f, base + VSS_FTR); / enable isolation cells */ in __enable_block() [all …]
/linux-4.1.27/drivers/ata/
D	pata_bf54x.c	`77 #define ATAPI_GET_CONTROL(base)\ argument 78 bfin_read16(base + ATAPI_OFFSET_CONTROL) 79 #define ATAPI_SET_CONTROL(base, val)\ argument 80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val) 81 #define ATAPI_GET_STATUS(base)\ argument 82 bfin_read16(base + ATAPI_OFFSET_STATUS) 83 #define ATAPI_GET_DEV_ADDR(base)\ argument 84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR) 85 #define ATAPI_SET_DEV_ADDR(base, val)\ argument 86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val) [all …]`
D	sata_rcar.c	153 void __iomem base; member 160 void __iomem base = priv->base; in sata_rcar_gen1_phy_preinit() local 163 iowrite32(0, base + SATAPHYADDR_REG); in sata_rcar_gen1_phy_preinit() 165 iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); in sata_rcar_gen1_phy_preinit() 168 iowrite32(0, base + SATAPHYRESET_REG); in sata_rcar_gen1_phy_preinit() 174 void __iomem *base = priv->base; in sata_rcar_gen1_phy_write() local 178 iowrite32(0, base + SATAPHYRESET_REG); in sata_rcar_gen1_phy_write() 180 iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); in sata_rcar_gen1_phy_write() 182 iowrite32(val, base + SATAPHYWDATA_REG); in sata_rcar_gen1_phy_write() 187 iowrite32(SATAPHYADDR_PHYCMD_WRITE \| reg, base + SATAPHYADDR_REG); in sata_rcar_gen1_phy_write() [all …]
D	pata_ninja32.c	91 static void ninja32_program(void __iomem base) in ninja32_program() argument 93 iowrite8(0x05, base + 0x01); / Enable interrupt lines / in ninja32_program() 94 iowrite8(0xBE, base + 0x02); / Burst, ?? setup / in ninja32_program() 95 iowrite8(0x01, base + 0x03); / Unknown / in ninja32_program() 96 iowrite8(0x20, base + 0x04); / WAIT0 / in ninja32_program() 97 iowrite8(0x8f, base + 0x05); / Unknown / in ninja32_program() 98 iowrite8(0xa4, base + 0x1c); / Unknown / in ninja32_program() 99 iowrite8(0x83, base + 0x1d); / BMDMA control: WAIT0 / in ninja32_program() 106 void __iomem base; in ninja32_init_one() local 135 base = host->iomap[0]; in ninja32_init_one() [all …]
/linux-4.1.27/drivers/media/platform/s5p-jpeg/
D	jpeg-hw-exynos4.c	19 void exynos4_jpeg_sw_reset(void __iomem base) in exynos4_jpeg_sw_reset() argument 23 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 24 writel(reg & ~EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 28 writel(reg \| EXYNOS4_SOFT_RESET_HI, base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_sw_reset() 31 void exynos4_jpeg_set_enc_dec_mode(void __iomem base, unsigned int mode) in exynos4_jpeg_set_enc_dec_mode() argument 35 reg = readl(base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode() 40 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode() 44 base + EXYNOS4_JPEG_CNTL_REG); in exynos4_jpeg_set_enc_dec_mode() 48 void exynos4_jpeg_set_img_fmt(void __iomem *base, unsigned int img_fmt) in exynos4_jpeg_set_img_fmt() argument 52 reg = readl(base + EXYNOS4_IMG_FMT_REG) & in exynos4_jpeg_set_img_fmt() [all …]
D	jpeg-hw-exynos4.h	16 void exynos4_jpeg_sw_reset(void __iomem base); 17 void exynos4_jpeg_set_enc_dec_mode(void __iomem base, unsigned int mode); 18 void exynos4_jpeg_set_img_fmt(void __iomem base, unsigned int img_fmt); 19 void exynos4_jpeg_set_enc_out_fmt(void __iomem base, unsigned int out_fmt); 20 void exynos4_jpeg_set_enc_tbl(void __iomem base); 21 void exynos4_jpeg_set_interrupt(void __iomem base); 22 unsigned int exynos4_jpeg_get_int_status(void __iomem base); 23 void exynos4_jpeg_set_huf_table_enable(void __iomem base, int value); 24 void exynos4_jpeg_set_sys_int_enable(void __iomem base, int value); 25 void exynos4_jpeg_set_stream_buf_address(void __iomem base, [all …]
/linux-4.1.27/drivers/net/ethernet/broadcom/bnx2x/
D	bnx2x_fw_defs.h	13 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base) 15 (IRO[151].base + ((assertListEntry) * IRO[151].m1)) 17 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \ 20 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \ 23 (IRO[163].base + ((funcId) * IRO[163].m1)) 25 (IRO[153].base + ((funcId) * IRO[153].m1)) 27 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2)) 29 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \ 31 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base) 33 (IRO[323].base + ((pfId) * IRO[323].m1)) [all …]
/linux-4.1.27/drivers/phy/
D	phy-qcom-apq8064-sata.c	100 void __iomem *base = phy->mmio; in qcom_apq8064_sata_phy_init() local 104 writel_relaxed(0x01, base + SATA_PHY_SER_CTRL); in qcom_apq8064_sata_phy_init() 105 writel_relaxed(0xB1, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init() 110 writel_relaxed(0x01, base + SATA_PHY_POW_DWN_CTRL0); in qcom_apq8064_sata_phy_init() 111 writel_relaxed(0x3E, base + SATA_PHY_POW_DWN_CTRL1); in qcom_apq8064_sata_phy_init() 112 writel_relaxed(0x01, base + SATA_PHY_RX_IMCAL0); in qcom_apq8064_sata_phy_init() 113 writel_relaxed(0x01, base + SATA_PHY_TX_IMCAL0); in qcom_apq8064_sata_phy_init() 114 writel_relaxed(0x02, base + SATA_PHY_TX_IMCAL2); in qcom_apq8064_sata_phy_init() 117 writel_relaxed(0x04, base + UNIPHY_PLL_REFCLK_CFG); in qcom_apq8064_sata_phy_init() 118 writel_relaxed(0x00, base + UNIPHY_PLL_PWRGEN_CFG); in qcom_apq8064_sata_phy_init() [all …]
D	phy-miphy28lp.c	208 void __iomem base; member 370 void base = miphy_phy->base; in miphy28lp_set_reset() local 374 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28lp_set_reset() 377 writeb_relaxed(val, base + MIPHY_CONF_RESET); in miphy28lp_set_reset() 379 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); in miphy28lp_set_reset() 384 writeb_relaxed(val, base + MIPHY_CONTROL); in miphy28lp_set_reset() 387 writeb_relaxed(val, base + MIPHY_CONTROL); in miphy28lp_set_reset() 394 void *base = miphy_phy->base; in miphy28lp_pll_calibration() local 398 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); in miphy28lp_pll_calibration() 399 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration() [all …]
D	phy-miphy365x.c	140 void __iomem *base; member 196 writeb_relaxed(val, miphy_phy->base + CTRL_REG); in miphy365x_init_pcie_port() 197 writeb_relaxed(0x00, miphy_phy->base + PCIE_REG); in miphy365x_init_pcie_port() 211 regval = readb_relaxed(miphy_phy->base + STATUS_REG); in miphy365x_hfc_not_rdy() 230 regval = readb_relaxed(miphy_phy->base + STATUS_REG); in miphy365x_rdy() 248 miphy_phy->base + COMP_CTRL2_REG); in miphy365x_set_comp() 251 miphy_phy->base + COMP_CTRL2_REG); in miphy365x_set_comp() 255 miphy_phy->base + COMP_CTRL3_REG); in miphy365x_set_comp() 261 writeb_relaxed(BYPASS_PLL_CAL, miphy_phy->base + PLL_CTRL2_REG); in miphy365x_set_comp() 262 writeb_relaxed(COMZC_IDLL, miphy_phy->base + COMP_IDLL_REG); in miphy365x_set_comp() [all …]
D	phy-rcar-gen2.c	64 void __iomem base; member 91 ugctrl2 = readl(drv->base + USBHS_UGCTRL2); in rcar_gen2_phy_init() 94 writel(ugctrl2, drv->base + USBHS_UGCTRL2); in rcar_gen2_phy_init() 115 void __iomem base = drv->base; in rcar_gen2_phy_power_on() local 127 value = readl(base + USBHS_UGCTRL); in rcar_gen2_phy_power_on() 129 writel(value, base + USBHS_UGCTRL); in rcar_gen2_phy_power_on() 131 value = readw(base + USBHS_LPSTS); in rcar_gen2_phy_power_on() 133 writew(value, base + USBHS_LPSTS); in rcar_gen2_phy_power_on() 136 value = readl(base + USBHS_UGSTS); in rcar_gen2_phy_power_on() 138 value = readl(base + USBHS_UGCTRL); in rcar_gen2_phy_power_on() [all …]
/linux-4.1.27/arch/powerpc/include/asm/
D	ppc_asm.h	78 #define SAVE_GPR(n, base) std n,GPR0+8(n)(base) argument 79 #define REST_GPR(n, base) ld n,GPR0+8(n)(base) argument 80 #define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base) argument 81 #define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base) argument 83 #define SAVE_GPR(n, base) stw n,GPR0+4(n)(base) argument 84 #define REST_GPR(n, base) lwz n,GPR0+4(n)(base) argument 85 #define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \ argument 86 SAVE_10GPRS(22, base) 87 #define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \ argument 88 REST_10GPRS(22, base) [all …]
/linux-4.1.27/arch/arm/plat-orion/
D	pcie.c	55 u32 orion_pcie_dev_id(void __iomem base) in orion_pcie_dev_id() argument 57 return readl(base + PCIE_DEV_ID_OFF) >> 16; in orion_pcie_dev_id() 60 u32 orion_pcie_rev(void __iomem base) in orion_pcie_rev() argument 62 return readl(base + PCIE_DEV_REV_OFF) & 0xff; in orion_pcie_rev() 65 int orion_pcie_link_up(void __iomem base) in orion_pcie_link_up() argument 67 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); in orion_pcie_link_up() 70 int __init orion_pcie_x4_mode(void __iomem base) in orion_pcie_x4_mode() argument 72 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE); in orion_pcie_x4_mode() 75 int orion_pcie_get_local_bus_nr(void __iomem *base) in orion_pcie_get_local_bus_nr() argument 77 u32 stat = readl(base + PCIE_STAT_OFF); in orion_pcie_get_local_bus_nr() [all …]
/linux-4.1.27/drivers/s390/block/
D	dasd_ioctl.c	46 struct dasd_device base; in dasd_ioctl_enable() local 51 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable() 52 if (!base) in dasd_ioctl_enable() 55 dasd_enable_device(base); in dasd_ioctl_enable() 59 (loff_t)get_capacity(base->block->gdp) << 9); in dasd_ioctl_enable() 61 dasd_put_device(base); in dasd_ioctl_enable() 72 struct dasd_device base; in dasd_ioctl_disable() local 77 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable() 78 if (!base) in dasd_ioctl_disable() 88 dasd_set_target_state(base, DASD_STATE_BASIC); in dasd_ioctl_disable() [all …]
D	dasd_genhd.c	32 struct dasd_device *base; in dasd_gendisk_alloc() local 36 base = block->base; in dasd_gendisk_alloc() 37 if (base->devindex >= DASD_PER_MAJOR) in dasd_gendisk_alloc() 46 gdp->first_minor = base->devindex << DASD_PARTN_BITS; in dasd_gendisk_alloc() 48 gdp->driverfs_dev = &base->cdev->dev; in dasd_gendisk_alloc() 58 if (base->devindex > 25) { in dasd_gendisk_alloc() 59 if (base->devindex > 701) { in dasd_gendisk_alloc() 60 if (base->devindex > 18277) in dasd_gendisk_alloc() 62 'a'+(((base->devindex-18278) in dasd_gendisk_alloc() 65 'a'+(((base->devindex-702)/676)%26)); in dasd_gendisk_alloc() [all …]
/linux-4.1.27/kernel/time/
D	timer.c	108 static inline unsigned int tbase_get_deferrable(struct tvec_base base) in tbase_get_deferrable() argument 110 return ((unsigned int)(unsigned long)base & TIMER_DEFERRABLE); in tbase_get_deferrable() 113 static inline unsigned int tbase_get_irqsafe(struct tvec_base base) in tbase_get_irqsafe() argument 115 return ((unsigned int)(unsigned long)base & TIMER_IRQSAFE); in tbase_get_irqsafe() 118 static inline struct tvec_base tbase_get_base(struct tvec_base base) in tbase_get_base() argument 120 return ((struct tvec_base )((unsigned long)base & ~TIMER_FLAG_MASK)); in tbase_get_base() 126 unsigned long flags = (unsigned long)timer->base & TIMER_FLAG_MASK; in timer_set_base() 128 timer->base = (struct tvec_base )((unsigned long)(new_base) \| flags); in timer_set_base() 357 static bool catchup_timer_jiffies(struct tvec_base *base) in catchup_timer_jiffies() argument 359 if (!base->all_timers) { in catchup_timer_jiffies() [all …]
D	hrtimer.c	117 static void hrtimer_get_softirq_time(struct hrtimer_cpu_base base) in hrtimer_get_softirq_time() argument 127 base->clock_base[HRTIMER_BASE_REALTIME].softirq_time = xtim; in hrtimer_get_softirq_time() 128 base->clock_base[HRTIMER_BASE_MONOTONIC].softirq_time = mono; in hrtimer_get_softirq_time() 129 base->clock_base[HRTIMER_BASE_BOOTTIME].softirq_time = boot; in hrtimer_get_softirq_time() 130 base->clock_base[HRTIMER_BASE_TAI].softirq_time = tai; in hrtimer_get_softirq_time() 155 struct hrtimer_clock_base base; in lock_hrtimer_base() local 158 base = timer->base; in lock_hrtimer_base() 159 if (likely(base != NULL)) { in lock_hrtimer_base() 160 raw_spin_lock_irqsave(&base->cpu_base->lock, *flags); in lock_hrtimer_base() 161 if (likely(base == timer->base)) in lock_hrtimer_base() [all …]
/linux-4.1.27/include/linux/mmc/
D	sh_mmcif.h	102 static inline void sh_mmcif_boot_cmd_send(void __iomem base, in sh_mmcif_boot_cmd_send() argument 105 sh_mmcif_writel(base, MMCIF_CE_INT, 0); in sh_mmcif_boot_cmd_send() 106 sh_mmcif_writel(base, MMCIF_CE_ARG, arg); in sh_mmcif_boot_cmd_send() 107 sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd); in sh_mmcif_boot_cmd_send() 110 static inline int sh_mmcif_boot_cmd_poll(void __iomem base, unsigned long mask) in sh_mmcif_boot_cmd_poll() argument 116 tmp = sh_mmcif_readl(base, MMCIF_CE_INT); in sh_mmcif_boot_cmd_poll() 118 sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask); in sh_mmcif_boot_cmd_poll() 126 static inline int sh_mmcif_boot_cmd(void __iomem *base, in sh_mmcif_boot_cmd() argument 129 sh_mmcif_boot_cmd_send(base, cmd, arg); in sh_mmcif_boot_cmd() 130 return sh_mmcif_boot_cmd_poll(base, 0x00010000); in sh_mmcif_boot_cmd() [all …]
/linux-4.1.27/drivers/scsi/pcmcia/
D	nsp_io.h	15 static inline void nsp_write(unsigned int base, 18 static inline unsigned char nsp_read(unsigned int base, 30 static inline void nsp_write(unsigned int base, in nsp_write() argument 34 outb(val, (base + index)); in nsp_write() 37 static inline unsigned char nsp_read(unsigned int base, in nsp_read() argument 40 return inb(base + index); in nsp_read() 75 static inline void nsp_fifo8_read(unsigned int base, in nsp_fifo8_read() argument 80 nsp_multi_read_1(base, FIFODATA, buf, count); in nsp_fifo8_read() 94 static inline void nsp_fifo16_read(unsigned int base, in nsp_fifo16_read() argument 99 nsp_multi_read_2(base, FIFODATA, buf, count); in nsp_fifo16_read() [all …]
D	nsp_cs.c	274 unsigned int base = data->BaseAddress; in DEF_SCSI_QCMD() local 287 nsp_index_write(base, TRANSFERMODE, transfer_mode_reg); in DEF_SCSI_QCMD() 309 unsigned int base = data->BaseAddress; in nsphw_init() local 311 nsp_dbg(NSP_DEBUG_INIT, "in base=0x%x", base); in nsphw_init() 321 nsp_write(base, IRQCONTROL, IRQCONTROL_ALLMASK); in nsphw_init() 324 nsp_write(base, IFSELECT, IF_IFSEL); in nsphw_init() 326 nsp_index_write(base, SCSIIRQMODE, 0); in nsphw_init() 328 nsp_index_write(base, TRANSFERMODE, MODE_IO8); in nsphw_init() 329 nsp_index_write(base, CLOCKDIV, data->ScsiClockDiv); in nsphw_init() 331 nsp_index_write(base, PARITYCTRL, 0); in nsphw_init() [all …]
/linux-4.1.27/arch/m68k/amiga/
D	cia.c	51 unsigned char cia_set_irq(struct ciabase base, unsigned char mask) in cia_set_irq() argument 55 old = (base->icr_data \|= base->cia->icr); in cia_set_irq() 57 base->icr_data \|= mask; in cia_set_irq() 59 base->icr_data &= ~mask; in cia_set_irq() 60 if (base->icr_data & base->icr_mask) in cia_set_irq() 61 amiga_custom.intreq = IF_SETCLR \| base->int_mask; in cia_set_irq() 62 return old & base->icr_mask; in cia_set_irq() 69 unsigned char cia_able_irq(struct ciabase base, unsigned char mask) in cia_able_irq() argument 73 old = base->icr_mask; in cia_able_irq() 74 base->icr_data \|= base->cia->icr; in cia_able_irq() [all …]
/linux-4.1.27/drivers/irqchip/
D	irq-vic.c	74 void __iomem base; member 100 static void vic_init2(void __iomem base) in vic_init2() argument 105 void __iomem reg = base + VIC_VECT_CNTL0 + (i 4); in vic_init2() 109 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2() 115 void __iomem *base = vic->base; in resume_one_vic() local 117 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); in resume_one_vic() 120 vic_init2(base); in resume_one_vic() 122 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic() 123 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic() 126 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic() [all …]
D	irq-sirfsoc.c	31 sirfsoc_alloc_gc(void __iomem base, unsigned int irq_start, unsigned int num) in sirfsoc_alloc_gc() argument 43 gc->reg_base = base; in sirfsoc_alloc_gc() 52 void __iomem base = sirfsoc_irqdomain->host_data; in sirfsoc_handle_irq() local 55 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); in sirfsoc_handle_irq() 62 void __iomem *base = of_iomap(np, 0); in sirfsoc_irq_init() local 63 if (!base) in sirfsoc_irq_init() 67 &irq_generic_chip_ops, base); in sirfsoc_irq_init() 69 sirfsoc_alloc_gc(base, 0, 32); in sirfsoc_irq_init() 70 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); in sirfsoc_irq_init() 72 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_init() [all …]
D	irq-vt8500.c	76 void __iomem base; / IO Memory base address / member 87 void __iomem base = priv->base; in vt8500_irq_mask() local 88 void __iomem stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); in vt8500_irq_mask() 92 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; in vt8500_irq_mask() 99 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask() 101 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask() 108 void __iomem base = priv->base; in vt8500_irq_unmask() local 111 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask() 113 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask() 119 void __iomem *base = priv->base; in vt8500_irq_set_type() local [all …]
D	irq-gic-common.c	25 void __iomem base, void (sync_access)(void)) in gic_configure_irq() argument 39 val = oldval = readl_relaxed(base + GIC_DIST_CONFIG + confoff); in gic_configure_irq() 49 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { in gic_configure_irq() 50 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); in gic_configure_irq() 61 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); in gic_configure_irq() 62 if (readl_relaxed(base + GIC_DIST_CONFIG + confoff) != val && val != oldval) in gic_configure_irq() 66 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); in gic_configure_irq() 74 void __init gic_dist_config(void __iomem *base, int gic_irqs, in gic_dist_config() argument 84 base + GIC_DIST_CONFIG + i / 4); in gic_dist_config() 90 writel_relaxed(GICD_INT_DEF_PRI_X4, base + GIC_DIST_PRI + i); in gic_dist_config() [all …]
/linux-4.1.27/drivers/gpio/
D	gpio-samsung.c	46 void __iomem reg = chip->base + 0x08; in samsung_gpio_setpull_updown() 61 void __iomem reg = chip->base + 0x08; in samsung_gpio_getpull_updown() 115 void __iomem reg = chip->base + 0x08; in s3c24xx_gpio_setpull_1() 133 void __iomem reg = chip->base + 0x08; in s3c24xx_gpio_getpull_1() 181 void __iomem reg = chip->base; in samsung_gpio_setcfg_2bit() 216 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit() 244 void __iomem reg = chip->base; in samsung_gpio_setcfg_4bit() 279 void __iomem reg = chip->base; in samsung_gpio_getcfg_4bit() 309 void __iomem reg = chip->base; in s3c24xx_gpio_setcfg_abank() 349 con = __raw_readl(chip->base); in s3c24xx_gpio_getcfg_abank() [all …]
D	gpio-pl061.c	53 void __iomem *base; member 69 int gpio = gc->base + offset; in pl061_gpio_request() 79 int gpio = gc->base + offset; in pl061_gpio_free() 95 gpiodir = readb(chip->base + GPIODIR); in pl061_direction_input() 97 writeb(gpiodir, chip->base + GPIODIR); in pl061_direction_input() 114 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_direction_output() 115 gpiodir = readb(chip->base + GPIODIR); in pl061_direction_output() 117 writeb(gpiodir, chip->base + GPIODIR); in pl061_direction_output() 123 writeb(!!value << offset, chip->base + (BIT(offset + 2))); in pl061_direction_output() 133 return !!readb(chip->base + (BIT(offset + 2))); in pl061_get_value() [all …]
D	gpio-f7188x.c	70 static inline int superio_inb(int base, int reg) in superio_inb() argument 72 outb(reg, base); in superio_inb() 73 return inb(base + 1); in superio_inb() 76 static int superio_inw(int base, int reg) in superio_inw() argument 80 outb(reg++, base); in superio_inw() 81 val = inb(base + 1) << 8; in superio_inw() 82 outb(reg, base); in superio_inw() 83 val \|= inb(base + 1); in superio_inw() 88 static inline void superio_outb(int base, int reg, int val) in superio_outb() argument 90 outb(reg, base); in superio_outb() [all …]
D	gpio-omap.c	52 void __iomem base; member 100 void __iomem reg = bank->base; in omap_set_gpio_direction() 118 void __iomem reg = bank->base; in omap_set_gpio_dataout_reg() 136 void __iomem reg = bank->base + bank->regs->dataout; in omap_set_gpio_dataout_mask() 151 void __iomem reg = bank->base + bank->regs->datain; in omap_get_gpio_datain() 158 void __iomem reg = bank->base + bank->regs->dataout; in omap_get_gpio_dataout() 163 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) in omap_gpio_rmw() argument 165 int l = readl_relaxed(base + reg); in omap_gpio_rmw() 172 writel_relaxed(l, base + reg); in omap_gpio_rmw() 182 bank->base + bank->regs->debounce_en); in omap_gpio_dbck_enable() [all …]
/linux-4.1.27/drivers/block/
D	swim.c	66 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) argument 67 #define swim_read(base, reg) in_8(&(base)->read_##reg) argument 90 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) argument 91 #define iwm_read(base, reg) in_8(&(base)->reg) argument 212 struct swim __iomem base; member 219 extern int swim_read_sector_header(struct swim __iomem base, 221 extern int swim_read_sector_data(struct swim __iomem base, 225 static inline void set_swim_mode(struct swim __iomem base, int enable) in set_swim_mode() argument 231 swim_write(base, mode0, 0xf8); in set_swim_mode() 235 iwm_base = (struct iwm __iomem *)base; in set_swim_mode() [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/fifo/
D	g84.c	45 struct nv50_fifo_base base = (void )parent->parent; in g84_fifo_context_attach() local 67 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in g84_fifo_context_attach() 68 nv_wo32(base->eng, addr + 0x00, 0x00190000); in g84_fifo_context_attach() 69 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); in g84_fifo_context_attach() 70 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); in g84_fifo_context_attach() 71 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 \| in g84_fifo_context_attach() 73 nv_wo32(base->eng, addr + 0x10, 0x00000000); in g84_fifo_context_attach() 74 nv_wo32(base->eng, addr + 0x14, 0x00000000); in g84_fifo_context_attach() 85 struct nv50_fifo_base base = (void )parent->parent; in g84_fifo_context_detach() local 107 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); in g84_fifo_context_detach() [all …]
D	nv50.c	51 for (i = priv->base.min, p = 0; i < priv->base.max; i++) { in nv50_fifo_playlist_update_locked() 75 struct nv50_fifo_base base = (void )parent->parent; in nv50_fifo_context_attach() local 89 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in nv50_fifo_context_attach() 90 nv_wo32(base->eng, addr + 0x00, 0x00190000); in nv50_fifo_context_attach() 91 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); in nv50_fifo_context_attach() 92 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); in nv50_fifo_context_attach() 93 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 \| in nv50_fifo_context_attach() 95 nv_wo32(base->eng, addr + 0x10, 0x00000000); in nv50_fifo_context_attach() 96 nv_wo32(base->eng, addr + 0x14, 0x00000000); in nv50_fifo_context_attach() 107 struct nv50_fifo_base base = (void )parent->parent; in nv50_fifo_context_detach() local [all …]
D	gf100.c	39 struct nvkm_fifo base; member 58 struct nvkm_fifo_base base; member 64 struct nvkm_fifo_chan base; member 88 struct gf100_fifo_chan chan = (void )priv->base.channel[i]; in gf100_fifo_runlist_update() 112 struct gf100_fifo_base base = (void )parent->parent; in gf100_fifo_context_attach() local 130 ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, in gf100_fifo_context_attach() 135 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in gf100_fifo_context_attach() 138 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) \| 4); in gf100_fifo_context_attach() 139 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); in gf100_fifo_context_attach() 150 struct gf100_fifo_base base = (void )parent->parent; in gf100_fifo_context_detach() local [all …]
D	gk104.c	62 struct nvkm_fifo base; member 76 struct nvkm_fifo_base base; member 82 struct nvkm_fifo_chan base; member 107 for (i = 0, p = 0; i < priv->base.max; i++) { in gk104_fifo_runlist_update() 108 struct gk104_fifo_chan chan = (void )priv->base.channel[i]; in gk104_fifo_runlist_update() 132 struct gk104_fifo_base base = (void )parent->parent; in gk104_fifo_context_attach() local 143 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in gk104_fifo_context_attach() 154 ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, in gk104_fifo_context_attach() 159 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in gk104_fifo_context_attach() 162 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) \| 4); in gk104_fifo_context_attach() [all …]
/linux-4.1.27/drivers/dma/
D	ste_dma40.c	336 void base; member 392 void base; member 472 struct d40_base base; member 616 return chan->base->virtbase + D40_DREG_PCBASE + in chan_base() 631 void base; in d40_pool_lli_alloc() local 639 base = d40d->lli_pool.pre_alloc_lli; in d40_pool_lli_alloc() 641 d40d->lli_pool.base = NULL; in d40_pool_lli_alloc() 645 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); in d40_pool_lli_alloc() 646 d40d->lli_pool.base = base; in d40_pool_lli_alloc() 648 if (d40d->lli_pool.base == NULL) in d40_pool_lli_alloc() [all …]
/linux-4.1.27/lib/
D	kstrtox.c	23 const char _parse_integer_fixup_radix(const char s, unsigned int base) in _parse_integer_fixup_radix() argument 25 if (base == 0) { in _parse_integer_fixup_radix() 28 base = 16; in _parse_integer_fixup_radix() 30 base = 8; in _parse_integer_fixup_radix() 32 base = 10; in _parse_integer_fixup_radix() 34 if (base == 16 && s[0] == '0' && _tolower(s[1]) == 'x') in _parse_integer_fixup_radix() 47 unsigned int _parse_integer(const char s, unsigned int base, unsigned long long p) in _parse_integer() argument 66 if (val >= base) in _parse_integer() 73 if (res > div_u64(ULLONG_MAX - val, base)) in _parse_integer() 76 res = res * base + val; in _parse_integer() [all …]
D	sort.c	`46 void sort(void *base, size_t num, size_t size, in sort() argument 61 cmp_func(base + c, base + c + size) < 0) in sort() 63 if (cmp_func(base + r, base + c) >= 0) in sort() 65 swap_func(base + r, base + c, size); in sort() 71 swap_func(base, base + i, size); in sort() 75 cmp_func(base + c, base + c + size) < 0) in sort() 77 if (cmp_func(base + r, base + c) >= 0) in sort() 79 swap_func(base + r, base + c, size); in sort()`
/linux-4.1.27/drivers/iommu/
D	msm_iommu.c	119 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); in __flush_iotlb() 126 static void __reset_context(void __iomem *base, int ctx) in __reset_context() argument 128 SET_BPRCOSH(base, ctx, 0); in __reset_context() 129 SET_BPRCISH(base, ctx, 0); in __reset_context() 130 SET_BPRCNSH(base, ctx, 0); in __reset_context() 131 SET_BPSHCFG(base, ctx, 0); in __reset_context() 132 SET_BPMTCFG(base, ctx, 0); in __reset_context() 133 SET_ACTLR(base, ctx, 0); in __reset_context() 134 SET_SCTLR(base, ctx, 0); in __reset_context() 135 SET_FSRRESTORE(base, ctx, 0); in __reset_context() [all …]
D	msm_iommu_dev.c	87 static void msm_iommu_reset(void __iomem *base, int ncb) in msm_iommu_reset() argument 91 SET_RPUE(base, 0); in msm_iommu_reset() 92 SET_RPUEIE(base, 0); in msm_iommu_reset() 93 SET_ESRRESTORE(base, 0); in msm_iommu_reset() 94 SET_TBE(base, 0); in msm_iommu_reset() 95 SET_CR(base, 0); in msm_iommu_reset() 96 SET_SPDMBE(base, 0); in msm_iommu_reset() 97 SET_TESTBUSCR(base, 0); in msm_iommu_reset() 98 SET_TLBRSW(base, 0); in msm_iommu_reset() 99 SET_GLOBAL_TLBIALL(base, 0); in msm_iommu_reset() [all …]
/linux-4.1.27/arch/alpha/kernel/
D	pc873xx.c	12 static unsigned int base, model; variable 17 return base; in pc873xx_get_base() 25 static unsigned char __init pc873xx_read(unsigned int base, int reg) in pc873xx_read() argument 27 outb(reg, base); in pc873xx_read() 28 return inb(base + 1); in pc873xx_read() 31 static void __init pc873xx_write(unsigned int base, int reg, unsigned char data) in pc873xx_write() argument 36 outb(reg, base); in pc873xx_write() 37 outb(data, base + 1); in pc873xx_write() 38 outb(data, base + 1); /* Must be written twice */ in pc873xx_write() 46 while ((base = pc873xx_probelist[index++])) { in pc873xx_probe() [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
D	gt215.c	30 struct nvkm_therm_priv base; member 47 struct dcb_gpio_func *tach = &priv->base.fan->tach; in gt215_therm_init() 50 ret = nvkm_therm_init(&priv->base.base); in gt215_therm_init() 54 g84_sensor_setup(&priv->base.base); in gt215_therm_init() 81 priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl; in gt215_therm_ctor() 82 priv->base.base.pwm_get = nv50_fan_pwm_get; in gt215_therm_ctor() 83 priv->base.base.pwm_set = nv50_fan_pwm_set; in gt215_therm_ctor() 84 priv->base.base.pwm_clock = nv50_fan_pwm_clock; in gt215_therm_ctor() 85 priv->base.base.temp_get = g84_temp_get; in gt215_therm_ctor() 86 priv->base.base.fan_sense = gt215_therm_fan_sense; in gt215_therm_ctor() [all …]
D	gf110.c	29 struct nvkm_therm_priv base; member 124 ret = nvkm_therm_init(&priv->base.base); in gf110_therm_init() 130 if (priv->base.fan->tach.func != DCB_GPIO_UNUSED) { in gf110_therm_init() 131 nv_mask(priv, 0x00d79c, 0x000000ff, priv->base.fan->tach.line); in gf110_therm_init() 153 g84_sensor_setup(&priv->base.base); in gf110_therm_ctor() 155 priv->base.base.pwm_ctrl = gf110_fan_pwm_ctrl; in gf110_therm_ctor() 156 priv->base.base.pwm_get = gf110_fan_pwm_get; in gf110_therm_ctor() 157 priv->base.base.pwm_set = gf110_fan_pwm_set; in gf110_therm_ctor() 158 priv->base.base.pwm_clock = gf110_fan_pwm_clock; in gf110_therm_ctor() 159 priv->base.base.temp_get = g84_temp_get; in gf110_therm_ctor() [all …]
D	gm107.c	29 struct nvkm_therm_priv base; member 74 priv->base.base.pwm_ctrl = gm107_fan_pwm_ctrl; in gm107_therm_ctor() 75 priv->base.base.pwm_get = gm107_fan_pwm_get; in gm107_therm_ctor() 76 priv->base.base.pwm_set = gm107_fan_pwm_set; in gm107_therm_ctor() 77 priv->base.base.pwm_clock = gm107_fan_pwm_clock; in gm107_therm_ctor() 78 priv->base.base.temp_get = g84_temp_get; in gm107_therm_ctor() 79 priv->base.base.fan_sense = gt215_therm_fan_sense; in gm107_therm_ctor() 80 priv->base.sensor.program_alarms = nvkm_therm_program_alarms_polling; in gm107_therm_ctor() 81 return nvkm_therm_preinit(&priv->base.base); in gm107_therm_ctor()
D	g84.c	30 struct nvkm_therm_priv base; member 198 ret = nvkm_therm_init(&priv->base.base); in g84_therm_init() 202 g84_sensor_setup(&priv->base.base); in g84_therm_init() 219 priv->base.base.pwm_ctrl = nv50_fan_pwm_ctrl; in g84_therm_ctor() 220 priv->base.base.pwm_get = nv50_fan_pwm_get; in g84_therm_ctor() 221 priv->base.base.pwm_set = nv50_fan_pwm_set; in g84_therm_ctor() 222 priv->base.base.pwm_clock = nv50_fan_pwm_clock; in g84_therm_ctor() 223 priv->base.base.temp_get = g84_temp_get; in g84_therm_ctor() 224 priv->base.sensor.program_alarms = g84_therm_program_alarms; in g84_therm_ctor() 228 nvkm_therm_sensor_set_threshold_state(&priv->base.base, in g84_therm_ctor() [all …]
/linux-4.1.27/drivers/tty/
D	isicom.c	141 #define InterruptTheCard(base) outw(0, (base) + 0xc) argument 142 #define ClearInterrupt(base) inw((base) + 0x0a) argument 189 unsigned long base; member 223 static inline int WaitTillCardIsFree(unsigned long base) in WaitTillCardIsFree() argument 228 while (!(inw(base + 0xe) & 0x1) && count++ < 100) in WaitTillCardIsFree() 234 return !(inw(base + 0xe) & 0x1); in WaitTillCardIsFree() 239 unsigned long base = card->base; in lock_card() local 245 if (inw(base + 0xe) & 0x1) in lock_card() 252 pr_warn("Failed to lock Card (0x%lx)\n", card->base); in lock_card() 270 unsigned long base = card->base; in raise_dtr() local [all …]
D	goldfish.c	44 void __iomem base; member 60 void __iomem base = qtty->base; in goldfish_tty_do_write() local 62 gf_write64((u64)buf, base + GOLDFISH_TTY_DATA_PTR, in goldfish_tty_do_write() 63 base + GOLDFISH_TTY_DATA_PTR_HIGH); in goldfish_tty_do_write() 64 writel(count, base + GOLDFISH_TTY_DATA_LEN); in goldfish_tty_do_write() 65 writel(GOLDFISH_TTY_CMD_WRITE_BUFFER, base + GOLDFISH_TTY_CMD); in goldfish_tty_do_write() 73 void __iomem *base = qtty->base; in goldfish_tty_interrupt() local 78 count = readl(base + GOLDFISH_TTY_BYTES_READY); in goldfish_tty_interrupt() 84 gf_write64((u64)buf, base + GOLDFISH_TTY_DATA_PTR, in goldfish_tty_interrupt() 85 base + GOLDFISH_TTY_DATA_PTR_HIGH); in goldfish_tty_interrupt() [all …]
/linux-4.1.27/drivers/mtd/chips/
D	cfi_probe.c	`27 static int cfi_probe_chip(struct map_info *map, __u32 base, 38 #define xip_allowed(base, map) \ argument 40 (void) map_read(map, base); \ 45 #define xip_enable(base, map, cfi) \ argument 47 cfi_qry_mode_off(base, map, cfi); \ 48 xip_allowed(base, map); \ 51 #define xip_disable_qry(base, map, cfi) \ argument 54 cfi_qry_mode_on(base, map, cfi); \ 60 #define xip_allowed(base, map) do { } while (0) argument 61 #define xip_enable(base, map, cfi) do { } while (0) argument [all …]`
D	cfi_util.c	26 int __xipram cfi_qry_present(struct map_info map, __u32 base, in cfi_qry_present() argument 37 val[0] = map_read(map, base + osf0x10); in cfi_qry_present() 38 val[1] = map_read(map, base + osf0x11); in cfi_qry_present() 39 val[2] = map_read(map, base + osf0x12); in cfi_qry_present() 54 int __xipram cfi_qry_mode_on(uint32_t base, struct map_info *map, in cfi_qry_mode_on() argument 57 cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); in cfi_qry_mode_on() 58 cfi_send_gen_cmd(0x98, 0x55, base, map, cfi, cfi->device_type, NULL); in cfi_qry_mode_on() 59 if (cfi_qry_present(map, base, cfi)) in cfi_qry_mode_on() 63 cfi_send_gen_cmd(0xF0, 0, base, map, cfi, cfi->device_type, NULL); in cfi_qry_mode_on() 64 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL); in cfi_qry_mode_on() [all …]
/linux-4.1.27/arch/sparc/kernel/
D	btext.c	22 static void draw_byte_32(unsigned char bits, unsigned int base, int rb); 23 static void draw_byte_16(unsigned char bits, unsigned int base, int rb); 24 static void draw_byte_8(unsigned char bits, unsigned int base, int rb); 89 unsigned char base = dispDeviceBase; in calc_base() local 91 base += (x + dispDeviceRect[0]) (dispDeviceDepth >> 3); in calc_base() 92 base += (y + dispDeviceRect[1]) * dispDeviceRowBytes; in calc_base() 93 return base; in calc_base() 98 unsigned int base = (unsigned int )calc_base(0, 0); in btext_clearscreen() local 105 unsigned int *ptr = base; in btext_clearscreen() 108 base += (dispDeviceRowBytes >> 2); in btext_clearscreen() [all …]
D	kstack.h	12 unsigned long base = (unsigned long) tp; in kstack_valid() local 18 if (sp >= (base + sizeof(struct thread_info)) && in kstack_valid() 19 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid() 23 base = (unsigned long) hardirq_stack[tp->cpu]; in kstack_valid() 24 if (sp >= base && in kstack_valid() 25 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid() 27 base = (unsigned long) softirq_stack[tp->cpu]; in kstack_valid() 28 if (sp >= base && in kstack_valid() 29 sp <= (base + THREAD_SIZE - sizeof(struct sparc_stackf))) in kstack_valid() 38 unsigned long base = (unsigned long) tp; in kstack_is_trap_frame() local [all …]
/linux-4.1.27/arch/arm/include/asm/
D	vfpmacros.h	20 .macro VFPFLDMIA, base, tmp in toolkits() 22 LDC p11, cr0, [\base],#334 @ FLDMIAX \base!, {d0-d15} in toolkits() 24 LDC p11, cr0, [\base],#324 @ FLDMIAD \base!, {d0-d15} 31 ldcnel p11, cr0, [\base],#324 @ FLDMIAD \base!, {d16-d31} 32 addeq \base, \base, #324 @ step over unused register space 37 ldceql p11, cr0, [\base],#324 @ FLDMIAD \base!, {d16-d31} 38 addne \base, \base, #324 @ step over unused register space 44 .macro VFPFSTMIA, base, tmp 46 STC p11, cr0, [\base],#334 @ FSTMIAX \base!, {d0-d15} 48 STC p11, cr0, [\base],#324 @ FSTMIAD \base!, {d0-d15} [all …]
D	cti.h	49 void __iomem base; member 66 void __iomem base, int irq, int trig_out) in cti_init() argument 68 cti->base = base; in cti_init() 86 void __iomem base = cti->base; in cti_map_trigger() local 89 val = __raw_readl(base + CTIINEN + trig_in 4); in cti_map_trigger() 91 __raw_writel(val, base + CTIINEN + trig_in * 4); in cti_map_trigger() 93 val = __raw_readl(base + CTIOUTEN + trig_out * 4); in cti_map_trigger() 95 __raw_writel(val, base + CTIOUTEN + trig_out * 4); in cti_map_trigger() 106 __raw_writel(0x1, cti->base + CTICONTROL); in cti_enable() 117 __raw_writel(0, cti->base + CTICONTROL); in cti_disable() [all …]
/linux-4.1.27/drivers/ide/
D	palm_bk3710.c	77 static void palm_bk3710_setudmamode(void __iomem base, unsigned int dev, in palm_bk3710_setudmamode() argument 92 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode() 94 writel(val32, base + BK3710_UDMASTB); in palm_bk3710_setudmamode() 97 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode() 99 writel(val32, base + BK3710_UDMATRP); in palm_bk3710_setudmamode() 102 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode() 104 writel(val32, base + BK3710_UDMAENV); in palm_bk3710_setudmamode() 107 val16 = readw(base + BK3710_UDMACTL) \| (1 << dev); in palm_bk3710_setudmamode() 108 writew(val16, base + BK3710_UDMACTL); in palm_bk3710_setudmamode() 111 static void palm_bk3710_setdmamode(void __iomem base, unsigned int dev, in palm_bk3710_setdmamode() argument [all …]
D	siimage.c	94 unsigned long base = (unsigned long)hwif->hwif_data; in siimage_selreg() local 96 base += 0xA0 + r; in siimage_selreg() 98 base += hwif->channel << 6; in siimage_selreg() 100 base += hwif->channel << 4; in siimage_selreg() 101 return base; in siimage_selreg() 117 unsigned long base = (unsigned long)hwif->hwif_data; in siimage_seldev() local 120 base += 0xA0 + r; in siimage_seldev() 122 base += hwif->channel << 6; in siimage_seldev() 124 base += hwif->channel << 4; in siimage_seldev() 125 base \|= unit << unit; in siimage_seldev() [all …]
D	tx4939ide.c	84 static u16 tx4939ide_readw(void __iomem base, u32 reg) in tx4939ide_readw() argument 86 return __raw_readw(base + tx4939ide_swizzlew(reg)); in tx4939ide_readw() 88 static u8 tx4939ide_readb(void __iomem base, u32 reg) in tx4939ide_readb() argument 90 return __raw_readb(base + tx4939ide_swizzleb(reg)); in tx4939ide_readb() 92 static void tx4939ide_writel(u32 val, void __iomem base, u32 reg) in tx4939ide_writel() argument 94 __raw_writel(val, base + tx4939ide_swizzlel(reg)); in tx4939ide_writel() 96 static void tx4939ide_writew(u16 val, void __iomem base, u32 reg) in tx4939ide_writew() argument 98 __raw_writew(val, base + tx4939ide_swizzlew(reg)); in tx4939ide_writew() 100 static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg) in tx4939ide_writeb() argument 102 __raw_writeb(val, base + tx4939ide_swizzleb(reg)); in tx4939ide_writeb() [all …]
/linux-4.1.27/arch/arm/mm/
D	cache-l2x0.c	73 static void l2c_write_sec(unsigned long val, void __iomem base, unsigned reg) in l2c_write_sec() argument 75 if (val == readl_relaxed(base + reg)) in l2c_write_sec() 80 writel_relaxed(val, base + reg); in l2c_write_sec() 88 static inline void l2c_set_debug(void __iomem base, unsigned long val) in l2c_set_debug() argument 90 l2c_write_sec(val, base, L2X0_DEBUG_CTRL); in l2c_set_debug() 99 static inline void l2c_unlock(void __iomem base, unsigned num) in l2c_unlock() argument 104 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + in l2c_unlock() 106 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + in l2c_unlock() 111 static void l2c_configure(void __iomem base) in l2c_configure() argument 119 l2x0_data->configure(base); in l2c_configure() [all …]
/linux-4.1.27/drivers/gpu/drm/msm/dsi/
D	dsi_phy.c	37 void __iomem base; member 175 void __iomem base = phy->reg_base; in dsi_28nm_phy_regulator_ctrl() local 178 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0); in dsi_28nm_phy_regulator_ctrl() 182 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0); in dsi_28nm_phy_regulator_ctrl() 183 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1); in dsi_28nm_phy_regulator_ctrl() 184 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0); in dsi_28nm_phy_regulator_ctrl() 185 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0); in dsi_28nm_phy_regulator_ctrl() 186 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3); in dsi_28nm_phy_regulator_ctrl() 187 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9); in dsi_28nm_phy_regulator_ctrl() 188 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7); in dsi_28nm_phy_regulator_ctrl() [all …]
/linux-4.1.27/drivers/gpu/drm/msm/mdp/mdp5/
D	mdp5_cfg.c	`29 .base = { 0x00100 }, 42 .base = { 0x00600, 0x00700, 0x00800, 0x00900, 0x00a00 }, 47 .base = { 0x01200, 0x01600, 0x01a00 }, 51 .base = { 0x01e00, 0x02200, 0x02600 }, 55 .base = { 0x02a00, 0x02e00 }, 59 .base = { 0x03200, 0x03600, 0x03a00, 0x03e00, 0x04200 }, 64 .base = { 0x04600, 0x04a00, 0x04e00 }, 68 .base = { 0x13100, 0x13300 }, /* NOTE: no ad in v1.0 */ 72 .base = { 0x12d00, 0x12e00, 0x12f00 }, 75 .base = { 0x12500, 0x12700, 0x12900, 0x12b00 }, [all …]`
/linux-4.1.27/drivers/gpu/drm/ttm/
D	ttm_object.c	158 struct ttm_base_object *base, in ttm_base_object_init() argument 168 base->shareable = shareable; in ttm_base_object_init() 169 base->tfile = ttm_object_file_ref(tfile); in ttm_base_object_init() 170 base->refcount_release = refcount_release; in ttm_base_object_init() 171 base->ref_obj_release = ref_obj_release; in ttm_base_object_init() 172 base->object_type = object_type; in ttm_base_object_init() 173 kref_init(&base->refcount); in ttm_base_object_init() 176 &base->hash, in ttm_base_object_init() 177 (unsigned long)base, 31, 0, 0); in ttm_base_object_init() 182 ret = ttm_ref_object_add(tfile, base, TTM_REF_USAGE, NULL); in ttm_base_object_init() [all …]
/linux-4.1.27/drivers/usb/phy/
D	phy-tegra-usb.c	208 void __iomem base = phy->regs; in set_pts() local 212 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts() 215 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_pts() 217 val = readl(base + TEGRA_USB_PORTSC1) & ~TEGRA_PORTSC1_RWC_BITS; in set_pts() 220 writel(val, base + TEGRA_USB_PORTSC1); in set_pts() 226 void __iomem base = phy->regs; in set_phcd() local 230 val = readl(base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd() 235 writel(val, base + TEGRA_USB_HOSTPC1_DEVLC); in set_phcd() 237 val = readl(base + TEGRA_USB_PORTSC1) & ~PORT_RWC_BITS; in set_phcd() 242 writel(val, base + TEGRA_USB_PORTSC1); in set_phcd() [all …]
D	phy-rcar-gen2-usb.c	23 void __iomem base; member 53 static int __rcar_gen2_usbhs_phy_enable(void __iomem base) in __rcar_gen2_usbhs_phy_enable() argument 59 val = ioread32(base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable() 61 iowrite32(val, base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable() 63 val = ioread16(base + USBHS_LPSTS_REG); in __rcar_gen2_usbhs_phy_enable() 65 iowrite16(val, base + USBHS_LPSTS_REG); in __rcar_gen2_usbhs_phy_enable() 68 val = ioread32(base + USBHS_UGSTS_REG); in __rcar_gen2_usbhs_phy_enable() 70 val = ioread32(base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable() 72 iowrite32(val, base + USBHS_UGCTRL_REG); in __rcar_gen2_usbhs_phy_enable() 83 static int __rcar_gen2_usbhs_phy_disable(void __iomem *base) in __rcar_gen2_usbhs_phy_disable() argument [all …]
/linux-4.1.27/arch/arm/mach-mmp/
D	devices.c	81 static unsigned int u2o_get(void __iomem base, unsigned int offset) in u2o_get() argument 83 return readl_relaxed(base + offset); in u2o_get() 86 static void u2o_set(void __iomem base, unsigned int offset, in u2o_set() argument 91 reg = readl_relaxed(base + offset); in u2o_set() 93 writel_relaxed(reg, base + offset); in u2o_set() 94 readl_relaxed(base + offset); in u2o_set() 97 static void u2o_clear(void __iomem *base, unsigned int offset, in u2o_clear() argument 102 reg = readl_relaxed(base + offset); in u2o_clear() 104 writel_relaxed(reg, base + offset); in u2o_clear() 105 readl_relaxed(base + offset); in u2o_clear() [all …]
/linux-4.1.27/drivers/clk/
D	clk-efm32gg.c	28 void __iomem *base; in efm32gg_cmu_init() local 33 base = of_iomap(np, 0); in efm32gg_cmu_init() 34 if (!base) { in efm32gg_cmu_init() 43 "HFXO", 0, base + CMU_HFPERCLKEN0, 0, 0, NULL); in efm32gg_cmu_init() 45 "HFXO", 0, base + CMU_HFPERCLKEN0, 1, 0, NULL); in efm32gg_cmu_init() 47 "HFXO", 0, base + CMU_HFPERCLKEN0, 2, 0, NULL); in efm32gg_cmu_init() 49 "HFXO", 0, base + CMU_HFPERCLKEN0, 3, 0, NULL); in efm32gg_cmu_init() 51 "HFXO", 0, base + CMU_HFPERCLKEN0, 4, 0, NULL); in efm32gg_cmu_init() 53 "HFXO", 0, base + CMU_HFPERCLKEN0, 5, 0, NULL); in efm32gg_cmu_init() 55 "HFXO", 0, base + CMU_HFPERCLKEN0, 6, 0, NULL); in efm32gg_cmu_init() [all …]
/linux-4.1.27/sound/soc/txx9/
D	txx9aclc-ac97.c	44 return __raw_readl(drvdata->base + ACINTSTS) & ACINT_REGACCRDY; in txx9aclc_regready() 52 void __iomem base = drvdata->base; in txx9aclc_ac97_read() local 55 if (!(__raw_readl(base + ACINTSTS) & ACINT_CODECRDY(ac97->num))) in txx9aclc_ac97_read() 59 __raw_writel(dat, base + ACREGACC); in txx9aclc_ac97_read() 60 __raw_writel(ACINT_REGACCRDY, base + ACINTEN); in txx9aclc_ac97_read() 62 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); in txx9aclc_ac97_read() 67 dat = __raw_readl(base + ACREGACC); in txx9aclc_ac97_read() 76 __raw_writel(ACINT_REGACCRDY, base + ACINTDIS); in txx9aclc_ac97_read() 85 void __iomem base = drvdata->base; in txx9aclc_ac97_write() local 89 base + ACREGACC); in txx9aclc_ac97_write() [all …]
/linux-4.1.27/arch/arm/plat-samsung/
D	pm-gpio.c	35 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_1bit_save() 36 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_1bit_save() 41 void __iomem *base = chip->base; in samsung_gpio_pm_1bit_resume() local 42 u32 old_gpcon = __raw_readl(base + OFFS_CON); in samsung_gpio_pm_1bit_resume() 43 u32 old_gpdat = __raw_readl(base + OFFS_DAT); in samsung_gpio_pm_1bit_resume() 54 __raw_writel(gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume() 58 __raw_writel(gps_gpdat, base + OFFS_DAT); in samsung_gpio_pm_1bit_resume() 59 __raw_writel(gps_gpcon, base + OFFS_CON); in samsung_gpio_pm_1bit_resume() 72 chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); in samsung_gpio_pm_2bit_save() 73 chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); in samsung_gpio_pm_2bit_save() [all …]
/linux-4.1.27/tools/perf/tests/attr/
D	test-stat-detailed-3	`8 [event1:base-stat] 14 [event2:base-stat] 20 [event3:base-stat] 26 [event4:base-stat] 32 [event5:base-stat] 38 [event6:base-stat] 44 [event7:base-stat] 50 [event8:base-stat] 56 [event9:base-stat] 62 [event10:base-stat] [all …]`
D	test-stat-detailed-2	`8 [event1:base-stat] 14 [event2:base-stat] 20 [event3:base-stat] 26 [event4:base-stat] 32 [event5:base-stat] 38 [event6:base-stat] 44 [event7:base-stat] 50 [event8:base-stat] 56 [event9:base-stat] 62 [event10:base-stat] [all …]`
D	test-stat-detailed-1	`8 [event1:base-stat] 14 [event2:base-stat] 20 [event3:base-stat] 26 [event4:base-stat] 32 [event5:base-stat] 38 [event6:base-stat] 44 [event7:base-stat] 50 [event8:base-stat] 56 [event9:base-stat] 62 [event10:base-stat] [all …]`
D	test-stat-default	`7 [event1:base-stat] 13 [event2:base-stat] 19 [event3:base-stat] 25 [event4:base-stat] 31 [event5:base-stat] 37 [event6:base-stat] 43 [event7:base-stat] 49 [event8:base-stat] 55 [event9:base-stat] 61 [event10:base-stat]`
/linux-4.1.27/drivers/mmc/host/
D	mmci_qcom_dml.c	60 void __iomem *base = host->base + DML_OFFSET; in dml_start_xfer() local 65 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer() 68 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer() 71 writel_relaxed(data->blksz, base + DML_PRODUCER_BAM_BLOCK_SIZE); in dml_start_xfer() 75 base + DML_PRODUCER_BAM_TRANS_SIZE); in dml_start_xfer() 77 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer() 79 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer() 81 writel_relaxed(1, base + DML_PRODUCER_START); in dml_start_xfer() 85 config = readl_relaxed(base + DML_CONFIG); in dml_start_xfer() 88 writel_relaxed(config, base + DML_CONFIG); in dml_start_xfer() [all …]
/linux-4.1.27/mm/
D	memblock.c	74 static inline phys_addr_t memblock_cap_size(phys_addr_t base, phys_addr_t size) in memblock_cap_size() argument 76 return size = min(*size, (phys_addr_t)ULLONG_MAX - base); in memblock_cap_size() 89 phys_addr_t base, phys_addr_t size) in memblock_overlaps_region() argument 94 phys_addr_t rgnbase = type->regions[i].base; in memblock_overlaps_region() 96 if (memblock_addrs_overlap(base, size, rgnbase, rgnsize)) in memblock_overlaps_region() 270 type->regions[0].base = 0; in memblock_remove_region() 437 if (this->base + this->size != next->base \|\| in memblock_merge_regions() 441 BUG_ON(this->base + this->size > next->base); in memblock_merge_regions() 466 int idx, phys_addr_t base, in memblock_insert_region() argument 474 rgn->base = base; in memblock_insert_region() [all …]
/linux-4.1.27/arch/arm/mach-realview/include/mach/
D	uncompress.h	29 #define AMBA_UART_DR(base) ((volatile unsigned char )((base) + 0x00)) argument 30 #define AMBA_UART_LCRH(base) ((volatile unsigned char )((base) + 0x2c)) argument 31 #define AMBA_UART_CR(base) ((volatile unsigned char )((base) + 0x30)) argument 32 #define AMBA_UART_FR(base) ((volatile unsigned char )((base) + 0x18)) argument 58 unsigned long base = get_uart_base(); in putc() local 60 while (AMBA_UART_FR(base) & (1 << 5)) in putc() 63 AMBA_UART_DR(base) = c; in putc() 68 unsigned long base = get_uart_base(); in flush() local 70 while (AMBA_UART_FR(base) & (1 << 3)) in flush()
/linux-4.1.27/drivers/atm/
D	nicstarmac.c	110 writel((val),(base)+(reg)) 112 readl((base)+(reg)) 121 u_int32_t nicstar_read_eprom_status(virt_addr_t base) 128 val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0; 131 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 141 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 143 rbyte \|= (((NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) 145 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 149 NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE, 2); 161 static u_int8_t read_eprom_byte(virt_addr_t base, u_int8_t offset) in read_eprom_byte() argument [all …]
/linux-4.1.27/arch/arm/common/
D	scoop.c	36 void __iomem base; member 48 iowrite16(0x0100, sdev->base + SCOOP_MCR); / 00 / in reset_scoop() 49 iowrite16(0x0000, sdev->base + SCOOP_CDR); / 04 / in reset_scoop() 50 iowrite16(0x0000, sdev->base + SCOOP_CCR); / 10 / in reset_scoop() 51 iowrite16(0x0000, sdev->base + SCOOP_IMR); / 18 / in reset_scoop() 52 iowrite16(0x00FF, sdev->base + SCOOP_IRM); / 14 / in reset_scoop() 53 iowrite16(0x0000, sdev->base + SCOOP_ISR); / 1C */ in reset_scoop() 54 iowrite16(0x0000, sdev->base + SCOOP_IRM); in reset_scoop() 62 gpwr = ioread16(sdev->base + SCOOP_GPWR); in __scoop_gpio_set() 67 iowrite16(gpwr, sdev->base + SCOOP_GPWR); in __scoop_gpio_set() [all …]
D	timer-sp.c	74 void __init __sp804_clocksource_and_sched_clock_init(void __iomem base, in __sp804_clocksource_and_sched_clock_init() argument 96 writel(0, base + TIMER_CTRL); in __sp804_clocksource_and_sched_clock_init() 97 writel(0xffffffff, base + TIMER_LOAD); in __sp804_clocksource_and_sched_clock_init() 98 writel(0xffffffff, base + TIMER_VALUE); in __sp804_clocksource_and_sched_clock_init() 100 base + TIMER_CTRL); in __sp804_clocksource_and_sched_clock_init() 102 clocksource_mmio_init(base + TIMER_VALUE, name, in __sp804_clocksource_and_sched_clock_init() 106 sched_clock_base = base; in __sp804_clocksource_and_sched_clock_init() 183 void __init __sp804_clockevents_init(void __iomem base, unsigned int irq, struct clk *clk, const c… in __sp804_clockevents_init() argument 200 clkevt_base = base; in __sp804_clockevents_init() 206 writel(0, base + TIMER_CTRL); in __sp804_clockevents_init() [all …]
D	locomo.c	69 void __iomem base; member 150 req = locomo_readl(lchip->base + LOCOMO_ICR) & 0x0f00; in locomo_handler() 172 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_mask_irq() 174 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_mask_irq() 181 r = locomo_readl(lchip->base + LOCOMO_ICR); in locomo_unmask_irq() 183 locomo_writel(r, lchip->base + LOCOMO_ICR); in locomo_unmask_irq() 249 dev->mapbase = lchip->base + info->offset; in locomo_init_one_child() 289 save->LCM_GPO = locomo_readl(lchip->base + LOCOMO_GPO); / GPIO / in locomo_suspend() 290 locomo_writel(0x00, lchip->base + LOCOMO_GPO); in locomo_suspend() 291 save->LCM_SPICT = locomo_readl(lchip->base + LOCOMO_SPI + LOCOMO_SPICT); / SPI */ in locomo_suspend() [all …]
D	sa1111.c	108 void __iomem base; member 204 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_irq_handler() 242 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_mask_lowirq() 253 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_unmask_lowirq() 271 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_retrigger_lowirq() 293 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_type_lowirq() 317 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_wake_lowirq() 344 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_mask_highirq() 355 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_unmask_highirq() 373 void __iomem mapbase = sachip->base + SA1111_INTC; in sa1111_retrigger_highirq() [all …]
/linux-4.1.27/arch/x86/mm/
D	amdtopology.c	`99 u64 base, limit; in amd_numa_init() local 101 base = read_pci_config(0, nb, 1, 0x40 + i*8); in amd_numa_init() 105 if ((base & 3) == 0) { in amd_numa_init() 112 base, limit); in amd_numa_init() 118 i, base); in amd_numa_init() 121 if ((base >> 8) & 3 \|\| (limit >> 8) & 3) { in amd_numa_init() 123 nodeid, (base >> 8) & 3, (limit >> 8) & 3); in amd_numa_init() 138 if (limit <= base) in amd_numa_init() 141 base >>= 16; in amd_numa_init() 142 base <<= 24; in amd_numa_init() [all …]`
/linux-4.1.27/arch/mips/include/asm/netlogic/xlp-hal/
D	pic.h	228 nlm_9xx_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, in nlm_9xx_pic_write_irt() argument 238 nlm_write_pic_reg(base, PIC_9XX_IRT(irt_num), val); in nlm_9xx_pic_write_irt() 242 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, in nlm_pic_write_irt() argument 252 nlm_write_pic_reg(base, PIC_IRT(irt_num), val); in nlm_pic_write_irt() 256 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, in nlm_pic_write_irt_direct() argument 260 nlm_9xx_pic_write_irt(base, irt_num, en, nmi, sch, vec, in nlm_pic_write_irt_direct() 263 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, in nlm_pic_write_irt_direct() 269 nlm_pic_read_timer(uint64_t base, int timer) in nlm_pic_read_timer() argument 271 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); in nlm_pic_read_timer() 275 nlm_pic_read_timer32(uint64_t base, int timer) in nlm_pic_read_timer32() argument [all …]
D	uart.h	103 nlm_uart_set_baudrate(uint64_t base, int baud) in nlm_uart_set_baudrate() argument 107 lcr = nlm_read_uart_reg(base, UART_LINE_CTL); in nlm_uart_set_baudrate() 110 nlm_write_uart_reg(base, UART_LINE_CTL, lcr \| (1 << 7)); in nlm_uart_set_baudrate() 111 nlm_write_uart_reg(base, UART_DIVISOR0, in nlm_uart_set_baudrate() 113 nlm_write_uart_reg(base, UART_DIVISOR1, in nlm_uart_set_baudrate() 117 nlm_write_uart_reg(base, UART_LINE_CTL, lcr); in nlm_uart_set_baudrate() 121 nlm_uart_outbyte(uint64_t base, char c) in nlm_uart_outbyte() argument 126 lsr = nlm_read_uart_reg(base, UART_LINE_STS); in nlm_uart_outbyte() 131 nlm_write_uart_reg(base, UART_TX_DATA, (int)c); in nlm_uart_outbyte() 135 nlm_uart_inbyte(uint64_t base) in nlm_uart_inbyte() argument [all …]
/linux-4.1.27/include/sound/
D	snd_wavefront.h	22 unsigned long base; /* I/O port address / member 50 unsigned long base; / low i/o port address / member 53 #define mpu_data_port base 54 #define mpu_command_port base + 1 / write semantics / 55 #define mpu_status_port base + 1 / read semantics / 56 #define data_port base + 2 57 #define status_port base + 3 / read semantics / 58 #define control_port base + 3 / write semantics / 59 #define block_port base + 4 / 16 bit, writeonly / 60 #define last_block_port base + 6 / 16 bit, writeonly */ [all …]
/linux-4.1.27/drivers/gpu/drm/i915/
D	i915_gem_debug.c	45 if (obj->base.dev != dev \|\| in i915_verify_lists() 46 !atomic_read(&obj->base.refcount.refcount)) { in i915_verify_lists() 51 (obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) { in i915_verify_lists() 55 obj->base.read_domains); in i915_verify_lists() 57 } else if (obj->base.write_domain && list_empty(&obj->gpu_write_list)) { in i915_verify_lists() 60 obj->base.write_domain, in i915_verify_lists() 67 if (obj->base.dev != dev \|\| in i915_verify_lists() 68 !atomic_read(&obj->base.refcount.refcount)) { in i915_verify_lists() 73 (obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0 \|\| in i915_verify_lists() 78 obj->base.write_domain, in i915_verify_lists() [all …]
D	intel_dp_mst.c	36 struct intel_dp_mst_encoder intel_mst = enc_to_mst(&encoder->base); in intel_dp_mst_compute_config() 42 struct drm_display_mode adjusted_mode = &pipe_config->base.adjusted_mode; in intel_dp_mst_compute_config() 71 state = pipe_config->base.state; in intel_dp_mst_compute_config() 77 if (state->connector_states[i]->best_encoder == &encoder->base) { in intel_dp_mst_compute_config() 105 struct intel_dp_mst_encoder intel_mst = enc_to_mst(&encoder->base); in intel_mst_disable_dp() 122 struct intel_dp_mst_encoder intel_mst = enc_to_mst(&encoder->base); in intel_mst_post_disable_dp() 138 intel_dig_port->base.post_disable(&intel_dig_port->base); in intel_mst_post_disable_dp() 145 struct intel_dp_mst_encoder intel_mst = enc_to_mst(&encoder->base); in intel_mst_pre_enable_dp() 148 struct drm_device dev = encoder->base.dev; in intel_mst_pre_enable_dp() 155 struct drm_crtc *crtc = encoder->base.crtc; in intel_mst_pre_enable_dp() [all …]
D	intel_psr.c	79 struct drm_device dev = dig_port->base.base.dev; in intel_psr_write_vsc() 81 struct intel_crtc crtc = to_intel_crtc(dig_port->base.base.crtc); in intel_psr_write_vsc() 107 struct drm_device dev = intel_dig_port->base.base.dev; in vlv_psr_setup_vsc() 109 struct drm_crtc crtc = intel_dig_port->base.base.crtc; in vlv_psr_setup_vsc() 142 struct drm_device dev = dig_port->base.base.dev; in hsw_psr_enable_sink() 201 struct drm_device dev = dig_port->base.base.dev; in vlv_psr_enable_source() 203 struct drm_crtc crtc = dig_port->base.base.crtc; in vlv_psr_enable_source() 216 struct drm_device dev = dig_port->base.base.dev; in vlv_psr_activate() 218 struct drm_crtc crtc = dig_port->base.base.crtc; in vlv_psr_activate() 233 struct drm_device dev = dig_port->base.base.dev; in hsw_psr_enable_source() [all …]
/linux-4.1.27/drivers/clocksource/
D	time-efm32.c	47 void __iomem *base; member 59 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode() 60 writel_relaxed(ddata->periodic_top, ddata->base + TIMERn_TOP); in efm32_clock_event_set_mode() 64 ddata->base + TIMERn_CTRL); in efm32_clock_event_set_mode() 65 writel_relaxed(TIMERn_CMD_START, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode() 69 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode() 74 ddata->base + TIMERn_CTRL); in efm32_clock_event_set_mode() 79 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_mode() 93 writel_relaxed(TIMERn_CMD_STOP, ddata->base + TIMERn_CMD); in efm32_clock_event_set_next_event() 94 writel_relaxed(evt, ddata->base + TIMERn_CNT); in efm32_clock_event_set_next_event() [all …]
D	asm9260_timer.c	109 void __iomem *base; member 117 writel_relaxed(delta, priv.base + HW_MR0); in asm9260_timer_set_next_event() 119 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_next_event() 127 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG); in asm9260_timer_set_mode() 133 priv.base + HW_MCR + CLR_REG); in asm9260_timer_set_mode() 135 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0); in asm9260_timer_set_mode() 137 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG); in asm9260_timer_set_mode() 142 priv.base + HW_MCR + SET_REG); in asm9260_timer_set_mode() 163 writel_relaxed(BM_IR_MR0, priv.base + HW_IR); in asm9260_timer_interrupt() 180 priv.base = of_io_request_and_map(np, 0, np->name); in asm9260_timer_init() [all …]
D	moxart_timer.c	58 static void __iomem *base; variable 67 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_mode() 68 writel(~0, base + TIMER1_BASE + REG_LOAD); in moxart_clkevt_mode() 71 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); in moxart_clkevt_mode() 72 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_mode() 77 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_mode() 87 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_next_event() 89 u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; in moxart_clkevt_next_event() 90 writel(u, base + TIMER1_BASE + REG_MATCH1); in moxart_clkevt_next_event() 92 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_next_event() [all …]
/linux-4.1.27/drivers/i2c/busses/
D	i2c-wmt.c	90 void __iomem *base; member 102 while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) { in wmt_i2c_wait_bus_not_busy() 147 writew(0, i2c_dev->base + REG_CDR); in wmt_i2c_write() 149 writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); in wmt_i2c_write() 153 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write() 155 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write() 157 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write() 159 writew(val, i2c_dev->base + REG_CR); in wmt_i2c_write() 171 writew(tcr_val, i2c_dev->base + REG_TCR); in wmt_i2c_write() 174 val = readw(i2c_dev->base + REG_CR); in wmt_i2c_write() [all …]
D	i2c-elektor.c	44 static int base; variable 144 if (!request_region(base, 2, pcf_isa_ops.name)) { in pcf_isa_init() 146 "in use\n", pcf_isa_ops.name, base); in pcf_isa_init() 149 base_iomem = ioport_map(base, 2); in pcf_isa_init() 152 pcf_isa_ops.name, base); in pcf_isa_init() 153 release_region(base, 2); in pcf_isa_init() 157 if (!request_mem_region(base, 2, pcf_isa_ops.name)) { in pcf_isa_init() 159 "is in use\n", pcf_isa_ops.name, base); in pcf_isa_init() 162 base_iomem = ioremap(base, 2); in pcf_isa_init() 165 "failed\n", pcf_isa_ops.name, base); in pcf_isa_init() [all …]
D	i2c-st.c	189 void __iomem *base; member 247 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) in st_i2c_flush_rx_fifo() 250 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & in st_i2c_flush_rx_fifo() 254 readl_relaxed(i2c_dev->base + SSC_RBUF); in st_i2c_flush_rx_fifo() 265 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); in st_i2c_soft_reset() 266 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); in st_i2c_soft_reset() 283 writel_relaxed(val, i2c_dev->base + SSC_CLR); in st_i2c_hw_config() 287 writel_relaxed(val, i2c_dev->base + SSC_CTL); in st_i2c_hw_config() 294 writel_relaxed(val, i2c_dev->base + SSC_BRG); in st_i2c_hw_config() 297 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); in st_i2c_hw_config() [all …]
D	i2c-axxia.c	96 void __iomem *base; member 111 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_disable() 112 writel(int_en & ~mask, idev->base + MST_INT_ENABLE); in i2c_int_disable() 119 int_en = readl(idev->base + MST_INT_ENABLE); in i2c_int_enable() 120 writel(int_en \| mask, idev->base + MST_INT_ENABLE); in i2c_int_enable() 145 writel(0x01, idev->base + SOFT_RESET); in axxia_i2c_init() 147 while (readl(idev->base + SOFT_RESET) & 1) { in axxia_i2c_init() 155 writel(0x1, idev->base + GLOBAL_CONTROL); in axxia_i2c_init() 170 writel(t_high, idev->base + SCL_HIGH_PERIOD); in axxia_i2c_init() 172 writel(t_low, idev->base + SCL_LOW_PERIOD); in axxia_i2c_init() [all …]
D	i2c-bcm-kona.c	157 void __iomem *base; member 178 dev->base + CS_OFFSET); in bcm_kona_i2c_send_cmd_to_ctrl() 185 dev->base + CS_OFFSET); in bcm_kona_i2c_send_cmd_to_ctrl() 192 dev->base + CS_OFFSET); in bcm_kona_i2c_send_cmd_to_ctrl() 198 dev->base + CS_OFFSET); in bcm_kona_i2c_send_cmd_to_ctrl() 208 writel(readl(dev->base + CLKEN_OFFSET) \| CLKEN_CLKEN_MASK, in bcm_kona_i2c_enable_clock() 209 dev->base + CLKEN_OFFSET); in bcm_kona_i2c_enable_clock() 214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, in bcm_kona_i2c_disable_clock() 215 dev->base + CLKEN_OFFSET); in bcm_kona_i2c_disable_clock() 221 uint32_t status = readl(dev->base + ISR_OFFSET); in bcm_kona_i2c_isr() [all …]
D	i2c-sirf.c	71 void __iomem *base; member 96 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); in i2c_sirfsoc_read_data() 116 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_queue_cmd() 129 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_queue_cmd() 131 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); in i2c_sirfsoc_queue_cmd() 137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); in i2c_sirfsoc_queue_cmd() 143 u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq() 148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); in i2c_sirfsoc_irq() 160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) \| SIRFSOC_I2C_RESET, in i2c_sirfsoc_irq() 161 siic->base + SIRFSOC_I2C_CTRL); in i2c_sirfsoc_irq() [all …]
D	i2c-bcm-iproc.c	91 void __iomem *base; member 107 u32 status = readl(iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_isr() 114 writel(status, iproc_i2c->base + IS_OFFSET); in bcm_iproc_i2c_isr() 126 val = readl(iproc_i2c->base + M_CMD_OFFSET); in bcm_iproc_i2c_check_status() 164 if (!!(readl(iproc_i2c->base + M_CMD_OFFSET) & in bcm_iproc_i2c_xfer_single_msg() 172 writel(addr, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 183 writel(val, iproc_i2c->base + M_TX_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 196 writel(1 << IE_M_START_BUSY_SHIFT, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 209 writel(val, iproc_i2c->base + M_CMD_OFFSET); in bcm_iproc_i2c_xfer_single_msg() 214 writel(0, iproc_i2c->base + IE_OFFSET); in bcm_iproc_i2c_xfer_single_msg() [all …]
D	i2c-riic.c	96 void __iomem base; member 115 writeb((readb(riic->base + reg) & ~clear) \| set, riic->base + reg); in riic_clear_set_bit() 129 if (readb(riic->base + RIIC_ICCR2) & ICCR2_BBSY) { in riic_xfer() 137 writeb(0, riic->base + RIIC_ICSR2); in riic_xfer() 145 writeb(ICIER_NAKIE \| ICIER_TIE, riic->base + RIIC_ICIER); in riic_xfer() 147 writeb(start_bit, riic->base + RIIC_ICCR2); in riic_xfer() 202 writeb(val, riic->base + RIIC_ICDRT); in riic_tdre_isr() 211 if (readb(riic->base + RIIC_ICSR2) & ICSR2_NACKF) { in riic_tend_isr() 213 readb(riic->base + RIIC_ICDRR); / dummy read */ in riic_tend_isr() 220 writeb(ICCR2_SP, riic->base + RIIC_ICCR2); in riic_tend_isr() [all …]
D	i2c-nforce2.c	64 int base; member 82 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC / 83 #define NVIDIA_SMB_STS (smbus->base + 0x01) / status / 84 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) / address / 85 #define NVIDIA_SMB_CMD (smbus->base + 0x03) / command / 86 #define NVIDIA_SMB_DATA (smbus->base + 0x04) / 32 data registers / 87 #define NVIDIA_SMB_BCNT (smbus->base + 0x24) / number of data 89 #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to 92 #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */ 331 smbus->base = pci_resource_start(dev, bar); in nforce2_probe_smb() [all …]
/linux-4.1.27/arch/powerpc/kernel/
D	btext.c	154 unsigned long base, offset, size; in btext_map() local 161 base = ((unsigned long) dispDeviceBase) & 0xFFFFF000UL; in btext_map() 162 offset = ((unsigned long) dispDeviceBase) - base; in btext_map() 165 vbase = __ioremap(base, size, _PAGE_NO_CACHE); in btext_map() 269 unsigned char base; in calc_base() local 271 base = logicalDisplayBase; in calc_base() 272 if (base == 0) in calc_base() 273 base = dispDeviceBase; in calc_base() 274 base += (x + dispDeviceRect[0]) (dispDeviceDepth >> 3); in calc_base() 275 base += (y + dispDeviceRect[1]) * dispDeviceRowBytes; in calc_base() [all …]
/linux-4.1.27/drivers/virtio/
D	virtio_mmio.c	89 void __iomem base; member 120 writel(1, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features() 121 features = readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES); in vm_get_features() 124 writel(0, vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES_SEL); in vm_get_features() 125 features \|= readl(vm_dev->base + VIRTIO_MMIO_DEVICE_FEATURES); in vm_get_features() 144 writel(1, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features() 146 vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES); in vm_finalize_features() 148 writel(0, vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES_SEL); in vm_finalize_features() 150 vm_dev->base + VIRTIO_MMIO_DRIVER_FEATURES); in vm_finalize_features() 159 void __iomem base = vm_dev->base + VIRTIO_MMIO_CONFIG; in vm_get() local [all …]
/linux-4.1.27/drivers/gpu/ipu-v3/
D	ipu-dp.c	64 void __iomem base; member 71 void __iomem base; member 96 reg = readl(flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 101 writel(reg, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 104 reg = readl(flow->base + DP_GRAPH_WIND_CTRL) & 0x00FFFFFFL; in ipu_dp_set_global_alpha() 106 flow->base + DP_GRAPH_WIND_CTRL); in ipu_dp_set_global_alpha() 108 reg = readl(flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 109 writel(reg \| DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 111 reg = readl(flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() 112 writel(reg & ~DP_COM_CONF_GWAM, flow->base + DP_COM_CONF); in ipu_dp_set_global_alpha() [all …]
/linux-4.1.27/arch/arm/mach-shmobile/
D	intc.h	37 #define INTC_IRQ_PINS_MASK_16L(p, base) \ argument 38 { base + 0x40, base + 0x60, 8, /* INTMSK00A / INTMSKCLR00A / \ 41 { base + 0x44, base + 0x64, 8, / INTMSK10A / INTMSKCLR10A / \ 45 #define INTC_IRQ_PINS_MASK_16H(p, base) \ argument 46 { base + 0x48, base + 0x68, 8, / INTMSK20A / INTMSKCLR20A / \ 49 { base + 0x4c, base + 0x6c, 8, / INTMSK30A / INTMSKCLR30A / \ 53 #define INTC_IRQ_PINS_PRIO_16L(p, base) \ argument 54 { base + 0x10, 0, 32, 4, / INTPRI00A / \ 57 { base + 0x14, 0, 32, 4, / INTPRI10A */ \ 61 #define INTC_IRQ_PINS_PRIO_16H(p, base) \ argument [all …]
D	setup-rcar-gen2.c	56 void __iomem *base; in rcar_gen2_timer_init() local 108 base = ioremap(0xe6080000, PAGE_SIZE); in rcar_gen2_timer_init() 117 if ((ioread32(base + CNTCR) & 1) == 0 \|\| in rcar_gen2_timer_init() 118 ioread32(base + CNTFID0) != freq) { in rcar_gen2_timer_init() 120 iowrite32(freq, base + CNTFID0); in rcar_gen2_timer_init() 124 iowrite32(1, base + CNTCR); in rcar_gen2_timer_init() 127 iounmap(base); in rcar_gen2_timer_init() 138 u64 base, size; member 162 u64 base, size; in rcar_gen2_scan_mem() local 164 base = dt_mem_next_cell(dt_root_addr_cells, &reg); in rcar_gen2_scan_mem() [all …]
/linux-4.1.27/arch/powerpc/net/
D	bpf_jit.h	104 #define PPC_STD(r, base, i) EMIT(PPC_INST_STD \| ___PPC_RS(r) \| \ argument 105 ___PPC_RA(base) \| ((i) & 0xfffc)) 106 #define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU \| ___PPC_RS(r) \| \ argument 107 ___PPC_RA(base) \| ((i) & 0xfffc)) 108 #define PPC_STW(r, base, i) EMIT(PPC_INST_STW \| ___PPC_RS(r) \| \ argument 109 ___PPC_RA(base) \| ((i) & 0xfffc)) 110 #define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU \| ___PPC_RS(r) \| \ argument 111 ___PPC_RA(base) \| ((i) & 0xfffc)) 113 #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ \| ___PPC_RT(r) \| \ argument 114 ___PPC_RA(base) \| IMM_L(i)) [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/engine/disp/
D	g94.c	63 { GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, 64 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, 65 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, 66 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, 67 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, 118 &nv50_pior_dp_impl.base.base, 119 &g94_sor_dp_impl.base.base, 125 .base.base.handle = NV_ENGINE(DISP, 0x88), 126 .base.base.ofuncs = &(struct nvkm_ofuncs) { 132 .base.vblank = &nv50_disp_vblank_func, [all …]
D	gm204.c	35 { GM204_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, 36 { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, 37 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, 38 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, 39 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, 91 &gm204_sor_dp_impl.base.base, 97 .base.base.handle = NV_ENGINE(DISP, 0x07), 98 .base.base.ofuncs = &(struct nvkm_ofuncs) { 104 .base.vblank = &gf110_disp_vblank_func, 105 .base.outp = gm204_disp_outp_sclass, [all …]
D	gm107.c	34 { GM107_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, 35 { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, 36 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, 37 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, 38 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, 89 .base.base.handle = NV_ENGINE(DISP, 0x07), 90 .base.base.ofuncs = &(struct nvkm_ofuncs) { 96 .base.vblank = &gf110_disp_vblank_func, 97 .base.outp = gf110_disp_outp_sclass, 99 .mthd.base = &gf110_disp_base_mthd_chan, [all …]
D	gt215.c	34 { GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, 35 { GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, 36 { GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, 37 { GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, 38 { GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, 90 .base.base.handle = NV_ENGINE(DISP, 0x85), 91 .base.base.ofuncs = &(struct nvkm_ofuncs) { 97 .base.vblank = &nv50_disp_vblank_func, 98 .base.outp = g94_disp_outp_sclass, 100 .mthd.base = &g84_disp_base_mthd_chan, [all …]
D	gk110.c	34 { GK110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, 35 { GK110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, 36 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, 37 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, 38 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, 89 .base.base.handle = NV_ENGINE(DISP, 0x92), 90 .base.base.ofuncs = &(struct nvkm_ofuncs) { 96 .base.vblank = &gf110_disp_vblank_func, 97 .base.outp = gf110_disp_outp_sclass, 99 .mthd.base = &gf110_disp_base_mthd_chan, [all …]
D	gt200.c	79 { GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, 80 { GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, 81 { GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, 82 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, 83 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, 134 .base.base.handle = NV_ENGINE(DISP, 0x83), 135 .base.base.ofuncs = &(struct nvkm_ofuncs) { 141 .base.vblank = &nv50_disp_vblank_func, 142 .base.outp = nv50_disp_outp_sclass, 144 .mthd.base = &g84_disp_base_mthd_chan, [all …]
D	gf110.c	77 struct nv50_disp_base base = (void )parent->parent; in gf110_disp_dmac_object_attach() local 81 return nvkm_ramht_insert(base->ramht, chan->chid, name, data); in gf110_disp_dmac_object_attach() 87 struct nv50_disp_base base = (void )parent->parent; in gf110_disp_dmac_object_detach() local 88 nvkm_ramht_remove(base->ramht, cookie); in gf110_disp_dmac_object_detach() 96 int chid = dmac->base.chid; in gf110_disp_dmac_init() 99 ret = nv50_disp_chan_init(&dmac->base); in gf110_disp_dmac_init() 129 int chid = dmac->base.chid; in gf110_disp_dmac_fini() 145 return nv50_disp_chan_fini(&dmac->base, suspend); in gf110_disp_dmac_fini() 299 ret = nv50_disp_chan_init(&mast->base); in gf110_disp_core_init() 342 return nv50_disp_chan_fini(&mast->base, suspend); in gf110_disp_core_fini() [all …]
D	gk104.c	199 { GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, 200 { GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, 201 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, 202 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, 203 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, 254 .base.base.handle = NV_ENGINE(DISP, 0x91), 255 .base.base.ofuncs = &(struct nvkm_ofuncs) { 261 .base.vblank = &gf110_disp_vblank_func, 262 .base.outp = gf110_disp_outp_sclass, 264 .mthd.base = &gf110_disp_base_mthd_chan, [all …]
D	g84.c	203 { G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base }, 204 { G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base }, 205 { G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base }, 206 { G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base }, 207 { G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base }, 258 .base.base.handle = NV_ENGINE(DISP, 0x82), 259 .base.base.ofuncs = &(struct nvkm_ofuncs) { 265 .base.vblank = &nv50_disp_vblank_func, 266 .base.outp = nv50_disp_outp_sclass, 268 .mthd.base = &g84_disp_base_mthd_chan, [all …]
D	outpdp.c	34 nvkm_output_dp_train(struct nvkm_output base, u32 datarate, bool wait) in nvkm_output_dp_train() argument 36 struct nvkm_output_dp outp = (void )base; in nvkm_output_dp_train() 43 ret = nv_rdaux(outp->base.edid, DPCD_LC00_LINK_BW_SET, link, 2); in nvkm_output_dp_train() 58 ret = nv_rdaux(outp->base.edid, DPCD_LS02, stat, 3); in nvkm_output_dp_train() 84 outp->base.info.dpconf.link_bw; in nvkm_output_dp_train() 86 outp->base.info.dpconf.link_nr; in nvkm_output_dp_train() 107 struct nvkm_i2c_port port = outp->base.edid; in nvkm_output_dp_enable() 114 nvkm_output_dp_train(&outp->base, 0, true); in nvkm_output_dp_enable() 128 struct nvkm_i2c_port *port = outp->base.edid; in nvkm_output_dp_detect() 131 ret = nv_rdaux(outp->base.edid, DPCD_RC00_DPCD_REV, in nvkm_output_dp_detect() [all …]
/linux-4.1.27/drivers/pcmcia/
D	rsrc_nonstatic.c	52 u_long base, num; member 76 claim_region(struct pcmcia_socket s, resource_size_t base, in claim_region() argument 82 res = pcmcia_make_resource(base, size, type \| IORESOURCE_BUSY, name); in claim_region() 111 static int add_interval(struct resource_map map, u_long base, u_long num) in add_interval() argument 116 if ((p != map) && (p->base+p->num >= base)) { in add_interval() 117 p->num = max(num + base - p->base, p->num); in add_interval() 120 if ((p->next == map) \|\| (p->next->base > base+num-1)) in add_interval() 128 q->base = base; q->num = num; in add_interval() 135 static int sub_interval(struct resource_map *map, u_long base, u_long num) in sub_interval() argument 143 if ((q->base+q->num > base) && (base+num > q->base)) { in sub_interval() [all …]
/linux-4.1.27/arch/arm/mach-gemini/
D	gpio.c	48 static void _set_gpio_irqenable(void __iomem base, unsigned int index, in _set_gpio_irqenable() argument 53 reg = __raw_readl(base + GPIO_INT_EN); in _set_gpio_irqenable() 55 __raw_writel(reg, base + GPIO_INT_EN); in _set_gpio_irqenable() 61 void __iomem base = GPIO_BASE(gpio / 32); in gpio_ack_irq() local 63 __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR); in gpio_ack_irq() 69 void __iomem base = GPIO_BASE(gpio / 32); in gpio_mask_irq() local 71 _set_gpio_irqenable(base, gpio % 32, 0); in gpio_mask_irq() 77 void __iomem base = GPIO_BASE(gpio / 32); in gpio_unmask_irq() local 79 _set_gpio_irqenable(base, gpio % 32, 1); in gpio_unmask_irq() 86 void __iomem *base = GPIO_BASE(gpio / 32); in gpio_set_irq_type() local [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
D	nv4e.c	29 struct nvkm_i2c base; member 33 struct nvkm_i2c_port base; member 38 nv4e_i2c_drive_scl(struct nvkm_i2c_port base, int state) in nv4e_i2c_drive_scl() argument 40 struct nv4e_i2c_priv priv = (void )nvkm_i2c(base); in nv4e_i2c_drive_scl() 41 struct nv4e_i2c_port port = (void )base; in nv4e_i2c_drive_scl() 46 nv4e_i2c_drive_sda(struct nvkm_i2c_port base, int state) in nv4e_i2c_drive_sda() argument 48 struct nv4e_i2c_priv priv = (void )nvkm_i2c(base); in nv4e_i2c_drive_sda() 49 struct nv4e_i2c_port port = (void )base; in nv4e_i2c_drive_sda() 54 nv4e_i2c_sense_scl(struct nvkm_i2c_port base) in nv4e_i2c_sense_scl() argument 56 struct nv4e_i2c_priv priv = (void *)nvkm_i2c(base); in nv4e_i2c_sense_scl() [all …]
D	nv04.c	29 struct nvkm_i2c base; member 33 struct nvkm_i2c_port base; member 39 nv04_i2c_drive_scl(struct nvkm_i2c_port base, int state) in nv04_i2c_drive_scl() argument 41 struct nv04_i2c_priv priv = (void )nvkm_i2c(base); in nv04_i2c_drive_scl() 42 struct nv04_i2c_port port = (void )base; in nv04_i2c_drive_scl() 50 nv04_i2c_drive_sda(struct nvkm_i2c_port base, int state) in nv04_i2c_drive_sda() argument 52 struct nv04_i2c_priv priv = (void )nvkm_i2c(base); in nv04_i2c_drive_sda() 53 struct nv04_i2c_port port = (void )base; in nv04_i2c_drive_sda() 61 nv04_i2c_sense_scl(struct nvkm_i2c_port base) in nv04_i2c_sense_scl() argument 63 struct nv04_i2c_priv priv = (void *)nvkm_i2c(base); in nv04_i2c_sense_scl() [all …]
D	nv50.c	27 nv50_i2c_drive_scl(struct nvkm_i2c_port base, int state) in nv50_i2c_drive_scl() argument 29 struct nv50_i2c_priv priv = (void )nvkm_i2c(base); in nv50_i2c_drive_scl() 30 struct nv50_i2c_port port = (void )base; in nv50_i2c_drive_scl() 37 nv50_i2c_drive_sda(struct nvkm_i2c_port base, int state) in nv50_i2c_drive_sda() argument 39 struct nv50_i2c_priv priv = (void )nvkm_i2c(base); in nv50_i2c_drive_sda() 40 struct nv50_i2c_port port = (void )base; in nv50_i2c_drive_sda() 47 nv50_i2c_sense_scl(struct nvkm_i2c_port base) in nv50_i2c_sense_scl() argument 49 struct nv50_i2c_priv priv = (void )nvkm_i2c(base); in nv50_i2c_sense_scl() 50 struct nv50_i2c_port port = (void )base; in nv50_i2c_sense_scl() 55 nv50_i2c_sense_sda(struct nvkm_i2c_port base) in nv50_i2c_sense_sda() argument [all …]
/linux-4.1.27/sound/soc/fsl/
D	imx-ssi.c	67 sccr = readl(ssi->base + SSI_STCCR); in imx_ssi_set_dai_tdm_slot() 70 writel(sccr, ssi->base + SSI_STCCR); in imx_ssi_set_dai_tdm_slot() 72 sccr = readl(ssi->base + SSI_SRCCR); in imx_ssi_set_dai_tdm_slot() 75 writel(sccr, ssi->base + SSI_SRCCR); in imx_ssi_set_dai_tdm_slot() 77 writel(~tx_mask, ssi->base + SSI_STMSK); in imx_ssi_set_dai_tdm_slot() 78 writel(~rx_mask, ssi->base + SSI_SRMSK); in imx_ssi_set_dai_tdm_slot() 92 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN \| SSI_SCR_NET); in imx_ssi_set_dai_fmt() 153 writel(strcr, ssi->base + SSI_STCR); in imx_ssi_set_dai_fmt() 154 writel(strcr, ssi->base + SSI_SRCR); in imx_ssi_set_dai_fmt() 155 writel(scr, ssi->base + SSI_SCR); in imx_ssi_set_dai_fmt() [all …]
/linux-4.1.27/drivers/watchdog/
D	omap_wdt.c	57 void __iomem base; / physical / member 66 void __iomem base = wdev->base; in omap_wdt_reload() local 69 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload() 73 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR)); in omap_wdt_reload() 76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08) in omap_wdt_reload() 83 void __iomem *base = wdev->base; in omap_wdt_enable() local 86 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR); in omap_wdt_enable() 87 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable() 90 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR); in omap_wdt_enable() 91 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10) in omap_wdt_enable() [all …]
D	nv_tco.h	`34 #define TCO_RLD(base) ((base) + 0x00) /* TCO Timer Reload and Current Value / argument 35 #define TCO_TMR(base) ((base) + 0x01) / TCO Timer Initial Value / argument 37 #define TCO_STS(base) ((base) + 0x04) / TCO Status Register / argument 53 #define TCO_CNT(base) ((base) + 0x08) / TCO Control Register */ argument 63 #define MCP51_SMI_EN(base) ((base) - 0x40 + 0x04) argument`
D	davinci_wdt.c	66 void __iomem *base; member 81 iowrite32(0, davinci_wdt->base + TCR); in davinci_wdt_start() 83 iowrite32(0, davinci_wdt->base + TGCR); in davinci_wdt_start() 85 iowrite32(tgcr, davinci_wdt->base + TGCR); in davinci_wdt_start() 87 iowrite32(0, davinci_wdt->base + TIM12); in davinci_wdt_start() 88 iowrite32(0, davinci_wdt->base + TIM34); in davinci_wdt_start() 91 iowrite32(timer_margin, davinci_wdt->base + PRD12); in davinci_wdt_start() 93 iowrite32(timer_margin, davinci_wdt->base + PRD34); in davinci_wdt_start() 95 iowrite32(ENAMODE12_PERIODIC, davinci_wdt->base + TCR); in davinci_wdt_start() 101 iowrite32(WDKEY_SEQ0 \| WDEN, davinci_wdt->base + WDTCR); in davinci_wdt_start() [all …]
/linux-4.1.27/arch/x86/kernel/cpu/mtrr/
D	if.c	38 mtrr_file_add(unsigned long base, unsigned long size, in mtrr_file_add() argument 52 if ((base & (PAGE_SIZE - 1)) \|\| (size & (PAGE_SIZE - 1))) in mtrr_file_add() 54 base >>= PAGE_SHIFT; in mtrr_file_add() 57 reg = mtrr_add_page(base, size, type, true); in mtrr_file_add() 64 mtrr_file_del(unsigned long base, unsigned long size, in mtrr_file_del() argument 71 if ((base & (PAGE_SIZE - 1)) \|\| (size & (PAGE_SIZE - 1))) in mtrr_file_del() 73 base >>= PAGE_SHIFT; in mtrr_file_del() 76 reg = mtrr_del_page(-1, base, size); in mtrr_file_del() 98 unsigned long long base, size; in mtrr_write() local 137 base = simple_strtoull(line + 5, &ptr, 0); in mtrr_write() [all …]
D	main.c	73 static void set_mtrr(unsigned int reg, unsigned long base, 223 set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type) in set_mtrr() argument 226 .smp_base = base, in set_mtrr() 234 static void set_mtrr_from_inactive_cpu(unsigned int reg, unsigned long base, in set_mtrr_from_inactive_cpu() argument 238 .smp_base = base, in set_mtrr_from_inactive_cpu() 282 int mtrr_add_page(unsigned long base, unsigned long size, in mtrr_add_page() argument 292 error = mtrr_if->validate_add_page(base, size, type); in mtrr_add_page() 312 if ((base \| (base + size - 1)) >> in mtrr_add_page() 328 if (!lsize \|\| base > lbase + lsize - 1 \|\| in mtrr_add_page() 329 base + size - 1 < lbase) in mtrr_add_page() [all …]
/linux-4.1.27/drivers/spi/
D	spi-sirf.c	145 void __iomem *base; member 183 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); in spi_sirfsoc_rx_word_u8() 203 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); in spi_sirfsoc_tx_word_u8() 212 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); in spi_sirfsoc_rx_word_u16() 232 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); in spi_sirfsoc_tx_word_u16() 241 data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA); in spi_sirfsoc_rx_word_u32() 262 writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA); in spi_sirfsoc_tx_word_u32() 269 u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS); in spi_sirfsoc_irq() 272 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN); in spi_sirfsoc_irq() 274 sspi->base + SIRFSOC_SPI_INT_STATUS); in spi_sirfsoc_irq() [all …]
D	spi-altera.c	52 void __iomem *base; member 77 hw->base + ALTERA_SPI_SLAVE_SEL); in altera_spi_chipsel() 79 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 84 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 85 writel(0, hw->base + ALTERA_SPI_SLAVE_SEL); in altera_spi_chipsel() 92 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 97 hw->base + ALTERA_SPI_SLAVE_SEL); in altera_spi_chipsel() 99 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_chipsel() 132 writel(hw->imr, hw->base + ALTERA_SPI_CONTROL); in altera_spi_txrx() 135 writel(hw_txbyte(hw, 0), hw->base + ALTERA_SPI_TXDATA); in altera_spi_txrx() [all …]
/linux-4.1.27/arch/mips/include/asm/netlogic/
D	haldefs.h	46 nlm_read_reg(uint64_t base, uint32_t reg) in nlm_read_reg() argument 48 volatile uint32_t addr = (volatile uint32_t )(long)base + reg; in nlm_read_reg() 54 nlm_write_reg(uint64_t base, uint32_t reg, uint32_t val) in nlm_write_reg() argument 56 volatile uint32_t addr = (volatile uint32_t )(long)base + reg; in nlm_write_reg() 71 nlm_read_reg64(uint64_t base, uint32_t reg) in nlm_read_reg64() argument 73 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_read_reg64() 98 nlm_write_reg64(uint64_t base, uint32_t reg, uint64_t val) in nlm_write_reg64() argument 100 uint64_t addr = base + (reg >> 1) * sizeof(uint64_t); in nlm_write_reg64() 129 nlm_read_reg_xkphys(uint64_t base, uint32_t reg) in nlm_read_reg_xkphys() argument 131 return nlm_read_reg(base, reg); in nlm_read_reg_xkphys() [all …]
/linux-4.1.27/arch/mips/pci/
D	pci-ar724x.c	75 void __iomem base; in ar724x_pci_local_write() local 84 base = apc->crp_base; in ar724x_pci_local_write() 85 data = __raw_readl(base + (where & ~3)); in ar724x_pci_local_write() 105 __raw_writel(data, base + (where & ~3)); in ar724x_pci_local_write() 107 __raw_readl(base + (where & ~3)); in ar724x_pci_local_write() 116 void __iomem base; in ar724x_pci_read() local 126 base = apc->devcfg_base; in ar724x_pci_read() 127 data = __raw_readl(base + (where & ~3)); in ar724x_pci_read() 163 void __iomem *base; in ar724x_pci_write() local 195 base = apc->devcfg_base; in ar724x_pci_write() [all …]
D	pci-ar71xx.c	112 void __iomem base = apc->cfg_base; in ar71xx_pci_check_error() local 116 pci_err = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR) & 3; in ar71xx_pci_check_error() 121 addr = __raw_readl(base + AR71XX_PCI_REG_PCI_ERR_ADDR); in ar71xx_pci_check_error() 127 __raw_writel(pci_err, base + AR71XX_PCI_REG_PCI_ERR); in ar71xx_pci_check_error() 130 ahb_err = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR) & 1; in ar71xx_pci_check_error() 135 addr = __raw_readl(base + AR71XX_PCI_REG_AHB_ERR_ADDR); in ar71xx_pci_check_error() 141 __raw_writel(ahb_err, base + AR71XX_PCI_REG_AHB_ERR); in ar71xx_pci_check_error() 150 void __iomem base = apc->cfg_base; in ar71xx_pci_local_write() local 158 __raw_writel(ad_cbe, base + AR71XX_PCI_REG_CRP_AD_CBE); in ar71xx_pci_local_write() 159 __raw_writel(value, base + AR71XX_PCI_REG_CRP_WRDATA); in ar71xx_pci_local_write() [all …]
/linux-4.1.27/arch/mips/ath25/
D	early_printk.c	17 static inline void prom_uart_wr(void __iomem base, unsigned reg, in prom_uart_wr() argument 20 __raw_writel(ch, base + 4 reg); in prom_uart_wr() 23 static inline unsigned char prom_uart_rr(void __iomem base, unsigned reg) in prom_uart_rr() argument 25 return __raw_readl(base + 4 reg); in prom_uart_rr() 30 static void __iomem base; in prom_putchar() local 32 if (unlikely(base == NULL)) { in prom_putchar() 34 base = (void __iomem )(KSEG1ADDR(AR2315_UART0_BASE)); in prom_putchar() 36 base = (void __iomem *)(KSEG1ADDR(AR5312_UART0_BASE)); in prom_putchar() 39 while ((prom_uart_rr(base, UART_LSR) & UART_LSR_THRE) == 0) in prom_putchar() 41 prom_uart_wr(base, UART_TX, ch); in prom_putchar() [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
D	nv04.c	42 ret = nvkm_fb_init(&priv->base); in nv04_fb_init() 68 priv->base.tile.regions = impl->tile.regions; in nv04_fb_ctor() 69 priv->base.tile.init = impl->tile.init; in nv04_fb_ctor() 70 priv->base.tile.comp = impl->tile.comp; in nv04_fb_ctor() 71 priv->base.tile.fini = impl->tile.fini; in nv04_fb_ctor() 72 priv->base.tile.prog = impl->tile.prog; in nv04_fb_ctor() 78 .base.base.handle = NV_SUBDEV(FB, 0x04), 79 .base.base.ofuncs = &(struct nvkm_ofuncs) { 85 .base.memtype = nv04_fb_memtype_valid, 86 .base.ram = &nv04_ram_oclass, [all …]
D	mcp89.c	`28 .base.base.handle = NV_SUBDEV(FB, 0xaf), 29 .base.base.ofuncs = &(struct nvkm_ofuncs) { 35 .base.memtype = nv50_fb_memtype_valid, 36 .base.ram = &mcp77_ram_oclass, 38 }.base.base;`
D	mcp77.c	`28 .base.base.handle = NV_SUBDEV(FB, 0xaa), 29 .base.base.ofuncs = &(struct nvkm_ofuncs) { 35 .base.memtype = nv50_fb_memtype_valid, 36 .base.ram = &mcp77_ram_oclass, 38 }.base.base;`
D	gt215.c	`28 .base.base.handle = NV_SUBDEV(FB, 0xa3), 29 .base.base.ofuncs = &(struct nvkm_ofuncs) { 35 .base.memtype = nv50_fb_memtype_valid, 36 .base.ram = &gt215_ram_oclass, 38 }.base.base;`
D	g84.c	`28 .base.base.handle = NV_SUBDEV(FB, 0x84), 29 .base.base.ofuncs = &(struct nvkm_ofuncs) { 35 .base.memtype = nv50_fb_memtype_valid, 36 .base.ram = &nv50_ram_oclass, 38 }.base.base;`
D	rammcp77.c	27 struct nvkm_ram base; member 47 priv->base.type = NV_MEM_TYPE_STOLEN; in mcp77_ram_ctor() 48 priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12; in mcp77_ram_ctor() 49 priv->base.size = (u64)nv_rd32(pfb, 0x100e14) << 12; in mcp77_ram_ctor() 52 priv->poller_base = priv->base.size - rsvd_tail; in mcp77_ram_ctor() 55 (priv->base.size - (rsvd_head + rsvd_tail)) >> 12, in mcp77_ram_ctor() 60 priv->base.get = nv50_ram_get; in mcp77_ram_ctor() 61 priv->base.put = nv50_ram_put; in mcp77_ram_ctor() 73 ret = nvkm_ram_init(&priv->base); in mcp77_ram_init() 77 dniso = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1; in mcp77_ram_init() [all …]
/linux-4.1.27/arch/arm/mach-davinci/
D	time.c	96 void __iomem base; member 136 __raw_writel(__raw_readl(t->base + t->tim_off) + t->period, in timer32_config() 137 t->base + dtip[event_timer].cmp_off); in timer32_config() 139 tcr = __raw_readl(t->base + TCR); in timer32_config() 143 __raw_writel(tcr, t->base + TCR); in timer32_config() 146 __raw_writel(0, t->base + t->tim_off); in timer32_config() 147 __raw_writel(t->period, t->base + t->prd_off); in timer32_config() 155 __raw_writel(tcr, t->base + TCR); in timer32_config() 162 return __raw_readl(t->base + t->tim_off); in timer32_read() 203 void __iomem base[2]; in timer_init() local [all …]
/linux-4.1.27/drivers/gpu/drm/msm/edp/
D	edp_phy.c	20 void __iomem *base; member 29 status = edp_read(phy->base + in msm_edp_phy_ready() 49 edp_write(phy->base + REG_EDP_PHY_CTRL, in msm_edp_phy_ctrl() 54 edp_write(phy->base + REG_EDP_PHY_CTRL, 0x000); in msm_edp_phy_ctrl() 55 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0x3f); in msm_edp_phy_ctrl() 56 edp_write(phy->base + REG_EDP_PHY_GLB_CFG, 0x1); in msm_edp_phy_ctrl() 58 edp_write(phy->base + REG_EDP_PHY_GLB_PD_CTL, 0xc0); in msm_edp_phy_ctrl() 65 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG0, 0x3); in msm_edp_phy_vm_pe_init() 66 edp_write(phy->base + REG_EDP_PHY_GLB_VM_CFG1, 0x64); in msm_edp_phy_vm_pe_init() 67 edp_write(phy->base + REG_EDP_PHY_GLB_MISC9, 0x6c); in msm_edp_phy_vm_pe_init() [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/
D	nv04_fence.c	30 struct nouveau_fence_chan base; member 34 struct nouveau_fence_priv base; member 44 OUT_RING (chan, fence->base.seqno); in nv04_fence_emit() 68 nouveau_fence_context_del(&fctx->base); in nv04_fence_context_del() 70 nouveau_fence_context_free(&fctx->base); in nv04_fence_context_del() 78 nouveau_fence_context_new(chan, &fctx->base); in nv04_fence_context_new() 79 fctx->base.emit = nv04_fence_emit; in nv04_fence_context_new() 80 fctx->base.sync = nv04_fence_sync; in nv04_fence_context_new() 81 fctx->base.read = nv04_fence_read; in nv04_fence_context_new() 105 priv->base.dtor = nv04_fence_destroy; in nv04_fence_create() [all …]
D	nv84_fence.c	85 return fctx->base.emit32(chan, addr, fence->base.seqno); in nv84_fence_emit() 100 return fctx->base.sync32(chan, addr, fence->base.seqno); in nv84_fence_sync() 123 nouveau_bo_wr32(priv->bo, chan->chid * 16 / 4, fctx->base.sequence); in nv84_fence_context_del() 126 nouveau_fence_context_del(&fctx->base); in nv84_fence_context_del() 128 nouveau_fence_context_free(&fctx->base); in nv84_fence_context_del() 134 struct nouveau_cli cli = (void )nvif_client(&chan->device->base); in nv84_fence_context_new() 143 nouveau_fence_context_new(chan, &fctx->base); in nv84_fence_context_new() 144 fctx->base.emit = nv84_fence_emit; in nv84_fence_context_new() 145 fctx->base.sync = nv84_fence_sync; in nv84_fence_context_new() 146 fctx->base.read = nv84_fence_read; in nv84_fence_context_new() [all …]
D	nv10_fence.c	36 OUT_RING (chan, fence->base.seqno); in nv10_fence_emit() 61 nouveau_fence_context_del(&fctx->base); in nv10_fence_context_del() 66 nouveau_fence_context_free(&fctx->base); in nv10_fence_context_del() 78 nouveau_fence_context_new(chan, &fctx->base); in nv10_fence_context_new() 79 fctx->base.emit = nv10_fence_emit; in nv10_fence_context_new() 80 fctx->base.read = nv10_fence_read; in nv10_fence_context_new() 81 fctx->base.sync = nv10_fence_sync; in nv10_fence_context_new() 106 priv->base.dtor = nv10_fence_destroy; in nv10_fence_create() 107 priv->base.context_new = nv10_fence_context_new; in nv10_fence_create() 108 priv->base.context_del = nv10_fence_context_del; in nv10_fence_create() [all …]
/linux-4.1.27/drivers/crypto/ux500/cryp/
D	cryp.c	38 peripheralid2 = readl_relaxed(&device_data->base->periphId2); in cryp_check() 45 readl_relaxed(&device_data->base->periphId0)) in cryp_check() 47 readl_relaxed(&device_data->base->periphId1)) in cryp_check() 49 readl_relaxed(&device_data->base->periphId3)) in cryp_check() 51 readl_relaxed(&device_data->base->pcellId0)) in cryp_check() 53 readl_relaxed(&device_data->base->pcellId1)) in cryp_check() 55 readl_relaxed(&device_data->base->pcellId2)) in cryp_check() 57 readl_relaxed(&device_data->base->pcellId3))) { in cryp_check() 72 CRYP_PUT_BITS(&device_data->base->cr, in cryp_activity() 93 CRYP_SET_BITS(&device_data->base->cr, CRYP_CR_FFLUSH_MASK); in cryp_flush_inoutfifo() [all …]
/linux-4.1.27/drivers/hwtracing/coresight/
D	coresight-etb10.c	80 void __iomem *base; member 103 depth = readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); in etb_get_buffer_depth() 114 CS_UNLOCK(drvdata->base); in etb_enable_hw() 118 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); in etb_enable_hw() 121 writel_relaxed(0x0, drvdata->base + ETB_RWD_REG); in etb_enable_hw() 124 writel_relaxed(0x0, drvdata->base + ETB_RAM_WRITE_POINTER); in etb_enable_hw() 126 writel_relaxed(0x0, drvdata->base + ETB_RAM_READ_POINTER); in etb_enable_hw() 128 writel_relaxed(drvdata->trigger_cntr, drvdata->base + ETB_TRG); in etb_enable_hw() 130 drvdata->base + ETB_FFCR); in etb_enable_hw() 132 writel_relaxed(ETB_CTL_CAPT_EN, drvdata->base + ETB_CTL_REG); in etb_enable_hw() [all …]
D	coresight-tmc.c	119 void __iomem *base; member 139 if (coresight_timeout(drvdata->base, in tmc_wait_for_ready() 151 ffcr = readl_relaxed(drvdata->base + TMC_FFCR); in tmc_flush_and_stop() 153 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); in tmc_flush_and_stop() 155 writel_relaxed(ffcr, drvdata->base + TMC_FFCR); in tmc_flush_and_stop() 157 if (coresight_timeout(drvdata->base, in tmc_flush_and_stop() 169 writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL); in tmc_enable_hw() 174 writel_relaxed(0x0, drvdata->base + TMC_CTL); in tmc_disable_hw() 182 CS_UNLOCK(drvdata->base); in tmc_etb_enable_hw() 184 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); in tmc_etb_enable_hw() [all …]
D	coresight-funnel.c	43 void __iomem *base; member 54 CS_UNLOCK(drvdata->base); in funnel_enable_hw() 56 functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); in funnel_enable_hw() 60 writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); in funnel_enable_hw() 61 writel_relaxed(drvdata->priority, drvdata->base + FUNNEL_PRICTL); in funnel_enable_hw() 63 CS_LOCK(drvdata->base); in funnel_enable_hw() 86 CS_UNLOCK(drvdata->base); in funnel_disable_hw() 88 functl = readl_relaxed(drvdata->base + FUNNEL_FUNCTL); in funnel_disable_hw() 90 writel_relaxed(functl, drvdata->base + FUNNEL_FUNCTL); in funnel_disable_hw() 92 CS_LOCK(drvdata->base); in funnel_disable_hw() [all …]
/linux-4.1.27/drivers/pnp/pnpbios/
D	rsparser.c	252 resource_size_t base, len; in pnpbios_parse_fixed_mem32_option() local 255 base = (p[7] << 24) \| (p[6] << 16) \| (p[5] << 8) \| p[4]; in pnpbios_parse_fixed_mem32_option() 258 pnp_register_mem_resource(dev, option_flags, base, base, 0, len, flags); in pnpbios_parse_fixed_mem32_option() 307 resource_size_t base, len; in pnpbios_parse_fixed_port_option() local 309 base = (p[2] << 8) \| p[1]; in pnpbios_parse_fixed_port_option() 311 pnp_register_port_resource(dev, option_flags, base, base, 0, len, in pnpbios_parse_fixed_port_option() 503 unsigned long base; in pnpbios_encode_mem() local 507 base = res->start; in pnpbios_encode_mem() 510 base = 0; in pnpbios_encode_mem() 514 p[4] = (base >> 8) & 0xff; in pnpbios_encode_mem() [all …]
/linux-4.1.27/net/ipv4/
D	inetpeer.c	212 struct inet_peer_base base) in lookup_rcu() argument 214 struct inet_peer u = rcu_dereference(base->root); in lookup_rcu() 238 #define lookup_rightempty(start, base) \ argument 244 for (u = rcu_deref_locked(v, base); \ 248 u = rcu_deref_locked(v, base); \ 259 struct inet_peer_base base) in peer_avl_rebalance() argument 267 node = rcu_deref_locked(nodep, base); in peer_avl_rebalance() 268 l = rcu_deref_locked(node->avl_left, base); in peer_avl_rebalance() 269 r = rcu_deref_locked(node->avl_right, base); in peer_avl_rebalance() 275 ll = rcu_deref_locked(l->avl_left, base); in peer_avl_rebalance() [all …]
/linux-4.1.27/arch/c6x/platforms/
D	dscr.c	107 void __iomem base; member 135 void __iomem reg_addr = dscr.base + reg; in dscr_write_locked1() 136 void __iomem *lock_addr = dscr.base + lock; in dscr_write_locked1() 165 soc_writel(key0, dscr.base + lock0); in dscr_write_locked2() 166 soc_writel(key1, dscr.base + lock1); in dscr_write_locked2() 167 soc_writel(val, dscr.base + reg); in dscr_write_locked2() 168 soc_writel(0, dscr.base + lock0); in dscr_write_locked2() 169 soc_writel(0, dscr.base + lock1); in dscr_write_locked2() 183 soc_writel(val, dscr.base + reg); in dscr_write() 199 if (!dscr.base) in dscr_set_devstate() [all …]
/linux-4.1.27/net/sunrpc/
D	socklib.c	72 ssize_t xdr_partial_copy_from_skb(struct xdr_buf xdr, unsigned int base, struct xdr_skb_reader de… in xdr_partial_copy_from_skb() argument 80 if (base < len) { in xdr_partial_copy_from_skb() 81 len -= base; in xdr_partial_copy_from_skb() 82 ret = copy_actor(desc, (char *)xdr->head[0].iov_base + base, len); in xdr_partial_copy_from_skb() 86 base = 0; in xdr_partial_copy_from_skb() 88 base -= len; in xdr_partial_copy_from_skb() 92 if (unlikely(base >= pglen)) { in xdr_partial_copy_from_skb() 93 base -= pglen; in xdr_partial_copy_from_skb() 96 if (base \|\| xdr->page_base) { in xdr_partial_copy_from_skb() 97 pglen -= base; in xdr_partial_copy_from_skb() [all …]
/linux-4.1.27/arch/mips/ath79/
D	gpio.c	34 void __iomem base = ath79_gpio_base; in __ath79_gpio_set_value() local 37 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_SET); in __ath79_gpio_set_value() 39 __raw_writel(1 << gpio, base + AR71XX_GPIO_REG_CLEAR); in __ath79_gpio_set_value() 61 void __iomem base = ath79_gpio_base; in ath79_gpio_direction_input() local 66 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) & ~(1 << offset), in ath79_gpio_direction_input() 67 base + AR71XX_GPIO_REG_OE); in ath79_gpio_direction_input() 77 void __iomem *base = ath79_gpio_base; in ath79_gpio_direction_output() local 83 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_SET); in ath79_gpio_direction_output() 85 __raw_writel(1 << offset, base + AR71XX_GPIO_REG_CLEAR); in ath79_gpio_direction_output() 87 __raw_writel(__raw_readl(base + AR71XX_GPIO_REG_OE) \| (1 << offset), in ath79_gpio_direction_output() [all …]
D	early_printk.c	38 void __iomem base = (void __iomem )(KSEG1ADDR(AR71XX_UART_BASE)); in prom_putchar_ar71xx() local 40 prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); in prom_putchar_ar71xx() 41 __raw_writel(ch, base + UART_TX * 4); in prom_putchar_ar71xx() 42 prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY); in prom_putchar_ar71xx() 47 void __iomem base = (void __iomem )(KSEG1ADDR(AR933X_UART_BASE)); in prom_putchar_ar933x() local 49 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, in prom_putchar_ar933x() 51 __raw_writel(AR933X_UART_DATA_TX_CSR \| ch, base + AR933X_UART_DATA_REG); in prom_putchar_ar933x() 52 prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR, in prom_putchar_ar933x() 63 void __iomem base; in prom_putchar_init() local 66 base = (void __iomem )(KSEG1ADDR(AR71XX_RESET_BASE)); in prom_putchar_init() [all …]
/linux-4.1.27/drivers/rtc/
D	rtc-s3c.c	39 void __iomem *base; member 129 tmp = readb(info->base + S3C2410_RTCALM) & ~S3C2410_RTCALM_ALMEN; in s3c_rtc_setaie() 134 writeb(tmp, info->base + S3C2410_RTCALM); in s3c_rtc_setaie() 171 rtc_tm->tm_min = readb(info->base + S3C2410_RTCMIN); in s3c_rtc_gettime() 172 rtc_tm->tm_hour = readb(info->base + S3C2410_RTCHOUR); in s3c_rtc_gettime() 173 rtc_tm->tm_mday = readb(info->base + S3C2410_RTCDATE); in s3c_rtc_gettime() 174 rtc_tm->tm_mon = readb(info->base + S3C2410_RTCMON); in s3c_rtc_gettime() 175 rtc_tm->tm_year = readb(info->base + S3C2410_RTCYEAR); in s3c_rtc_gettime() 176 rtc_tm->tm_sec = readb(info->base + S3C2410_RTCSEC); in s3c_rtc_gettime() 226 writeb(bin2bcd(tm->tm_sec), info->base + S3C2410_RTCSEC); in s3c_rtc_settime() [all …]
D	rtc-pl031.c	91 void __iomem *base; member 101 writel(RTC_BIT_AI, ldata->base + RTC_ICR); in pl031_alarm_irq_enable() 103 imsc = readl(ldata->base + RTC_IMSC); in pl031_alarm_irq_enable() 106 writel(imsc \| RTC_BIT_AI, ldata->base + RTC_IMSC); in pl031_alarm_irq_enable() 108 writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC); in pl031_alarm_irq_enable() 173 pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR), in pl031_stv2_read_time() 174 readl(ldata->base + RTC_YDR), tm); in pl031_stv2_read_time() 188 writel(bcd_year, ldata->base + RTC_YLR); in pl031_stv2_set_time() 189 writel(time, ldata->base + RTC_LR); in pl031_stv2_set_time() 200 ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR), in pl031_stv2_read_alarm() [all …]
D	rtc-sun6i.c	114 void __iomem *base; member 124 val = readl(chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_alarmirq() 128 writel(val, chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_alarmirq() 150 chip->base + SUN6I_ALRM_IRQ_STA); in sun6i_rtc_setaie() 153 writel(alrm_val, chip->base + SUN6I_ALRM_EN); in sun6i_rtc_setaie() 154 writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN); in sun6i_rtc_setaie() 155 writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG); in sun6i_rtc_setaie() 167 date = readl(chip->base + SUN6I_RTC_YMD); in sun6i_rtc_gettime() 168 time = readl(chip->base + SUN6I_RTC_HMS); in sun6i_rtc_gettime() 169 } while ((date != readl(chip->base + SUN6I_RTC_YMD)) \|\| in sun6i_rtc_gettime() [all …]
/linux-4.1.27/arch/arm/plat-orion/include/plat/
D	pcie.h	16 u32 orion_pcie_dev_id(void __iomem base); 17 u32 orion_pcie_rev(void __iomem base); 18 int orion_pcie_link_up(void __iomem base); 19 int orion_pcie_x4_mode(void __iomem base); 20 int orion_pcie_get_local_bus_nr(void __iomem base); 21 void orion_pcie_set_local_bus_nr(void __iomem base, int nr); 22 void orion_pcie_reset(void __iomem base); 23 void orion_pcie_setup(void __iomem base); 24 int orion_pcie_rd_conf(void __iomem base, struct pci_bus bus, 26 int orion_pcie_rd_conf_tlp(void __iomem base, struct pci_bus bus, [all …]
/linux-4.1.27/arch/mips/include/asm/netlogic/xlr/
D	pic.h	223 nlm_pic_enable_irt(uint64_t base, int irt) in nlm_pic_enable_irt() argument 227 reg = nlm_read_reg(base, PIC_IRT_1(irt)); in nlm_pic_enable_irt() 228 nlm_write_reg(base, PIC_IRT_1(irt), reg \| (1u << 31)); in nlm_pic_enable_irt() 232 nlm_pic_disable_irt(uint64_t base, int irt) in nlm_pic_disable_irt() argument 236 reg = nlm_read_reg(base, PIC_IRT_1(irt)); in nlm_pic_disable_irt() 237 nlm_write_reg(base, PIC_IRT_1(irt), reg & ~(1u << 31)); in nlm_pic_disable_irt() 241 nlm_pic_send_ipi(uint64_t base, int hwt, int irq, int nmi) in nlm_pic_send_ipi() argument 247 nlm_write_reg(base, PIC_IPI, in nlm_pic_send_ipi() 252 nlm_pic_ack(uint64_t base, int irt) in nlm_pic_ack() argument 254 nlm_write_reg(base, PIC_INT_ACK, 1u << irt); in nlm_pic_ack() [all …]
/linux-4.1.27/net/netfilter/
D	nf_conntrack_h323_asn1.c	114 static int decode_nul(bitstr_t bs, const struct field_t f, char base, int level); 115 static int decode_bool(bitstr_t bs, const struct field_t f, char base, int level); 116 static int decode_oid(bitstr_t bs, const struct field_t f, char base, int level); 117 static int decode_int(bitstr_t bs, const struct field_t f, char base, int level); 118 static int decode_enum(bitstr_t bs, const struct field_t f, char base, int level); 119 static int decode_bitstr(bitstr_t bs, const struct field_t f, char base, int level); 120 static int decode_numstr(bitstr_t bs, const struct field_t f, char base, int level); 121 static int decode_octstr(bitstr_t bs, const struct field_t f, char base, int level); 122 static int decode_bmpstr(bitstr_t bs, const struct field_t f, char base, int level); 123 static int decode_seq(bitstr_t bs, const struct field_t f, char base, int level); [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
D	nv50.c	29 struct nvkm_instmem base; member 35 struct nvkm_instobj base; member 49 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; in nv50_instobj_rd32() local 54 if (unlikely(priv->addr != base)) { in nv50_instobj_rd32() 55 nv_wr32(priv, 0x001700, base >> 16); in nv50_instobj_rd32() 56 priv->addr = base; in nv50_instobj_rd32() 69 u64 base = (node->mem->offset + offset) & 0xffffff00000ULL; in nv50_instobj_wr32() local 73 if (unlikely(priv->addr != base)) { in nv50_instobj_wr32() 74 nv_wr32(priv, 0x001700, base >> 16); in nv50_instobj_wr32() 75 priv->addr = base; in nv50_instobj_wr32() [all …]
D	nv40.c	79 if (device->chipset == 0x40) priv->base.reserved = 0x6aa0 * vs; in nv40_instmem_ctor() 80 else if (device->chipset < 0x43) priv->base.reserved = 0x4f00 * vs; in nv40_instmem_ctor() 81 else if (nv44_gr_class(priv)) priv->base.reserved = 0x4980 * vs; in nv40_instmem_ctor() 82 else priv->base.reserved = 0x4a40 * vs; in nv40_instmem_ctor() 83 priv->base.reserved += 16 * 1024; in nv40_instmem_ctor() 84 priv->base.reserved = 32; / per-channel / in nv40_instmem_ctor() 85 priv->base.reserved += 512 1024; /* pci(e)gart table / in nv40_instmem_ctor() 86 priv->base.reserved += 512 1024; /* object storage */ in nv40_instmem_ctor() 88 priv->base.reserved = round_up(priv->base.reserved, 4096); in nv40_instmem_ctor() 90 ret = nvkm_mm_init(&priv->heap, 0, priv->base.reserved, 1); in nv40_instmem_ctor() [all …]
/linux-4.1.27/drivers/usb/host/
D	xhci-mvebu.c	21 static void xhci_mvebu_mbus_config(void __iomem base, in xhci_mvebu_mbus_config() argument 28 writel(0, base + USB3_WIN_CTRL(win)); in xhci_mvebu_mbus_config() 29 writel(0, base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config() 38 base + USB3_WIN_CTRL(win)); in xhci_mvebu_mbus_config() 40 writel((cs->base & 0xffff0000), base + USB3_WIN_BASE(win)); in xhci_mvebu_mbus_config() 47 void __iomem base; in xhci_mvebu_mbus_init_quirk() local 58 base = ioremap(res->start, resource_size(res)); in xhci_mvebu_mbus_init_quirk() 59 if (!base) in xhci_mvebu_mbus_init_quirk() 63 xhci_mvebu_mbus_config(base, dram); in xhci_mvebu_mbus_init_quirk() 69 iounmap(base); in xhci_mvebu_mbus_init_quirk()
/linux-4.1.27/net/sctp/
D	endpointola.c	114 ep->base.type = SCTP_EP_TYPE_SOCKET; in sctp_endpoint_init() 117 atomic_set(&ep->base.refcnt, 1); in sctp_endpoint_init() 118 ep->base.dead = false; in sctp_endpoint_init() 121 sctp_inq_init(&ep->base.inqueue); in sctp_endpoint_init() 124 sctp_inq_set_th_handler(&ep->base.inqueue, sctp_endpoint_bh_rcv); in sctp_endpoint_init() 127 sctp_bind_addr_init(&ep->base.bind_addr, 0); in sctp_endpoint_init() 130 ep->base.sk = sk; in sctp_endpoint_init() 131 sock_hold(ep->base.sk); in sctp_endpoint_init() 209 struct sock *sk = ep->base.sk; in sctp_endpoint_add_asoc() 231 ep->base.dead = true; in sctp_endpoint_free() [all …]
/linux-4.1.27/drivers/char/hw_random/
D	tx4939-rng.c	30 void __iomem base; member 55 static u64 read_rng(void __iomem base, unsigned int offset) in read_rng() argument 57 return ____raw_readq(base + offset); in read_rng() 60 static void write_rng(u64 val, void __iomem *base, unsigned int offset) in write_rng() argument 62 return ____raw_writeq(val, base + offset); in write_rng() 74 if (!(read_rng(rngdev->base, TX4939_RNG_RCSR) in tx4939_rng_data_present() 77 read_rng(rngdev->base, TX4939_RNG_ROR(0)); in tx4939_rng_data_present() 79 read_rng(rngdev->base, TX4939_RNG_ROR(1)); in tx4939_rng_data_present() 81 read_rng(rngdev->base, TX4939_RNG_ROR(2)); in tx4939_rng_data_present() 86 rngdev->base, TX4939_RNG_RCSR); in tx4939_rng_data_present() [all …]
/linux-4.1.27/drivers/scsi/arm/
D	arxescsi.c	44 void __iomem base; member 75 static void arxescsi_pseudo_dma_write(unsigned char addr, void __iomem base) in arxescsi_pseudo_dma_write() argument 100 : "r" (addr), "r" (base)); in arxescsi_pseudo_dma_write() 117 void __iomem base = info->info.scsi.io_base; in arxescsi_dma_pseudo() local 126 if (readb(base + 0x80) & STAT_INT) { in arxescsi_dma_pseudo() 130 arxescsi_pseudo_dma_write(addr, base); in arxescsi_dma_pseudo() 137 if (readb(base + 0x80) & STAT_INT) in arxescsi_dma_pseudo() 140 if (!(readb(base + DMASTAT_OFFSET) & DMASTAT_DRQ)) in arxescsi_dma_pseudo() 145 writew(word, base + DMADATA_OFFSET); in arxescsi_dma_pseudo() 158 if (readb(base + 0x80) & STAT_INT) { in arxescsi_dma_pseudo() [all …]
D	cumana_1.c	33 void __iomem *base; \ 55 writeb(0x02, priv(host)->base + CTRL); in NCR5380_pwrite() 61 status = readb(priv(host)->base + STAT); in NCR5380_pwrite() 80 writeb(0x12, priv(host)->base + CTRL); in NCR5380_pwrite() 85 status = readb(priv(host)->base + STAT); in NCR5380_pwrite() 95 status = readb(priv(host)->base + STAT); in NCR5380_pwrite() 106 writeb(priv(host)->ctrl \| 0x40, priv(host)->base + CTRL); in NCR5380_pwrite() 118 writeb(0x00, priv(host)->base + CTRL); in NCR5380_pread() 123 status = readb(priv(host)->base + STAT); in NCR5380_pread() 142 writeb(0x10, priv(host)->base + CTRL); in NCR5380_pread() [all …]
/linux-4.1.27/arch/x86/realmode/
D	init.c	14 unsigned char base; in reserve_real_mode() local 22 base = __va(mem); in reserve_real_mode() 24 real_mode_header = (struct real_mode_header ) base; in reserve_real_mode() 26 base, (unsigned long long)mem, size); in reserve_real_mode() 34 unsigned char base; in setup_real_mode() local 43 base = (unsigned char )real_mode_header; in setup_real_mode() 45 memcpy(base, real_mode_blob, size); in setup_real_mode() 47 phys_base = __pa(base); in setup_real_mode() 55 u16 seg = (u16 ) (base + rel++); in setup_real_mode() 62 u32 ptr = (u32 ) (base + rel++); in setup_real_mode() [all …]
/linux-4.1.27/drivers/gpu/drm/radeon/
D	radeon_connectors.c	342 radeon_connector->edid = drm_get_edid(&radeon_connector->base, in radeon_connector_get_edid() 345 radeon_connector->edid = drm_get_edid(&radeon_connector->base, in radeon_connector_get_edid() 348 radeon_connector->edid = drm_get_edid(&radeon_connector->base, in radeon_connector_get_edid() 453 if (conflict->encoder_ids[i] == encoder->base.id) { in radeon_connector_analog_encoder_conflict_solve() 590 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property() 605 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property() 620 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property() 634 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property() 648 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property() 662 radeon_property_change_mode(&radeon_encoder->base); in radeon_connector_set_property() [all …]
/linux-4.1.27/arch/mn10300/proc-mn103e010/
D	proc-init.c	85 unsigned long base, size; in get_mem_info() local 90 base = SDBASE(0); in get_mem_info() 91 if (base & SDBASE_CE) { in get_mem_info() 92 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; in get_mem_info() 94 base &= SDBASE_CBA; in get_mem_info() 96 printk(KERN_INFO "SDRAM[0]: %luMb @%08lx\n", size >> 20, base); in get_mem_info() 98 *mem_base = base; in get_mem_info() 101 base = SDBASE(1); in get_mem_info() 102 if (base & SDBASE_CE) { in get_mem_info() 103 size = (base & SDBASE_CBAM) << SDBASE_CBAM_SHIFT; in get_mem_info() [all …]
/linux-4.1.27/arch/x86/platform/intel-quark/
D	imr_selftest.c	58 phys_addr_t base = virt_to_phys(&_text); in imr_self_test() local 59 size_t size = virt_to_phys(&__end_rodata) - base; in imr_self_test() 68 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU, false); in imr_self_test() 69 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); in imr_self_test() 72 base += size - IMR_ALIGN; in imr_self_test() 73 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU, false); in imr_self_test() 74 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); in imr_self_test() 77 base -= size + IMR_ALIGN * 2; in imr_self_test() 78 ret = imr_add_range(base, size, IMR_CPU, IMR_CPU, false); in imr_self_test() 79 imr_self_test_result(ret < 0, fmt_over, __va(base), __va(base + size)); in imr_self_test()
/linux-4.1.27/drivers/clk/berlin/
D	berlin2-avpll.c	118 void __iomem base; member 129 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_is_enabled() 141 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable() 146 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_enable() 156 reg = readl_relaxed(vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable() 161 writel_relaxed(reg, vco->base + VCO_CTRL0); in berlin2_avpll_vco_disable() 174 reg = readl_relaxed(vco->base + VCO_CTRL1); in berlin2_avpll_vco_recalc_rate() 191 struct clk __init berlin2_avpll_vco_register(void __iomem base, in berlin2_avpll_vco_register() argument 202 vco->base = base; in berlin2_avpll_vco_register() 216 void __iomem base; member [all …]
/linux-4.1.27/drivers/mtd/maps/
D	pci.c	34 void __iomem *base; member 44 val.x[0]= readb(map->base + map->translate(map, ofs)); in mtd_pci_read8() 52 val.x[0] = readl(map->base + map->translate(map, ofs)); in mtd_pci_read32() 59 memcpy_fromio(to, map->base + map->translate(map, from), len); in mtd_pci_copyfrom() 65 writeb(val.x[0], map->base + map->translate(map, ofs)); in mtd_pci_write8() 71 writel(val.x[0], map->base + map->translate(map, ofs)); in mtd_pci_write32() 77 memcpy_toio(map->base + map->translate(map, to), from, len); in mtd_pci_copyto() 100 map->base = ioremap_nocache(pci_resource_start(dev, 0), in intel_iq80310_init() 103 if (!map->base) in intel_iq80310_init() 121 if (map->base) in intel_iq80310_exit() [all …]
/linux-4.1.27/arch/mips/mti-sead3/
D	sead3-init.c	63 void base; in mips_nmi_setup() local 65 base = cpu_has_veic ? in mips_nmi_setup() 72 memcpy(base, (&except_vec_nmi - 1), 0x80); in mips_nmi_setup() 101 memcpy(base, &except_vec_nmi, 0x80); in mips_nmi_setup() 103 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); in mips_nmi_setup() 108 void base; in mips_ejtag_setup() local 110 base = cpu_has_veic ? in mips_ejtag_setup() 115 memcpy(base, (&except_vec_ejtag_debug - 1), 0x80); in mips_ejtag_setup() 126 memcpy(base, &except_vec_ejtag_debug, 0x80); in mips_ejtag_setup() 128 flush_icache_range((unsigned long)base, (unsigned long)base + 0x80); in mips_ejtag_setup()
/linux-4.1.27/security/apparmor/
D	policy.c	262 return view->base.hname + strlen(curr->base.hname) + 2; in aa_ns_name() 283 if (!policy_init(&ns->base, prefix, name)) in alloc_namespace() 306 kzfree(ns->base.hname); in alloc_namespace() 324 policy_destroy(&ns->base); in free_namespace() 394 ns = alloc_namespace(root->base.hname, name); in aa_prepare_namespace() 399 ns->base.name); in aa_prepare_namespace() 405 list_add_rcu(&ns->base.list, &root->sub_ns); in aa_prepare_namespace() 428 list_add_rcu(&profile->base.list, list); in __list_add_profile() 447 list_del_rcu(&profile->base.list); in __list_remove_profile() 462 __profile_list_release(&profile->base.profiles); in __remove_profile() [all …]
/linux-4.1.27/drivers/isdn/hisax/
D	enternow_pci.c	129 outb(0x00, cs->hw.njet.base + NETJET_IRQMASK1); in enpci_setIrqMask() 131 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); in enpci_setIrqMask() 157 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci() 161 outb(cs->hw.njet.ctrl_reg, cs->hw.njet.base + NETJET_CTRL); in reset_enpci() 166 outb(~TJ_AMD_IRQ, cs->hw.njet.base + NETJET_AUXCTRL); in reset_enpci() 167 outb(TJ_AMD_IRQ, cs->hw.njet.base + NETJET_IRQMASK1); in reset_enpci() 202 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg() 207 outb(0x00, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg() 219 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg() 232 outb(cs->hw.njet.auxd, cs->hw.njet.base + NETJET_AUXDATA); in enpci_card_msg() [all …]
/linux-4.1.27/arch/arm/mach-netx/include/mach/
D	uncompress.h	`45 unsigned long base; in putc() local 48 base = UART1_BASE; in putc() 50 base = UART2_BASE; in putc() 54 while (REG(base + UART_FR) & FR_TXFF); in putc() 55 REG(base + UART_DR) = c; in putc() 60 unsigned long base; in flush() local 63 base = UART1_BASE; in flush() 65 base = UART2_BASE; in flush() 69 while (REG(base + UART_FR) & FR_BUSY); in flush()`
/linux-4.1.27/arch/mips/pistachio/
D	init.c	75 void base; in mips_nmi_setup() local 78 base = cpu_has_veic ? in mips_nmi_setup() 81 memcpy(base, &except_vec_nmi, 0x80); in mips_nmi_setup() 82 flush_icache_range((unsigned long)base, in mips_nmi_setup() 83 (unsigned long)base + 0x80); in mips_nmi_setup() 88 void base; in mips_ejtag_setup() local 91 base = cpu_has_veic ? in mips_ejtag_setup() 94 memcpy(base, &except_vec_ejtag_debug, 0x80); in mips_ejtag_setup() 95 flush_icache_range((unsigned long)base, in mips_ejtag_setup() 96 (unsigned long)base + 0x80); in mips_ejtag_setup()
/linux-4.1.27/drivers/gpu/drm/vmwgfx/
D	vmwgfx_fence.c	53 struct ttm_base_object base; member 87 return container_of(fence->base.lock, struct vmw_fence_manager, lock); in fman_from_fence() 115 container_of(f, struct vmw_fence_obj, base); in vmw_fence_obj_destroy() 140 container_of(f, struct vmw_fence_obj, base); in vmw_fence_enable_signaling() 147 if (seqno - fence->base.seqno < VMW_FENCE_WRAP) in vmw_fence_enable_signaling() 156 struct fence_cb base; member 164 container_of(cb, struct vmwgfx_wait_cb, base); in vmwgfx_wait_cb() 174 container_of(f, struct vmw_fence_obj, base); in vmw_fence_wait() 195 cb.base.func = vmwgfx_wait_cb; in vmw_fence_wait() 197 list_add(&cb.base.node, &f->cb_list); in vmw_fence_wait() [all …]
/linux-4.1.27/arch/x86/kernel/
D	mmconf-fam10h_64.c	62 u64 base = FAM10H_PCI_MMCONF_BASE; in get_fam10h_pci_mmconf_base() local 110 if (base <= tom2) in get_fam10h_pci_mmconf_base() 111 base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK; in get_fam10h_pci_mmconf_base() 144 if (range[hi_mmio_num - 1].end < base) in get_fam10h_pci_mmconf_base() 146 if (range[0].start > base + MMCONF_SIZE) in get_fam10h_pci_mmconf_base() 150 base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT; in get_fam10h_pci_mmconf_base() 151 if ((base > tom2) && BASE_VALID(base)) in get_fam10h_pci_mmconf_base() 153 base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK; in get_fam10h_pci_mmconf_base() 154 if (BASE_VALID(base)) in get_fam10h_pci_mmconf_base() 158 base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK; in get_fam10h_pci_mmconf_base() [all …]
/linux-4.1.27/drivers/gpu/drm/nouveau/nvif/
D	client.c	32 return client->driver->ioctl(client->base.priv, client->super, data, size, NULL); in nvif_client_ioctl() 38 return client->driver->suspend(client->base.priv); in nvif_client_suspend() 44 return client->driver->resume(client->base.priv); in nvif_client_resume() 51 client->driver->fini(client->base.priv); in nvif_client_fini() 53 client->base.parent = NULL; in nvif_client_fini() 54 nvif_object_fini(&client->base); in nvif_client_fini() 77 ret = nvif_object_init(NULL, (void*)dtor, 0, 0, NULL, 0, &client->base); in nvif_client_init() 81 client->base.parent = &client->base; in nvif_client_init() 82 client->base.handle = ~0; in nvif_client_init() 83 client->object = &client->base; in nvif_client_init() [all …]
/linux-4.1.27/drivers/net/ethernet/natsemi/
D	ns83820.c	426 u8 __iomem *base; member 469 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) 479 dev->base + RXDP); in kick_rx() 620 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; in phy_intr() 624 tbisr = readl(dev->base + TBISR); in phy_intr() 625 tanar = readl(dev->base + TANAR); in phy_intr() 626 tanlpar = readl(dev->base + TANLPAR); in phy_intr() 634 writel(readl(dev->base + TXCFG) in phy_intr() 636 dev->base + TXCFG); in phy_intr() 637 writel(readl(dev->base + RXCFG) \| RXCFG_RX_FD, in phy_intr() [all …]
/linux-4.1.27/arch/arm/mach-at91/
D	sam9_smc.c	26 static void sam9_smc_cs_write_mode(void __iomem base, in sam9_smc_cs_write_mode() argument 31 base + AT91_SMC_MODE); in sam9_smc_cs_write_mode() 41 static void sam9_smc_cs_configure(void __iomem base, in sam9_smc_cs_configure() argument 50 base + AT91_SMC_SETUP); in sam9_smc_cs_configure() 57 base + AT91_SMC_PULSE); in sam9_smc_cs_configure() 62 base + AT91_SMC_CYCLE); in sam9_smc_cs_configure() 65 sam9_smc_cs_write_mode(base, config); in sam9_smc_cs_configure() 75 static void sam9_smc_cs_read_mode(void __iomem base, in sam9_smc_cs_read_mode() argument 78 u32 val = __raw_readl(base + AT91_SMC_MODE); in sam9_smc_cs_read_mode() 91 static void sam9_smc_cs_read(void __iomem base, in sam9_smc_cs_read() argument [all …]
/linux-4.1.27/arch/powerpc/boot/
D	crt0.S	233 #define SAVE_GPR(n, base) std n,8(n)(base) argument 234 #define REST_GPR(n, base) ld n,8(n)(base) argument 235 #define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) argument 236 #define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) argument 237 #define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) argument 238 #define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) argument 239 #define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) argument 240 #define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) argument 241 #define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) argument 242 #define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) argument
/linux-4.1.27/drivers/net/ethernet/hisilicon/
D	hix5hd2_gmac.c	212 void __iomem *base; member 267 writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port() 274 writel_relaxed(val, priv->base + PORT_MODE); in hix5hd2_config_port() 275 writel_relaxed(0, priv->base + MODE_CHANGE_EN); in hix5hd2_config_port() 276 writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL); in hix5hd2_config_port() 281 writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth() 282 writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH); in hix5hd2_set_desc_depth() 283 writel_relaxed(0, priv->base + RX_FQ_REG_EN); in hix5hd2_set_desc_depth() 285 writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN); in hix5hd2_set_desc_depth() 286 writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH); in hix5hd2_set_desc_depth() [all …]
/linux-4.1.27/sound/arm/
D	aaci.c	47 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_select_codec() 49 readl(aaci->base + AACI_SL2RX); in aaci_ac97_select_codec() 51 readl(aaci->base + AACI_SL1RX); in aaci_ac97_select_codec() 53 if (maincr != readl(aaci->base + AACI_MAINCR)) { in aaci_ac97_select_codec() 54 writel(maincr, aaci->base + AACI_MAINCR); in aaci_ac97_select_codec() 55 readl(aaci->base + AACI_MAINCR); in aaci_ac97_select_codec() 87 writel(val << 4, aaci->base + AACI_SL2TX); in aaci_ac97_write() 88 writel(reg << 12, aaci->base + AACI_SL1TX); in aaci_ac97_write() 97 v = readl(aaci->base + AACI_SLFR); in aaci_ac97_write() 126 writel((reg << 12) \| (1 << 19), aaci->base + AACI_SL1TX); in aaci_ac97_read() [all …]

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