51 	for (i = priv->base.min, p = 0; i < priv->base.max; i++) {  in nv50_fifo_playlist_update_locked()
75 	struct nv50_fifo_base *base = (void *)parent->parent;  in nv50_fifo_context_attach()  local
89 	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;  in nv50_fifo_context_attach()
90 	nv_wo32(base->eng, addr + 0x00, 0x00190000);  in nv50_fifo_context_attach()
91 	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));  in nv50_fifo_context_attach()
92 	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));  in nv50_fifo_context_attach()
93 	nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |  in nv50_fifo_context_attach()
95 	nv_wo32(base->eng, addr + 0x10, 0x00000000);  in nv50_fifo_context_attach()
96 	nv_wo32(base->eng, addr + 0x14, 0x00000000);  in nv50_fifo_context_attach()
107 	struct nv50_fifo_base *base = (void *)parent->parent;  in nv50_fifo_context_detach()  local
135 	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);  in nv50_fifo_context_detach()
138 			 chan->base.chid, nvkm_client_name(chan));  in nv50_fifo_context_detach()
145 		nv_wo32(base->eng, addr + 0x00, 0x00000000);  in nv50_fifo_context_detach()
146 		nv_wo32(base->eng, addr + 0x04, 0x00000000);  in nv50_fifo_context_detach()
147 		nv_wo32(base->eng, addr + 0x08, 0x00000000);  in nv50_fifo_context_detach()
148 		nv_wo32(base->eng, addr + 0x0c, 0x00000000);  in nv50_fifo_context_detach()
149 		nv_wo32(base->eng, addr + 0x10, 0x00000000);  in nv50_fifo_context_detach()
150 		nv_wo32(base->eng, addr + 0x14, 0x00000000);  in nv50_fifo_context_detach()
197 	struct nv50_fifo_base *base = (void *)parent;  in nv50_fifo_chan_ctor_dma()  local
219 	args->v0.chid = chan->base.chid;  in nv50_fifo_chan_ctor_dma()
231 	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
232 	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
233 	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
234 	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));  in nv50_fifo_chan_ctor_dma()
235 	nv_wo32(base->ramfc, 0x3c, 0x003f6078);  in nv50_fifo_chan_ctor_dma()
236 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in nv50_fifo_chan_ctor_dma()
237 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in nv50_fifo_chan_ctor_dma()
238 	nv_wo32(base->ramfc, 0x4c, 0xffffffff);  in nv50_fifo_chan_ctor_dma()
239 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in nv50_fifo_chan_ctor_dma()
240 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in nv50_fifo_chan_ctor_dma()
241 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in nv50_fifo_chan_ctor_dma()
242 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in nv50_fifo_chan_ctor_dma()
258 	struct nv50_fifo_base *base = (void *)parent;  in nv50_fifo_chan_ctor_ind()  local
282 	args->v0.chid = chan->base.chid;  in nv50_fifo_chan_ctor_ind()
297 	nv_wo32(base->ramfc, 0x3c, 0x403f6078);  in nv50_fifo_chan_ctor_ind()
298 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in nv50_fifo_chan_ctor_ind()
299 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in nv50_fifo_chan_ctor_ind()
300 	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));  in nv50_fifo_chan_ctor_ind()
301 	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));  in nv50_fifo_chan_ctor_ind()
302 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in nv50_fifo_chan_ctor_ind()
303 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in nv50_fifo_chan_ctor_ind()
304 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in nv50_fifo_chan_ctor_ind()
305 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in nv50_fifo_chan_ctor_ind()
317 	nvkm_fifo_channel_destroy(&chan->base);  in nv50_fifo_chan_dtor()
324 	struct nv50_fifo_base *base = (void *)object->parent;  in nv50_fifo_chan_init()  local
326 	struct nvkm_gpuobj *ramfc = base->ramfc;  in nv50_fifo_chan_init()
327 	u32 chid = chan->base.chid;  in nv50_fifo_chan_init()
330 	ret = nvkm_fifo_channel_init(&chan->base);  in nv50_fifo_chan_init()
344 	u32 chid = chan->base.chid;  in nv50_fifo_chan_fini()
351 	return nvkm_fifo_channel_fini(&chan->base, suspend);  in nv50_fifo_chan_fini()
394 	struct nv50_fifo_base *base;  in nv50_fifo_context_ctor()  local
398 				       0x1000, NVOBJ_FLAG_HEAP, &base);  in nv50_fifo_context_ctor()
399 	*pobject = nv_object(base);  in nv50_fifo_context_ctor()
403 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200,  in nv50_fifo_context_ctor()
404 			      0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);  in nv50_fifo_context_ctor()
408 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1200, 0,  in nv50_fifo_context_ctor()
409 			      NVOBJ_FLAG_ZERO_ALLOC, &base->eng);  in nv50_fifo_context_ctor()
413 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0, 0,  in nv50_fifo_context_ctor()
414 			      &base->pgd);  in nv50_fifo_context_ctor()
418 	ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);  in nv50_fifo_context_ctor()
428 	struct nv50_fifo_base *base = (void *)object;  in nv50_fifo_context_dtor()  local
429 	nvkm_vm_ref(NULL, &base->vm, base->pgd);  in nv50_fifo_context_dtor()
430 	nvkm_gpuobj_ref(NULL, &base->pgd);  in nv50_fifo_context_dtor()
431 	nvkm_gpuobj_ref(NULL, &base->eng);  in nv50_fifo_context_dtor()
432 	nvkm_gpuobj_ref(NULL, &base->ramfc);  in nv50_fifo_context_dtor()
433 	nvkm_gpuobj_ref(NULL, &base->cache);  in nv50_fifo_context_dtor()
434 	nvkm_fifo_context_destroy(&base->base);  in nv50_fifo_context_dtor()
481 	priv->base.pause = nv04_fifo_pause;  in nv50_fifo_ctor()
482 	priv->base.start = nv04_fifo_start;  in nv50_fifo_ctor()
494 	nvkm_fifo_destroy(&priv->base);  in nv50_fifo_dtor()
503 	ret = nvkm_fifo_init(&priv->base);  in nv50_fifo_init()