1/*
2 * interrupt controller support for CSR SiRFprimaII
3 *
4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include <linux/init.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/of.h>
13#include <linux/of_address.h>
14#include <linux/irqdomain.h>
15#include <linux/syscore_ops.h>
16#include <asm/mach/irq.h>
17#include <asm/exception.h>
18#include "irqchip.h"
19
20#define SIRFSOC_INT_RISC_MASK0          0x0018
21#define SIRFSOC_INT_RISC_MASK1          0x001C
22#define SIRFSOC_INT_RISC_LEVEL0         0x0020
23#define SIRFSOC_INT_RISC_LEVEL1         0x0024
24#define SIRFSOC_INIT_IRQ_ID		0x0038
25
26#define SIRFSOC_NUM_IRQS		64
27
28static struct irq_domain *sirfsoc_irqdomain;
29
30static __init void
31sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
32{
33	struct irq_chip_generic *gc;
34	struct irq_chip_type *ct;
35	int ret;
36	unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
37	unsigned int set = IRQ_LEVEL;
38
39	ret = irq_alloc_domain_generic_chips(sirfsoc_irqdomain, num, 1, "irq_sirfsoc",
40		handle_level_irq, clr, set, IRQ_GC_INIT_MASK_CACHE);
41
42	gc = irq_get_domain_generic_chip(sirfsoc_irqdomain, irq_start);
43	gc->reg_base = base;
44	ct = gc->chip_types;
45	ct->chip.irq_mask = irq_gc_mask_clr_bit;
46	ct->chip.irq_unmask = irq_gc_mask_set_bit;
47	ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
48}
49
50static void __exception_irq_entry sirfsoc_handle_irq(struct pt_regs *regs)
51{
52	void __iomem *base = sirfsoc_irqdomain->host_data;
53	u32 irqstat;
54
55	irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID);
56	handle_domain_irq(sirfsoc_irqdomain, irqstat & 0xff, regs);
57}
58
59static int __init sirfsoc_irq_init(struct device_node *np,
60	struct device_node *parent)
61{
62	void __iomem *base = of_iomap(np, 0);
63	if (!base)
64		panic("unable to map intc cpu registers\n");
65
66	sirfsoc_irqdomain = irq_domain_add_linear(np, SIRFSOC_NUM_IRQS,
67		&irq_generic_chip_ops, base);
68
69	sirfsoc_alloc_gc(base, 0, 32);
70	sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32);
71
72	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0);
73	writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL1);
74
75	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK0);
76	writel_relaxed(0, base + SIRFSOC_INT_RISC_MASK1);
77
78	set_handle_irq(sirfsoc_handle_irq);
79
80	return 0;
81}
82IRQCHIP_DECLARE(sirfsoc_intc, "sirf,prima2-intc", sirfsoc_irq_init);
83
84struct sirfsoc_irq_status {
85	u32 mask0;
86	u32 mask1;
87	u32 level0;
88	u32 level1;
89};
90
91static struct sirfsoc_irq_status sirfsoc_irq_st;
92
93static int sirfsoc_irq_suspend(void)
94{
95	void __iomem *base = sirfsoc_irqdomain->host_data;
96
97	sirfsoc_irq_st.mask0 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK0);
98	sirfsoc_irq_st.mask1 = readl_relaxed(base + SIRFSOC_INT_RISC_MASK1);
99	sirfsoc_irq_st.level0 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL0);
100	sirfsoc_irq_st.level1 = readl_relaxed(base + SIRFSOC_INT_RISC_LEVEL1);
101
102	return 0;
103}
104
105static void sirfsoc_irq_resume(void)
106{
107	void __iomem *base = sirfsoc_irqdomain->host_data;
108
109	writel_relaxed(sirfsoc_irq_st.mask0, base + SIRFSOC_INT_RISC_MASK0);
110	writel_relaxed(sirfsoc_irq_st.mask1, base + SIRFSOC_INT_RISC_MASK1);
111	writel_relaxed(sirfsoc_irq_st.level0, base + SIRFSOC_INT_RISC_LEVEL0);
112	writel_relaxed(sirfsoc_irq_st.level1, base + SIRFSOC_INT_RISC_LEVEL1);
113}
114
115static struct syscore_ops sirfsoc_irq_syscore_ops = {
116	.suspend	= sirfsoc_irq_suspend,
117	.resume		= sirfsoc_irq_resume,
118};
119
120static int __init sirfsoc_irq_pm_init(void)
121{
122	if (!sirfsoc_irqdomain)
123		return 0;
124
125	register_syscore_ops(&sirfsoc_irq_syscore_ops);
126	return 0;
127}
128device_initcall(sirfsoc_irq_pm_init);
129