45 	struct nv50_fifo_base *base = (void *)parent->parent;  in g84_fifo_context_attach()  local
67 	nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;  in g84_fifo_context_attach()
68 	nv_wo32(base->eng, addr + 0x00, 0x00190000);  in g84_fifo_context_attach()
69 	nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit));  in g84_fifo_context_attach()
70 	nv_wo32(base->eng, addr + 0x08, lower_32_bits(start));  in g84_fifo_context_attach()
71 	nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 |  in g84_fifo_context_attach()
73 	nv_wo32(base->eng, addr + 0x10, 0x00000000);  in g84_fifo_context_attach()
74 	nv_wo32(base->eng, addr + 0x14, 0x00000000);  in g84_fifo_context_attach()
85 	struct nv50_fifo_base *base = (void *)parent->parent;  in g84_fifo_context_detach()  local
107 	nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12);  in g84_fifo_context_detach()
112 			 chan->base.chid, nvkm_client_name(chan));  in g84_fifo_context_detach()
117 	nv_wo32(base->eng, addr + 0x00, 0x00000000);  in g84_fifo_context_detach()
118 	nv_wo32(base->eng, addr + 0x04, 0x00000000);  in g84_fifo_context_detach()
119 	nv_wo32(base->eng, addr + 0x08, 0x00000000);  in g84_fifo_context_detach()
120 	nv_wo32(base->eng, addr + 0x0c, 0x00000000);  in g84_fifo_context_detach()
121 	nv_wo32(base->eng, addr + 0x10, 0x00000000);  in g84_fifo_context_detach()
122 	nv_wo32(base->eng, addr + 0x14, 0x00000000);  in g84_fifo_context_detach()
170 	struct nv50_fifo_base *base = (void *)parent;  in g84_fifo_chan_ctor_dma()  local
202 	args->v0.chid = chan->base.chid;  in g84_fifo_chan_ctor_dma()
214 	nv_wo32(base->ramfc, 0x08, lower_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
215 	nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
216 	nv_wo32(base->ramfc, 0x10, lower_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
217 	nv_wo32(base->ramfc, 0x14, upper_32_bits(args->v0.offset));  in g84_fifo_chan_ctor_dma()
218 	nv_wo32(base->ramfc, 0x3c, 0x003f6078);  in g84_fifo_chan_ctor_dma()
219 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in g84_fifo_chan_ctor_dma()
220 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in g84_fifo_chan_ctor_dma()
221 	nv_wo32(base->ramfc, 0x4c, 0xffffffff);  in g84_fifo_chan_ctor_dma()
222 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in g84_fifo_chan_ctor_dma()
223 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in g84_fifo_chan_ctor_dma()
224 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in g84_fifo_chan_ctor_dma()
225 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in g84_fifo_chan_ctor_dma()
228 	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);  in g84_fifo_chan_ctor_dma()
229 	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);  in g84_fifo_chan_ctor_dma()
243 	struct nv50_fifo_base *base = (void *)parent;  in g84_fifo_chan_ctor_ind()  local
277 	args->v0.chid = chan->base.chid;  in g84_fifo_chan_ctor_ind()
292 	nv_wo32(base->ramfc, 0x3c, 0x403f6078);  in g84_fifo_chan_ctor_ind()
293 	nv_wo32(base->ramfc, 0x44, 0x01003fff);  in g84_fifo_chan_ctor_ind()
294 	nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4);  in g84_fifo_chan_ctor_ind()
295 	nv_wo32(base->ramfc, 0x50, lower_32_bits(ioffset));  in g84_fifo_chan_ctor_ind()
296 	nv_wo32(base->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16));  in g84_fifo_chan_ctor_ind()
297 	nv_wo32(base->ramfc, 0x60, 0x7fffffff);  in g84_fifo_chan_ctor_ind()
298 	nv_wo32(base->ramfc, 0x78, 0x00000000);  in g84_fifo_chan_ctor_ind()
299 	nv_wo32(base->ramfc, 0x7c, 0x30000001);  in g84_fifo_chan_ctor_ind()
300 	nv_wo32(base->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |  in g84_fifo_chan_ctor_ind()
303 	nv_wo32(base->ramfc, 0x88, base->cache->addr >> 10);  in g84_fifo_chan_ctor_ind()
304 	nv_wo32(base->ramfc, 0x98, nv_gpuobj(base)->addr >> 12);  in g84_fifo_chan_ctor_ind()
313 	struct nv50_fifo_base *base = (void *)object->parent;  in g84_fifo_chan_init()  local
315 	struct nvkm_gpuobj *ramfc = base->ramfc;  in g84_fifo_chan_init()
316 	u32 chid = chan->base.chid;  in g84_fifo_chan_init()
319 	ret = nvkm_fifo_channel_init(&chan->base);  in g84_fifo_chan_init()
368 	struct nv50_fifo_base *base;  in g84_fifo_context_ctor()  local
372 				       0x1000, NVOBJ_FLAG_HEAP, &base);  in g84_fifo_context_ctor()
373 	*pobject = nv_object(base);  in g84_fifo_context_ctor()
377 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0200, 0,  in g84_fifo_context_ctor()
378 			      NVOBJ_FLAG_ZERO_ALLOC, &base->eng);  in g84_fifo_context_ctor()
382 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x4000, 0,  in g84_fifo_context_ctor()
383 			      0, &base->pgd);  in g84_fifo_context_ctor()
387 	ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);  in g84_fifo_context_ctor()
391 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x1000,  in g84_fifo_context_ctor()
392 			      0x400, NVOBJ_FLAG_ZERO_ALLOC, &base->cache);  in g84_fifo_context_ctor()
396 	ret = nvkm_gpuobj_new(nv_object(base), nv_object(base), 0x0100,  in g84_fifo_context_ctor()
397 			      0x100, NVOBJ_FLAG_ZERO_ALLOC, &base->ramfc);  in g84_fifo_context_ctor()
465 	ret = nvkm_event_init(&g84_fifo_uevent_func, 1, 1, &priv->base.uevent);  in g84_fifo_ctor()
473 	priv->base.pause = nv04_fifo_pause;  in g84_fifo_ctor()
474 	priv->base.start = nv04_fifo_start;  in g84_fifo_ctor()