1/* 2 * I2C bus driver for CSR SiRFprimaII 3 * 4 * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company. 5 * 6 * Licensed under GPLv2 or later. 7 */ 8 9#include <linux/interrupt.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/slab.h> 13#include <linux/platform_device.h> 14#include <linux/i2c.h> 15#include <linux/clk.h> 16#include <linux/err.h> 17#include <linux/io.h> 18 19#define SIRFSOC_I2C_CLK_CTRL 0x00 20#define SIRFSOC_I2C_STATUS 0x0C 21#define SIRFSOC_I2C_CTRL 0x10 22#define SIRFSOC_I2C_IO_CTRL 0x14 23#define SIRFSOC_I2C_SDA_DELAY 0x18 24#define SIRFSOC_I2C_CMD_START 0x1C 25#define SIRFSOC_I2C_CMD_BUF 0x30 26#define SIRFSOC_I2C_DATA_BUF 0x80 27 28#define SIRFSOC_I2C_CMD_BUF_MAX 16 29#define SIRFSOC_I2C_DATA_BUF_MAX 16 30 31#define SIRFSOC_I2C_CMD(x) (SIRFSOC_I2C_CMD_BUF + (x)*0x04) 32#define SIRFSOC_I2C_DATA_MASK(x) (0xFF<<(((x)&3)*8)) 33#define SIRFSOC_I2C_DATA_SHIFT(x) (((x)&3)*8) 34 35#define SIRFSOC_I2C_DIV_MASK (0xFFFF) 36 37/* I2C status flags */ 38#define SIRFSOC_I2C_STAT_BUSY BIT(0) 39#define SIRFSOC_I2C_STAT_TIP BIT(1) 40#define SIRFSOC_I2C_STAT_NACK BIT(2) 41#define SIRFSOC_I2C_STAT_TR_INT BIT(4) 42#define SIRFSOC_I2C_STAT_STOP BIT(6) 43#define SIRFSOC_I2C_STAT_CMD_DONE BIT(8) 44#define SIRFSOC_I2C_STAT_ERR BIT(9) 45#define SIRFSOC_I2C_CMD_INDEX (0x1F<<16) 46 47/* I2C control flags */ 48#define SIRFSOC_I2C_RESET BIT(0) 49#define SIRFSOC_I2C_CORE_EN BIT(1) 50#define SIRFSOC_I2C_MASTER_MODE BIT(2) 51#define SIRFSOC_I2C_CMD_DONE_EN BIT(11) 52#define SIRFSOC_I2C_ERR_INT_EN BIT(12) 53 54#define SIRFSOC_I2C_SDA_DELAY_MASK (0xFF) 55#define SIRFSOC_I2C_SCLF_FILTER (3<<8) 56 57#define SIRFSOC_I2C_START_CMD BIT(0) 58 59#define SIRFSOC_I2C_CMD_RP(x) ((x)&0x7) 60#define SIRFSOC_I2C_NACK BIT(3) 61#define SIRFSOC_I2C_WRITE BIT(4) 62#define SIRFSOC_I2C_READ BIT(5) 63#define SIRFSOC_I2C_STOP BIT(6) 64#define SIRFSOC_I2C_START BIT(7) 65 66#define SIRFSOC_I2C_DEFAULT_SPEED 100000 67#define SIRFSOC_I2C_ERR_NOACK 1 68#define SIRFSOC_I2C_ERR_TIMEOUT 2 69 70struct sirfsoc_i2c { 71 void __iomem *base; 72 struct clk *clk; 73 u32 cmd_ptr; /* Current position in CMD buffer */ 74 u8 *buf; /* Buffer passed by user */ 75 u32 msg_len; /* Message length */ 76 u32 finished_len; /* number of bytes read/written */ 77 u32 read_cmd_len; /* number of read cmd sent */ 78 int msg_read; /* 1 indicates a read message */ 79 int err_status; /* 1 indicates an error on bus */ 80 81 u32 sda_delay; /* For suspend/resume */ 82 u32 clk_div; 83 int last; /* Last message in transfer, STOP cmd can be sent */ 84 85 struct completion done; /* indicates completion of message transfer */ 86 struct i2c_adapter adapter; 87}; 88 89static void i2c_sirfsoc_read_data(struct sirfsoc_i2c *siic) 90{ 91 u32 data = 0; 92 int i; 93 94 for (i = 0; i < siic->read_cmd_len; i++) { 95 if (!(i & 0x3)) 96 data = readl(siic->base + SIRFSOC_I2C_DATA_BUF + i); 97 siic->buf[siic->finished_len++] = 98 (u8)((data & SIRFSOC_I2C_DATA_MASK(i)) >> 99 SIRFSOC_I2C_DATA_SHIFT(i)); 100 } 101} 102 103static void i2c_sirfsoc_queue_cmd(struct sirfsoc_i2c *siic) 104{ 105 u32 regval; 106 int i = 0; 107 108 if (siic->msg_read) { 109 while (((siic->finished_len + i) < siic->msg_len) 110 && (siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX)) { 111 regval = SIRFSOC_I2C_READ | SIRFSOC_I2C_CMD_RP(0); 112 if (((siic->finished_len + i) == 113 (siic->msg_len - 1)) && siic->last) 114 regval |= SIRFSOC_I2C_STOP | SIRFSOC_I2C_NACK; 115 writel(regval, 116 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 117 i++; 118 } 119 120 siic->read_cmd_len = i; 121 } else { 122 while ((siic->cmd_ptr < SIRFSOC_I2C_CMD_BUF_MAX - 1) 123 && (siic->finished_len < siic->msg_len)) { 124 regval = SIRFSOC_I2C_WRITE | SIRFSOC_I2C_CMD_RP(0); 125 if ((siic->finished_len == (siic->msg_len - 1)) 126 && siic->last) 127 regval |= SIRFSOC_I2C_STOP; 128 writel(regval, 129 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 130 writel(siic->buf[siic->finished_len++], 131 siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 132 } 133 } 134 siic->cmd_ptr = 0; 135 136 /* Trigger the transfer */ 137 writel(SIRFSOC_I2C_START_CMD, siic->base + SIRFSOC_I2C_CMD_START); 138} 139 140static irqreturn_t i2c_sirfsoc_irq(int irq, void *dev_id) 141{ 142 struct sirfsoc_i2c *siic = (struct sirfsoc_i2c *)dev_id; 143 u32 i2c_stat = readl(siic->base + SIRFSOC_I2C_STATUS); 144 145 if (i2c_stat & SIRFSOC_I2C_STAT_ERR) { 146 /* Error conditions */ 147 siic->err_status = SIRFSOC_I2C_ERR_NOACK; 148 writel(SIRFSOC_I2C_STAT_ERR, siic->base + SIRFSOC_I2C_STATUS); 149 150 if (i2c_stat & SIRFSOC_I2C_STAT_NACK) 151 dev_dbg(&siic->adapter.dev, "ACK not received\n"); 152 else 153 dev_err(&siic->adapter.dev, "I2C error\n"); 154 155 /* 156 * Due to hardware ANOMALY, we need to reset I2C earlier after 157 * we get NOACK while accessing non-existing clients, otherwise 158 * we will get errors even we access existing clients later 159 */ 160 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, 161 siic->base + SIRFSOC_I2C_CTRL); 162 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) 163 cpu_relax(); 164 165 complete(&siic->done); 166 } else if (i2c_stat & SIRFSOC_I2C_STAT_CMD_DONE) { 167 /* CMD buffer execution complete */ 168 if (siic->msg_read) 169 i2c_sirfsoc_read_data(siic); 170 if (siic->finished_len == siic->msg_len) 171 complete(&siic->done); 172 else /* Fill a new CMD buffer for left data */ 173 i2c_sirfsoc_queue_cmd(siic); 174 175 writel(SIRFSOC_I2C_STAT_CMD_DONE, siic->base + SIRFSOC_I2C_STATUS); 176 } 177 178 return IRQ_HANDLED; 179} 180 181static void i2c_sirfsoc_set_address(struct sirfsoc_i2c *siic, 182 struct i2c_msg *msg) 183{ 184 unsigned char addr; 185 u32 regval = SIRFSOC_I2C_START | SIRFSOC_I2C_CMD_RP(0) | SIRFSOC_I2C_WRITE; 186 187 /* no data and last message -> add STOP */ 188 if (siic->last && (msg->len == 0)) 189 regval |= SIRFSOC_I2C_STOP; 190 191 writel(regval, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 192 193 addr = msg->addr << 1; /* Generate address */ 194 if (msg->flags & I2C_M_RD) 195 addr |= 1; 196 197 /* Reverse direction bit */ 198 if (msg->flags & I2C_M_REV_DIR_ADDR) 199 addr ^= 1; 200 201 writel(addr, siic->base + SIRFSOC_I2C_CMD(siic->cmd_ptr++)); 202} 203 204static int i2c_sirfsoc_xfer_msg(struct sirfsoc_i2c *siic, struct i2c_msg *msg) 205{ 206 u32 regval = readl(siic->base + SIRFSOC_I2C_CTRL); 207 /* timeout waiting for the xfer to finish or fail */ 208 int timeout = msecs_to_jiffies((msg->len + 1) * 50); 209 210 i2c_sirfsoc_set_address(siic, msg); 211 212 writel(regval | SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN, 213 siic->base + SIRFSOC_I2C_CTRL); 214 i2c_sirfsoc_queue_cmd(siic); 215 216 if (wait_for_completion_timeout(&siic->done, timeout) == 0) { 217 siic->err_status = SIRFSOC_I2C_ERR_TIMEOUT; 218 dev_err(&siic->adapter.dev, "Transfer timeout\n"); 219 } 220 221 writel(regval & ~(SIRFSOC_I2C_CMD_DONE_EN | SIRFSOC_I2C_ERR_INT_EN), 222 siic->base + SIRFSOC_I2C_CTRL); 223 writel(0, siic->base + SIRFSOC_I2C_CMD_START); 224 225 /* i2c control doesn't response, reset it */ 226 if (siic->err_status == SIRFSOC_I2C_ERR_TIMEOUT) { 227 writel(readl(siic->base + SIRFSOC_I2C_CTRL) | SIRFSOC_I2C_RESET, 228 siic->base + SIRFSOC_I2C_CTRL); 229 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) 230 cpu_relax(); 231 } 232 return siic->err_status ? -EAGAIN : 0; 233} 234 235static u32 i2c_sirfsoc_func(struct i2c_adapter *adap) 236{ 237 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 238} 239 240static int i2c_sirfsoc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 241 int num) 242{ 243 struct sirfsoc_i2c *siic = adap->algo_data; 244 int i, ret; 245 246 clk_enable(siic->clk); 247 248 for (i = 0; i < num; i++) { 249 siic->buf = msgs[i].buf; 250 siic->msg_len = msgs[i].len; 251 siic->msg_read = !!(msgs[i].flags & I2C_M_RD); 252 siic->err_status = 0; 253 siic->cmd_ptr = 0; 254 siic->finished_len = 0; 255 siic->last = (i == (num - 1)); 256 257 ret = i2c_sirfsoc_xfer_msg(siic, &msgs[i]); 258 if (ret) { 259 clk_disable(siic->clk); 260 return ret; 261 } 262 } 263 264 clk_disable(siic->clk); 265 return num; 266} 267 268/* I2C algorithms associated with this master controller driver */ 269static const struct i2c_algorithm i2c_sirfsoc_algo = { 270 .master_xfer = i2c_sirfsoc_xfer, 271 .functionality = i2c_sirfsoc_func, 272}; 273 274static int i2c_sirfsoc_probe(struct platform_device *pdev) 275{ 276 struct sirfsoc_i2c *siic; 277 struct i2c_adapter *adap; 278 struct resource *mem_res; 279 struct clk *clk; 280 int bitrate; 281 int ctrl_speed; 282 int irq; 283 284 int err; 285 u32 regval; 286 287 clk = clk_get(&pdev->dev, NULL); 288 if (IS_ERR(clk)) { 289 err = PTR_ERR(clk); 290 dev_err(&pdev->dev, "Clock get failed\n"); 291 goto err_get_clk; 292 } 293 294 err = clk_prepare(clk); 295 if (err) { 296 dev_err(&pdev->dev, "Clock prepare failed\n"); 297 goto err_clk_prep; 298 } 299 300 err = clk_enable(clk); 301 if (err) { 302 dev_err(&pdev->dev, "Clock enable failed\n"); 303 goto err_clk_en; 304 } 305 306 ctrl_speed = clk_get_rate(clk); 307 308 siic = devm_kzalloc(&pdev->dev, sizeof(*siic), GFP_KERNEL); 309 if (!siic) { 310 err = -ENOMEM; 311 goto out; 312 } 313 adap = &siic->adapter; 314 adap->class = I2C_CLASS_DEPRECATED; 315 316 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 317 siic->base = devm_ioremap_resource(&pdev->dev, mem_res); 318 if (IS_ERR(siic->base)) { 319 err = PTR_ERR(siic->base); 320 goto out; 321 } 322 323 irq = platform_get_irq(pdev, 0); 324 if (irq < 0) { 325 err = irq; 326 goto out; 327 } 328 err = devm_request_irq(&pdev->dev, irq, i2c_sirfsoc_irq, 0, 329 dev_name(&pdev->dev), siic); 330 if (err) 331 goto out; 332 333 adap->algo = &i2c_sirfsoc_algo; 334 adap->algo_data = siic; 335 adap->retries = 3; 336 337 adap->dev.of_node = pdev->dev.of_node; 338 adap->dev.parent = &pdev->dev; 339 adap->nr = pdev->id; 340 341 strlcpy(adap->name, "sirfsoc-i2c", sizeof(adap->name)); 342 343 platform_set_drvdata(pdev, adap); 344 init_completion(&siic->done); 345 346 /* Controller Initalisation */ 347 348 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); 349 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) 350 cpu_relax(); 351 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, 352 siic->base + SIRFSOC_I2C_CTRL); 353 354 siic->clk = clk; 355 356 err = of_property_read_u32(pdev->dev.of_node, 357 "clock-frequency", &bitrate); 358 if (err < 0) 359 bitrate = SIRFSOC_I2C_DEFAULT_SPEED; 360 361 if (bitrate < 100000) 362 regval = 363 (2 * ctrl_speed) / (bitrate * 11); 364 else 365 regval = ctrl_speed / (bitrate * 5); 366 367 writel(regval, siic->base + SIRFSOC_I2C_CLK_CTRL); 368 if (regval > 0xFF) 369 writel(0xFF, siic->base + SIRFSOC_I2C_SDA_DELAY); 370 else 371 writel(regval, siic->base + SIRFSOC_I2C_SDA_DELAY); 372 373 err = i2c_add_numbered_adapter(adap); 374 if (err < 0) { 375 dev_err(&pdev->dev, "Can't add new i2c adapter\n"); 376 goto out; 377 } 378 379 clk_disable(clk); 380 381 dev_info(&pdev->dev, " I2C adapter ready to operate\n"); 382 383 return 0; 384 385out: 386 clk_disable(clk); 387err_clk_en: 388 clk_unprepare(clk); 389err_clk_prep: 390 clk_put(clk); 391err_get_clk: 392 return err; 393} 394 395static int i2c_sirfsoc_remove(struct platform_device *pdev) 396{ 397 struct i2c_adapter *adapter = platform_get_drvdata(pdev); 398 struct sirfsoc_i2c *siic = adapter->algo_data; 399 400 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); 401 i2c_del_adapter(adapter); 402 clk_unprepare(siic->clk); 403 clk_put(siic->clk); 404 return 0; 405} 406 407#ifdef CONFIG_PM 408static int i2c_sirfsoc_suspend(struct device *dev) 409{ 410 struct platform_device *pdev = to_platform_device(dev); 411 struct i2c_adapter *adapter = platform_get_drvdata(pdev); 412 struct sirfsoc_i2c *siic = adapter->algo_data; 413 414 clk_enable(siic->clk); 415 siic->sda_delay = readl(siic->base + SIRFSOC_I2C_SDA_DELAY); 416 siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL); 417 clk_disable(siic->clk); 418 return 0; 419} 420 421static int i2c_sirfsoc_resume(struct device *dev) 422{ 423 struct platform_device *pdev = to_platform_device(dev); 424 struct i2c_adapter *adapter = platform_get_drvdata(pdev); 425 struct sirfsoc_i2c *siic = adapter->algo_data; 426 427 clk_enable(siic->clk); 428 writel(SIRFSOC_I2C_RESET, siic->base + SIRFSOC_I2C_CTRL); 429 while (readl(siic->base + SIRFSOC_I2C_CTRL) & SIRFSOC_I2C_RESET) 430 cpu_relax(); 431 writel(SIRFSOC_I2C_CORE_EN | SIRFSOC_I2C_MASTER_MODE, 432 siic->base + SIRFSOC_I2C_CTRL); 433 writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL); 434 writel(siic->sda_delay, siic->base + SIRFSOC_I2C_SDA_DELAY); 435 clk_disable(siic->clk); 436 return 0; 437} 438 439static const struct dev_pm_ops i2c_sirfsoc_pm_ops = { 440 .suspend = i2c_sirfsoc_suspend, 441 .resume = i2c_sirfsoc_resume, 442}; 443#endif 444 445static const struct of_device_id sirfsoc_i2c_of_match[] = { 446 { .compatible = "sirf,prima2-i2c", }, 447 {}, 448}; 449MODULE_DEVICE_TABLE(of, sirfsoc_i2c_of_match); 450 451static struct platform_driver i2c_sirfsoc_driver = { 452 .driver = { 453 .name = "sirfsoc_i2c", 454#ifdef CONFIG_PM 455 .pm = &i2c_sirfsoc_pm_ops, 456#endif 457 .of_match_table = sirfsoc_i2c_of_match, 458 }, 459 .probe = i2c_sirfsoc_probe, 460 .remove = i2c_sirfsoc_remove, 461}; 462module_platform_driver(i2c_sirfsoc_driver); 463 464MODULE_DESCRIPTION("SiRF SoC I2C master controller driver"); 465MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, " 466 "Xiangzhen Ye <Xiangzhen.Ye@csr.com>"); 467MODULE_LICENSE("GPL v2"); 468