1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv50.h"
25
26#include <nvif/class.h>
27
28/*******************************************************************************
29 * EVO master channel object
30 ******************************************************************************/
31
32const struct nv50_disp_mthd_list
33g84_disp_core_mthd_dac = {
34	.mthd = 0x0080,
35	.addr = 0x000008,
36	.data = {
37		{ 0x0400, 0x610b58 },
38		{ 0x0404, 0x610bdc },
39		{ 0x0420, 0x610bc4 },
40		{}
41	}
42};
43
44const struct nv50_disp_mthd_list
45g84_disp_core_mthd_head = {
46	.mthd = 0x0400,
47	.addr = 0x000540,
48	.data = {
49		{ 0x0800, 0x610ad8 },
50		{ 0x0804, 0x610ad0 },
51		{ 0x0808, 0x610a48 },
52		{ 0x080c, 0x610a78 },
53		{ 0x0810, 0x610ac0 },
54		{ 0x0814, 0x610af8 },
55		{ 0x0818, 0x610b00 },
56		{ 0x081c, 0x610ae8 },
57		{ 0x0820, 0x610af0 },
58		{ 0x0824, 0x610b08 },
59		{ 0x0828, 0x610b10 },
60		{ 0x082c, 0x610a68 },
61		{ 0x0830, 0x610a60 },
62		{ 0x0834, 0x000000 },
63		{ 0x0838, 0x610a40 },
64		{ 0x0840, 0x610a24 },
65		{ 0x0844, 0x610a2c },
66		{ 0x0848, 0x610aa8 },
67		{ 0x084c, 0x610ab0 },
68		{ 0x085c, 0x610c5c },
69		{ 0x0860, 0x610a84 },
70		{ 0x0864, 0x610a90 },
71		{ 0x0868, 0x610b18 },
72		{ 0x086c, 0x610b20 },
73		{ 0x0870, 0x610ac8 },
74		{ 0x0874, 0x610a38 },
75		{ 0x0878, 0x610c50 },
76		{ 0x0880, 0x610a58 },
77		{ 0x0884, 0x610a9c },
78		{ 0x089c, 0x610c68 },
79		{ 0x08a0, 0x610a70 },
80		{ 0x08a4, 0x610a50 },
81		{ 0x08a8, 0x610ae0 },
82		{ 0x08c0, 0x610b28 },
83		{ 0x08c4, 0x610b30 },
84		{ 0x08c8, 0x610b40 },
85		{ 0x08d4, 0x610b38 },
86		{ 0x08d8, 0x610b48 },
87		{ 0x08dc, 0x610b50 },
88		{ 0x0900, 0x610a18 },
89		{ 0x0904, 0x610ab8 },
90		{ 0x0910, 0x610c70 },
91		{ 0x0914, 0x610c78 },
92		{}
93	}
94};
95
96const struct nv50_disp_mthd_chan
97g84_disp_core_mthd_chan = {
98	.name = "Core",
99	.addr = 0x000000,
100	.data = {
101		{ "Global", 1, &nv50_disp_core_mthd_base },
102		{    "DAC", 3, &g84_disp_core_mthd_dac  },
103		{    "SOR", 2, &nv50_disp_core_mthd_sor  },
104		{   "PIOR", 3, &nv50_disp_core_mthd_pior },
105		{   "HEAD", 2, &g84_disp_core_mthd_head },
106		{}
107	}
108};
109
110/*******************************************************************************
111 * EVO sync channel objects
112 ******************************************************************************/
113
114static const struct nv50_disp_mthd_list
115g84_disp_base_mthd_base = {
116	.mthd = 0x0000,
117	.addr = 0x000000,
118	.data = {
119		{ 0x0080, 0x000000 },
120		{ 0x0084, 0x0008c4 },
121		{ 0x0088, 0x0008d0 },
122		{ 0x008c, 0x0008dc },
123		{ 0x0090, 0x0008e4 },
124		{ 0x0094, 0x610884 },
125		{ 0x00a0, 0x6108a0 },
126		{ 0x00a4, 0x610878 },
127		{ 0x00c0, 0x61086c },
128		{ 0x00c4, 0x610800 },
129		{ 0x00c8, 0x61080c },
130		{ 0x00cc, 0x610818 },
131		{ 0x00e0, 0x610858 },
132		{ 0x00e4, 0x610860 },
133		{ 0x00e8, 0x6108ac },
134		{ 0x00ec, 0x6108b4 },
135		{ 0x00fc, 0x610824 },
136		{ 0x0100, 0x610894 },
137		{ 0x0104, 0x61082c },
138		{ 0x0110, 0x6108bc },
139		{ 0x0114, 0x61088c },
140		{}
141	}
142};
143
144const struct nv50_disp_mthd_chan
145g84_disp_base_mthd_chan = {
146	.name = "Base",
147	.addr = 0x000540,
148	.data = {
149		{ "Global", 1, &g84_disp_base_mthd_base },
150		{  "Image", 2, &nv50_disp_base_mthd_image },
151		{}
152	}
153};
154
155/*******************************************************************************
156 * EVO overlay channel objects
157 ******************************************************************************/
158
159static const struct nv50_disp_mthd_list
160g84_disp_ovly_mthd_base = {
161	.mthd = 0x0000,
162	.addr = 0x000000,
163	.data = {
164		{ 0x0080, 0x000000 },
165		{ 0x0084, 0x6109a0 },
166		{ 0x0088, 0x6109c0 },
167		{ 0x008c, 0x6109c8 },
168		{ 0x0090, 0x6109b4 },
169		{ 0x0094, 0x610970 },
170		{ 0x00a0, 0x610998 },
171		{ 0x00a4, 0x610964 },
172		{ 0x00c0, 0x610958 },
173		{ 0x00e0, 0x6109a8 },
174		{ 0x00e4, 0x6109d0 },
175		{ 0x00e8, 0x6109d8 },
176		{ 0x0100, 0x61094c },
177		{ 0x0104, 0x610984 },
178		{ 0x0108, 0x61098c },
179		{ 0x0800, 0x6109f8 },
180		{ 0x0808, 0x610a08 },
181		{ 0x080c, 0x610a10 },
182		{ 0x0810, 0x610a00 },
183		{}
184	}
185};
186
187const struct nv50_disp_mthd_chan
188g84_disp_ovly_mthd_chan = {
189	.name = "Overlay",
190	.addr = 0x000540,
191	.data = {
192		{ "Global", 1, &g84_disp_ovly_mthd_base },
193		{}
194	}
195};
196
197/*******************************************************************************
198 * Base display object
199 ******************************************************************************/
200
201static struct nvkm_oclass
202g84_disp_sclass[] = {
203	{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
204	{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
205	{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
206	{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
207	{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
208	{}
209};
210
211static struct nvkm_oclass
212g84_disp_main_oclass[] = {
213	{ G82_DISP, &nv50_disp_main_ofuncs },
214	{}
215};
216
217/*******************************************************************************
218 * Display engine implementation
219 ******************************************************************************/
220
221static int
222g84_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
223	      struct nvkm_oclass *oclass, void *data, u32 size,
224	      struct nvkm_object **pobject)
225{
226	struct nv50_disp_priv *priv;
227	int ret;
228
229	ret = nvkm_disp_create(parent, engine, oclass, 2, "PDISP",
230			       "display", &priv);
231	*pobject = nv_object(priv);
232	if (ret)
233		return ret;
234
235	ret = nvkm_event_init(&nv50_disp_chan_uevent, 1, 9, &priv->uevent);
236	if (ret)
237		return ret;
238
239	nv_engine(priv)->sclass = g84_disp_main_oclass;
240	nv_engine(priv)->cclass = &nv50_disp_cclass;
241	nv_subdev(priv)->intr = nv50_disp_intr;
242	INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
243	priv->sclass = g84_disp_sclass;
244	priv->head.nr = 2;
245	priv->dac.nr = 3;
246	priv->sor.nr = 2;
247	priv->pior.nr = 3;
248	priv->dac.power = nv50_dac_power;
249	priv->dac.sense = nv50_dac_sense;
250	priv->sor.power = nv50_sor_power;
251	priv->sor.hdmi = g84_hdmi_ctrl;
252	priv->pior.power = nv50_pior_power;
253	return 0;
254}
255
256struct nvkm_oclass *
257g84_disp_oclass = &(struct nv50_disp_impl) {
258	.base.base.handle = NV_ENGINE(DISP, 0x82),
259	.base.base.ofuncs = &(struct nvkm_ofuncs) {
260		.ctor = g84_disp_ctor,
261		.dtor = _nvkm_disp_dtor,
262		.init = _nvkm_disp_init,
263		.fini = _nvkm_disp_fini,
264	},
265	.base.vblank = &nv50_disp_vblank_func,
266	.base.outp =  nv50_disp_outp_sclass,
267	.mthd.core = &g84_disp_core_mthd_chan,
268	.mthd.base = &g84_disp_base_mthd_chan,
269	.mthd.ovly = &g84_disp_ovly_mthd_chan,
270	.mthd.prev = 0x000004,
271	.head.scanoutpos = nv50_disp_main_scanoutpos,
272}.base.base;
273