212 	void __iomem *base;  member
267 	writel_relaxed(BIT_MODE_CHANGE_EN, priv->base + MODE_CHANGE_EN);  in hix5hd2_config_port()
274 	writel_relaxed(val, priv->base + PORT_MODE);  in hix5hd2_config_port()
275 	writel_relaxed(0, priv->base + MODE_CHANGE_EN);  in hix5hd2_config_port()
276 	writel_relaxed(duplex, priv->base + MAC_DUPLEX_HALF_CTRL);  in hix5hd2_config_port()
281 	writel_relaxed(BITS_RX_FQ_DEPTH_EN, priv->base + RX_FQ_REG_EN);  in hix5hd2_set_desc_depth()
282 	writel_relaxed(rx << 3, priv->base + RX_FQ_DEPTH);  in hix5hd2_set_desc_depth()
283 	writel_relaxed(0, priv->base + RX_FQ_REG_EN);  in hix5hd2_set_desc_depth()
285 	writel_relaxed(BITS_RX_BQ_DEPTH_EN, priv->base + RX_BQ_REG_EN);  in hix5hd2_set_desc_depth()
286 	writel_relaxed(rx << 3, priv->base + RX_BQ_DEPTH);  in hix5hd2_set_desc_depth()
287 	writel_relaxed(0, priv->base + RX_BQ_REG_EN);  in hix5hd2_set_desc_depth()
289 	writel_relaxed(BITS_TX_BQ_DEPTH_EN, priv->base + TX_BQ_REG_EN);  in hix5hd2_set_desc_depth()
290 	writel_relaxed(tx << 3, priv->base + TX_BQ_DEPTH);  in hix5hd2_set_desc_depth()
291 	writel_relaxed(0, priv->base + TX_BQ_REG_EN);  in hix5hd2_set_desc_depth()
293 	writel_relaxed(BITS_TX_RQ_DEPTH_EN, priv->base + TX_RQ_REG_EN);  in hix5hd2_set_desc_depth()
294 	writel_relaxed(tx << 3, priv->base + TX_RQ_DEPTH);  in hix5hd2_set_desc_depth()
295 	writel_relaxed(0, priv->base + TX_RQ_REG_EN);  in hix5hd2_set_desc_depth()
300 	writel_relaxed(BITS_RX_FQ_START_ADDR_EN, priv->base + RX_FQ_REG_EN);  in hix5hd2_set_rx_fq()
301 	writel_relaxed(phy_addr, priv->base + RX_FQ_START_ADDR);  in hix5hd2_set_rx_fq()
302 	writel_relaxed(0, priv->base + RX_FQ_REG_EN);  in hix5hd2_set_rx_fq()
307 	writel_relaxed(BITS_RX_BQ_START_ADDR_EN, priv->base + RX_BQ_REG_EN);  in hix5hd2_set_rx_bq()
308 	writel_relaxed(phy_addr, priv->base + RX_BQ_START_ADDR);  in hix5hd2_set_rx_bq()
309 	writel_relaxed(0, priv->base + RX_BQ_REG_EN);  in hix5hd2_set_rx_bq()
314 	writel_relaxed(BITS_TX_BQ_START_ADDR_EN, priv->base + TX_BQ_REG_EN);  in hix5hd2_set_tx_bq()
315 	writel_relaxed(phy_addr, priv->base + TX_BQ_START_ADDR);  in hix5hd2_set_tx_bq()
316 	writel_relaxed(0, priv->base + TX_BQ_REG_EN);  in hix5hd2_set_tx_bq()
321 	writel_relaxed(BITS_TX_RQ_START_ADDR_EN, priv->base + TX_RQ_REG_EN);  in hix5hd2_set_tx_rq()
322 	writel_relaxed(phy_addr, priv->base + TX_RQ_START_ADDR);  in hix5hd2_set_tx_rq()
323 	writel_relaxed(0, priv->base + TX_RQ_REG_EN);  in hix5hd2_set_tx_rq()
339 	writel_relaxed(0, priv->base + ENA_PMU_INT);  in hix5hd2_hw_init()
340 	writel_relaxed(~0, priv->base + RAW_PMU_INT);  in hix5hd2_hw_init()
342 	writel_relaxed(BIT_CRC_ERR_PASS, priv->base + REC_FILT_CONTROL);  in hix5hd2_hw_init()
343 	writel_relaxed(MAC_MAX_FRAME_SIZE, priv->base + CONTROL_WORD);  in hix5hd2_hw_init()
344 	writel_relaxed(0, priv->base + COL_SLOT_TIME);  in hix5hd2_hw_init()
347 	writel_relaxed(val, priv->base + IN_QUEUE_TH);  in hix5hd2_hw_init()
349 	writel_relaxed(RX_BQ_IN_TIMEOUT, priv->base + RX_BQ_IN_TIMEOUT_TH);  in hix5hd2_hw_init()
350 	writel_relaxed(TX_RQ_IN_TIMEOUT, priv->base + TX_RQ_IN_TIMEOUT_TH);  in hix5hd2_hw_init()
358 	writel_relaxed(DEF_INT_MASK, priv->base + ENA_PMU_INT);  in hix5hd2_irq_enable()
363 	writel_relaxed(0, priv->base + ENA_PMU_INT);  in hix5hd2_irq_disable()
368 	writel_relaxed(0xf, priv->base + DESC_WR_RD_ENA);  in hix5hd2_port_enable()
369 	writel_relaxed(BITS_RX_EN | BITS_TX_EN, priv->base + PORT_EN);  in hix5hd2_port_enable()
374 	writel_relaxed(~(BITS_RX_EN | BITS_TX_EN), priv->base + PORT_EN);  in hix5hd2_port_disable()
375 	writel_relaxed(0, priv->base + DESC_WR_RD_ENA);  in hix5hd2_port_disable()
385 	writel_relaxed(val, priv->base + STATION_ADDR_HIGH);  in hix5hd2_hw_set_mac_addr()
388 	writel_relaxed(val, priv->base + STATION_ADDR_LOW);  in hix5hd2_hw_set_mac_addr()
422 	start = dma_cnt(readl_relaxed(priv->base + RX_FQ_WR_ADDR));  in hix5hd2_rx_refill()
424 	end = dma_cnt(readl_relaxed(priv->base + RX_FQ_RD_ADDR));  in hix5hd2_rx_refill()
454 		writel_relaxed(dma_byte(pos), priv->base + RX_FQ_WR_ADDR);  in hix5hd2_rx_refill()
466 	start = dma_cnt(readl_relaxed(priv->base + RX_BQ_RD_ADDR));  in hix5hd2_rx()
468 	end = dma_cnt(readl_relaxed(priv->base + RX_BQ_WR_ADDR));  in hix5hd2_rx()
509 		writel_relaxed(dma_byte(pos), priv->base + RX_BQ_RD_ADDR);  in hix5hd2_rx()
528 	start = dma_cnt(readl_relaxed(priv->base + TX_RQ_RD_ADDR));  in hix5hd2_xmit_reclaim()
530 	end = dma_cnt(readl_relaxed(priv->base + TX_RQ_WR_ADDR));  in hix5hd2_xmit_reclaim()
551 		writel_relaxed(dma_byte(pos), priv->base + TX_RQ_RD_ADDR);  in hix5hd2_xmit_reclaim()
578 		ints = readl_relaxed(priv->base + RAW_PMU_INT);  in hix5hd2_poll()
579 		writel_relaxed(ints, priv->base + RAW_PMU_INT);  in hix5hd2_poll()
594 	int ints = readl_relaxed(priv->base + RAW_PMU_INT);  in hix5hd2_interrupt()
596 	writel_relaxed(ints, priv->base + RAW_PMU_INT);  in hix5hd2_interrupt()
613 	pos = dma_cnt(readl_relaxed(priv->base + TX_BQ_WR_ADDR));  in hix5hd2_net_xmit()
638 	writel_relaxed(dma_byte(pos), priv->base + TX_BQ_WR_ADDR);  in hix5hd2_net_xmit()
785 	void __iomem *base = priv->base;  in hix5hd2_mdio_wait_ready()  local
788 	for (i = 0; readl_relaxed(base + MDIO_SINGLE_CMD) & MDIO_START; i++) {  in hix5hd2_mdio_wait_ready()
800 	void __iomem *base = priv->base;  in hix5hd2_mdio_read()  local
807 	writel_relaxed(MDIO_READ | phy << 8 | reg, base + MDIO_SINGLE_CMD);  in hix5hd2_mdio_read()
812 	val = readl_relaxed(base + MDIO_RDATA_STATUS);  in hix5hd2_mdio_read()
819 	val = readl_relaxed(priv->base + MDIO_SINGLE_DATA);  in hix5hd2_mdio_read()
828 	void __iomem *base = priv->base;  in hix5hd2_mdio_write()  local
835 	writel_relaxed(val, base + MDIO_SINGLE_DATA);  in hix5hd2_mdio_write()
836 	writel_relaxed(MDIO_WRITE | phy << 8 | reg, base + MDIO_SINGLE_CMD);  in hix5hd2_mdio_write()
910 	priv->base = devm_ioremap_resource(dev, res);  in hix5hd2_dev_probe()
911 	if (IS_ERR(priv->base)) {  in hix5hd2_dev_probe()
912 		ret = PTR_ERR(priv->base);  in hix5hd2_dev_probe()