76 	void __iomem 		*base;		/* IO Memory base address */  member
87 	void __iomem *base = priv->base;  in vt8500_irq_mask()  local
88 	void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4);  in vt8500_irq_mask()
92 	edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE;  in vt8500_irq_mask()
99 		dctr = readb(base + VT8500_ICDC + d->hwirq);  in vt8500_irq_mask()
101 		writeb(dctr, base + VT8500_ICDC + d->hwirq);  in vt8500_irq_mask()
108 	void __iomem *base = priv->base;  in vt8500_irq_unmask()  local
111 	dctr = readb(base + VT8500_ICDC + d->hwirq);  in vt8500_irq_unmask()
113 	writeb(dctr, base + VT8500_ICDC + d->hwirq);  in vt8500_irq_unmask()
119 	void __iomem *base = priv->base;  in vt8500_irq_set_type()  local
122 	dctr = readb(base + VT8500_ICDC + d->hwirq);  in vt8500_irq_set_type()
141 	writeb(dctr, base + VT8500_ICDC + d->hwirq);  in vt8500_irq_set_type()
154 static void __init vt8500_init_irq_hw(void __iomem *base)  in vt8500_init_irq_hw()  argument
159 	writel(ICPC_ROTATE, base + VT8500_ICPC_IRQ);  in vt8500_init_irq_hw()
160 	writel(0x00, base + VT8500_ICPC_FIQ);  in vt8500_init_irq_hw()
164 		writeb(VT8500_INT_DISABLE | ICDC_IRQ, base + VT8500_ICDC + i);  in vt8500_init_irq_hw()
185 	void __iomem *base;  in vt8500_handle_irq()  local
189 		base = intc[i].base;  in vt8500_handle_irq()
190 		irqnr = readl_relaxed(base) & 0x3F;  in vt8500_handle_irq()
196 			stat = readl_relaxed(base + VT8500_ICIS + 4);  in vt8500_handle_irq()
217 	intc[active_cnt].base = of_iomap(np, 0);  in vt8500_irq_init()
221 	if (!intc[active_cnt].base) {  in vt8500_irq_init()
233 	vt8500_init_irq_hw(intc[active_cnt].base);  in vt8500_irq_init()