1/*
2 * Copyright 2013 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24#include "nv50.h"
25
26struct mcp77_ram_priv {
27	struct nvkm_ram base;
28	u64 poller_base;
29};
30
31static int
32mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
33	       struct nvkm_oclass *oclass, void *data, u32 datasize,
34	       struct nvkm_object **pobject)
35{
36	u32 rsvd_head = ( 256 * 1024); /* vga memory */
37	u32 rsvd_tail = (1024 * 1024); /* vbios etc */
38	struct nvkm_fb *pfb = nvkm_fb(parent);
39	struct mcp77_ram_priv *priv;
40	int ret;
41
42	ret = nvkm_ram_create(parent, engine, oclass, &priv);
43	*pobject = nv_object(priv);
44	if (ret)
45		return ret;
46
47	priv->base.type   = NV_MEM_TYPE_STOLEN;
48	priv->base.stolen = (u64)nv_rd32(pfb, 0x100e10) << 12;
49	priv->base.size   = (u64)nv_rd32(pfb, 0x100e14) << 12;
50
51	rsvd_tail += 0x1000;
52	priv->poller_base = priv->base.size - rsvd_tail;
53
54	ret = nvkm_mm_init(&pfb->vram, rsvd_head >> 12,
55			   (priv->base.size  - (rsvd_head + rsvd_tail)) >> 12,
56			   1);
57	if (ret)
58		return ret;
59
60	priv->base.get = nv50_ram_get;
61	priv->base.put = nv50_ram_put;
62	return 0;
63}
64
65static int
66mcp77_ram_init(struct nvkm_object *object)
67{
68	struct nvkm_fb *pfb = nvkm_fb(object);
69	struct mcp77_ram_priv *priv = (void *)object;
70	int ret;
71	u64 dniso, hostnb, flush;
72
73	ret = nvkm_ram_init(&priv->base);
74	if (ret)
75		return ret;
76
77	dniso  = ((priv->base.size - (priv->poller_base + 0x00)) >> 5) - 1;
78	hostnb = ((priv->base.size - (priv->poller_base + 0x20)) >> 5) - 1;
79	flush  = ((priv->base.size - (priv->poller_base + 0x40)) >> 5) - 1;
80
81	/* Enable NISO poller for various clients and set their associated
82	 * read address, only for MCP77/78 and MCP79/7A. (fd#25701)
83	 */
84	nv_wr32(pfb, 0x100c18, dniso);
85	nv_mask(pfb, 0x100c14, 0x00000000, 0x00000001);
86	nv_wr32(pfb, 0x100c1c, hostnb);
87	nv_mask(pfb, 0x100c14, 0x00000000, 0x00000002);
88	nv_wr32(pfb, 0x100c24, flush);
89	nv_mask(pfb, 0x100c14, 0x00000000, 0x00010000);
90	return 0;
91}
92
93struct nvkm_oclass
94mcp77_ram_oclass = {
95	.ofuncs = &(struct nvkm_ofuncs) {
96		.ctor = mcp77_ram_ctor,
97		.dtor = _nvkm_ram_dtor,
98		.init = mcp77_ram_init,
99		.fini = _nvkm_ram_fini,
100	},
101};
102