1/*
2 * TX4939 internal IDE driver
3 * Based on RBTX49xx patch from CELF patch archive.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License.  See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * (C) Copyright TOSHIBA CORPORATION 2005-2007
10 */
11
12#include <linux/module.h>
13#include <linux/types.h>
14#include <linux/ide.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/platform_device.h>
18#include <linux/io.h>
19#include <linux/scatterlist.h>
20
21#include <asm/ide.h>
22
23#define MODNAME	"tx4939ide"
24
25/* ATA Shadow Registers (8-bit except for Data which is 16-bit) */
26#define TX4939IDE_Data			0x000
27#define TX4939IDE_Error_Feature		0x001
28#define TX4939IDE_Sec			0x002
29#define TX4939IDE_LBA0			0x003
30#define TX4939IDE_LBA1			0x004
31#define TX4939IDE_LBA2			0x005
32#define TX4939IDE_DevHead		0x006
33#define TX4939IDE_Stat_Cmd		0x007
34#define TX4939IDE_AltStat_DevCtl	0x402
35/* H/W DMA Registers  */
36#define TX4939IDE_DMA_Cmd	0x800	/* 8-bit */
37#define TX4939IDE_DMA_Stat	0x802	/* 8-bit */
38#define TX4939IDE_PRD_Ptr	0x804	/* 32-bit */
39/* ATA100 CORE Registers (16-bit) */
40#define TX4939IDE_Sys_Ctl	0xc00
41#define TX4939IDE_Xfer_Cnt_1	0xc08
42#define TX4939IDE_Xfer_Cnt_2	0xc0a
43#define TX4939IDE_Sec_Cnt	0xc10
44#define TX4939IDE_Start_Lo_Addr	0xc18
45#define TX4939IDE_Start_Up_Addr	0xc20
46#define TX4939IDE_Add_Ctl	0xc28
47#define TX4939IDE_Lo_Burst_Cnt	0xc30
48#define TX4939IDE_Up_Burst_Cnt	0xc38
49#define TX4939IDE_PIO_Addr	0xc88
50#define TX4939IDE_H_Rst_Tim	0xc90
51#define TX4939IDE_Int_Ctl	0xc98
52#define TX4939IDE_Pkt_Cmd	0xcb8
53#define TX4939IDE_Bxfer_Cnt_Hi	0xcc0
54#define TX4939IDE_Bxfer_Cnt_Lo	0xcc8
55#define TX4939IDE_Dev_TErr	0xcd0
56#define TX4939IDE_Pkt_Xfer_Ctl	0xcd8
57#define TX4939IDE_Start_TAddr	0xce0
58
59/* bits for Int_Ctl */
60#define TX4939IDE_INT_ADDRERR	0x80
61#define TX4939IDE_INT_REACHMUL	0x40
62#define TX4939IDE_INT_DEVTIMING	0x20
63#define TX4939IDE_INT_UDMATERM	0x10
64#define TX4939IDE_INT_TIMER	0x08
65#define TX4939IDE_INT_BUSERR	0x04
66#define TX4939IDE_INT_XFEREND	0x02
67#define TX4939IDE_INT_HOST	0x01
68
69#define TX4939IDE_IGNORE_INTS	\
70	(TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
71	 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
72	 TX4939IDE_INT_TIMER | TX4939IDE_INT_XFEREND)
73
74#ifdef __BIG_ENDIAN
75#define tx4939ide_swizzlel(a)	((a) ^ 4)
76#define tx4939ide_swizzlew(a)	((a) ^ 6)
77#define tx4939ide_swizzleb(a)	((a) ^ 7)
78#else
79#define tx4939ide_swizzlel(a)	(a)
80#define tx4939ide_swizzlew(a)	(a)
81#define tx4939ide_swizzleb(a)	(a)
82#endif
83
84static u16 tx4939ide_readw(void __iomem *base, u32 reg)
85{
86	return __raw_readw(base + tx4939ide_swizzlew(reg));
87}
88static u8 tx4939ide_readb(void __iomem *base, u32 reg)
89{
90	return __raw_readb(base + tx4939ide_swizzleb(reg));
91}
92static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
93{
94	__raw_writel(val, base + tx4939ide_swizzlel(reg));
95}
96static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
97{
98	__raw_writew(val, base + tx4939ide_swizzlew(reg));
99}
100static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
101{
102	__raw_writeb(val, base + tx4939ide_swizzleb(reg));
103}
104
105#define TX4939IDE_BASE(hwif)	((void __iomem *)(hwif)->extra_base)
106
107static void tx4939ide_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
108{
109	int is_slave = drive->dn;
110	u32 mask, val;
111	const u8 pio = drive->pio_mode - XFER_PIO_0;
112	u8 safe = pio;
113	ide_drive_t *pair;
114
115	pair = ide_get_pair_dev(drive);
116	if (pair)
117		safe = min_t(u8, safe, pair->pio_mode - XFER_PIO_0);
118	/*
119	 * Update Command Transfer Mode for master/slave and Data
120	 * Transfer Mode for this drive.
121	 */
122	mask = is_slave ? 0x07f00000 : 0x000007f0;
123	val = ((safe << 8) | (pio << 4)) << (is_slave ? 16 : 0);
124	hwif->select_data = (hwif->select_data & ~mask) | val;
125	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
126}
127
128static void tx4939ide_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
129{
130	u32 mask, val;
131	const u8 mode = drive->dma_mode;
132
133	/* Update Data Transfer Mode for this drive. */
134	if (mode >= XFER_UDMA_0)
135		val = mode - XFER_UDMA_0 + 8;
136	else
137		val = mode - XFER_MW_DMA_0 + 5;
138	if (drive->dn) {
139		mask = 0x00f00000;
140		val <<= 20;
141	} else {
142		mask = 0x000000f0;
143		val <<= 4;
144	}
145	hwif->select_data = (hwif->select_data & ~mask) | val;
146	/* tx4939ide_tf_load_fixup() will set the Sys_Ctl register */
147}
148
149static u16 tx4939ide_check_error_ints(ide_hwif_t *hwif)
150{
151	void __iomem *base = TX4939IDE_BASE(hwif);
152	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
153
154	if (ctl & TX4939IDE_INT_BUSERR) {
155		/* reset FIFO */
156		u16 sysctl = tx4939ide_readw(base, TX4939IDE_Sys_Ctl);
157
158		tx4939ide_writew(sysctl | 0x4000, base, TX4939IDE_Sys_Ctl);
159		mmiowb();
160		/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz, max 270ns) */
161		ndelay(270);
162		tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
163	}
164	if (ctl & (TX4939IDE_INT_ADDRERR |
165		   TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
166		pr_err("%s: Error interrupt %#x (%s%s%s )\n",
167		       hwif->name, ctl,
168		       ctl & TX4939IDE_INT_ADDRERR ? " Address-Error" : "",
169		       ctl & TX4939IDE_INT_DEVTIMING ? " DEV-Timing" : "",
170		       ctl & TX4939IDE_INT_BUSERR ? " Bus-Error" : "");
171	return ctl;
172}
173
174static void tx4939ide_clear_irq(ide_drive_t *drive)
175{
176	ide_hwif_t *hwif;
177	void __iomem *base;
178	u16 ctl;
179
180	/*
181	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all job
182	 * for DMA case.
183	 */
184	if (drive->waiting_for_dma)
185		return;
186	hwif = drive->hwif;
187	base = TX4939IDE_BASE(hwif);
188	ctl = tx4939ide_check_error_ints(hwif);
189	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
190}
191
192static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
193{
194	void __iomem *base = TX4939IDE_BASE(hwif);
195
196	return tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000 ?
197		ATA_CBL_PATA40 : ATA_CBL_PATA80;
198}
199
200#ifdef __BIG_ENDIAN
201static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
202{
203	ide_hwif_t *hwif = drive->hwif;
204	u8 unit = drive->dn;
205	void __iomem *base = TX4939IDE_BASE(hwif);
206	u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
207
208	if (on)
209		dma_stat |= (1 << (5 + unit));
210	else
211		dma_stat &= ~(1 << (5 + unit));
212
213	tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_Stat);
214}
215#else
216#define tx4939ide_dma_host_set	ide_dma_host_set
217#endif
218
219static u8 tx4939ide_clear_dma_status(void __iomem *base)
220{
221	u8 dma_stat;
222
223	/* read DMA status for INTR & ERROR flags */
224	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
225	/* clear INTR & ERROR flags */
226	tx4939ide_writeb(dma_stat | ATA_DMA_INTR | ATA_DMA_ERR, base,
227			 TX4939IDE_DMA_Stat);
228	/* recover intmask cleared by writing to bit2 of DMA_Stat */
229	tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_Int_Ctl);
230	return dma_stat;
231}
232
233#ifdef __BIG_ENDIAN
234/* custom ide_build_dmatable to handle swapped layout */
235static int tx4939ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
236{
237	ide_hwif_t *hwif = drive->hwif;
238	u32 *table = (u32 *)hwif->dmatable_cpu;
239	unsigned int count = 0;
240	int i;
241	struct scatterlist *sg;
242
243	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
244		u32 cur_addr, cur_len, bcount;
245
246		cur_addr = sg_dma_address(sg);
247		cur_len = sg_dma_len(sg);
248
249		/*
250		 * Fill in the DMA table, without crossing any 64kB boundaries.
251		 */
252
253		while (cur_len) {
254			if (count++ >= PRD_ENTRIES)
255				goto use_pio_instead;
256
257			bcount = 0x10000 - (cur_addr & 0xffff);
258			if (bcount > cur_len)
259				bcount = cur_len;
260			/*
261			 * This workaround for zero count seems required.
262			 * (standard ide_build_dmatable does it too)
263			 */
264			if (bcount == 0x10000)
265				bcount = 0x8000;
266			*table++ = bcount & 0xffff;
267			*table++ = cur_addr;
268			cur_addr += bcount;
269			cur_len -= bcount;
270		}
271	}
272
273	if (count) {
274		*(table - 2) |= 0x80000000;
275		return count;
276	}
277
278use_pio_instead:
279	printk(KERN_ERR "%s: %s\n", drive->name,
280		count ? "DMA table too small" : "empty DMA table?");
281
282	return 0; /* revert to PIO for this request */
283}
284#else
285#define tx4939ide_build_dmatable	ide_build_dmatable
286#endif
287
288static int tx4939ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
289{
290	ide_hwif_t *hwif = drive->hwif;
291	void __iomem *base = TX4939IDE_BASE(hwif);
292	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
293
294	/* fall back to PIO! */
295	if (tx4939ide_build_dmatable(drive, cmd) == 0)
296		return 1;
297
298	/* PRD table */
299	tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
300
301	/* specify r/w */
302	tx4939ide_writeb(rw, base, TX4939IDE_DMA_Cmd);
303
304	/* clear INTR & ERROR flags */
305	tx4939ide_clear_dma_status(base);
306
307	tx4939ide_writew(SECTOR_SIZE / 2, base, drive->dn ?
308			 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
309
310	tx4939ide_writew(blk_rq_sectors(cmd->rq), base, TX4939IDE_Sec_Cnt);
311
312	return 0;
313}
314
315static int tx4939ide_dma_end(ide_drive_t *drive)
316{
317	ide_hwif_t *hwif = drive->hwif;
318	u8 dma_stat, dma_cmd;
319	void __iomem *base = TX4939IDE_BASE(hwif);
320	u16 ctl = tx4939ide_readw(base, TX4939IDE_Int_Ctl);
321
322	/* get DMA command mode */
323	dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
324	/* stop DMA */
325	tx4939ide_writeb(dma_cmd & ~ATA_DMA_START, base, TX4939IDE_DMA_Cmd);
326
327	/* read and clear the INTR & ERROR bits */
328	dma_stat = tx4939ide_clear_dma_status(base);
329
330#define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)
331
332	/* verify good DMA status */
333	if ((dma_stat & CHECK_DMA_MASK) == 0 &&
334	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
335	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
336		/* INT_IDE lost... bug? */
337		return 0;
338	return ((dma_stat & CHECK_DMA_MASK) !=
339		ATA_DMA_INTR) ? 0x10 | dma_stat : 0;
340}
341
342/* returns 1 if DMA IRQ issued, 0 otherwise */
343static int tx4939ide_dma_test_irq(ide_drive_t *drive)
344{
345	ide_hwif_t *hwif = drive->hwif;
346	void __iomem *base = TX4939IDE_BASE(hwif);
347	u16 ctl, ide_int;
348	u8 dma_stat, stat;
349	int found = 0;
350
351	ctl = tx4939ide_check_error_ints(hwif);
352	ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
353	switch (ide_int) {
354	case TX4939IDE_INT_HOST:
355		/* On error, XFEREND might not be asserted. */
356		stat = tx4939ide_readb(base, TX4939IDE_AltStat_DevCtl);
357		if ((stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) == ATA_ERR)
358			found = 1;
359		else
360			/* Wait for XFEREND (Mask HOST and unmask XFEREND) */
361			ctl &= ~TX4939IDE_INT_XFEREND << 8;
362		ctl |= ide_int << 8;
363		break;
364	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
365		dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_Stat);
366		if (!(dma_stat & ATA_DMA_INTR))
367			pr_warning("%s: weird interrupt status. "
368				   "DMA_Stat %#02x int_ctl %#04x\n",
369				   hwif->name, dma_stat, ctl);
370		found = 1;
371		break;
372	}
373	/*
374	 * Do not clear XFEREND, HOST now.  They will be cleared by
375	 * clearing bit2 of DMA_Stat.
376	 */
377	ctl &= ~ide_int;
378	tx4939ide_writew(ctl, base, TX4939IDE_Int_Ctl);
379	return found;
380}
381
382#ifdef __BIG_ENDIAN
383static u8 tx4939ide_dma_sff_read_status(ide_hwif_t *hwif)
384{
385	void __iomem *base = TX4939IDE_BASE(hwif);
386
387	return tx4939ide_readb(base, TX4939IDE_DMA_Stat);
388}
389#else
390#define tx4939ide_dma_sff_read_status ide_dma_sff_read_status
391#endif
392
393static void tx4939ide_init_hwif(ide_hwif_t *hwif)
394{
395	void __iomem *base = TX4939IDE_BASE(hwif);
396
397	/* Soft Reset */
398	tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
399	mmiowb();
400	/* at least 20 GBUSCLK (typ. 100ns @ GBUS200MHz, max 450ns) */
401	ndelay(450);
402	tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
403	/* mask some interrupts and clear all interrupts */
404	tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
405			 TX4939IDE_Int_Ctl);
406
407	tx4939ide_writew(0x0008, base, TX4939IDE_Lo_Burst_Cnt);
408	tx4939ide_writew(0, base, TX4939IDE_Up_Burst_Cnt);
409}
410
411static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
412{
413	hwif->dma_base =
414		hwif->extra_base + tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
415	/*
416	 * Note that we cannot use ATA_DMA_TABLE_OFS, ATA_DMA_STATUS
417	 * for big endian.
418	 */
419	return ide_allocate_dma_engine(hwif);
420}
421
422static void tx4939ide_tf_load_fixup(ide_drive_t *drive)
423{
424	ide_hwif_t *hwif = drive->hwif;
425	void __iomem *base = TX4939IDE_BASE(hwif);
426	u16 sysctl = hwif->select_data >> (drive->dn ? 16 : 0);
427
428	/*
429	 * Fix ATA100 CORE System Control Register. (The write to the
430	 * Device/Head register may write wrong data to the System
431	 * Control Register)
432	 * While Sys_Ctl is written here, dev_select() is not needed.
433	 */
434	tx4939ide_writew(sysctl, base, TX4939IDE_Sys_Ctl);
435}
436
437static void tx4939ide_tf_load(ide_drive_t *drive, struct ide_taskfile *tf,
438			      u8 valid)
439{
440	ide_tf_load(drive, tf, valid);
441
442	if (valid & IDE_VALID_DEVICE)
443		tx4939ide_tf_load_fixup(drive);
444}
445
446#ifdef __BIG_ENDIAN
447
448/* custom iops (independent from SWAP_IO_SPACE) */
449static void tx4939ide_input_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
450				void *buf, unsigned int len)
451{
452	unsigned long port = drive->hwif->io_ports.data_addr;
453	unsigned short *ptr = buf;
454	unsigned int count = (len + 1) / 2;
455
456	while (count--)
457		*ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
458	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
459}
460
461static void tx4939ide_output_data_swap(ide_drive_t *drive, struct ide_cmd *cmd,
462				void *buf, unsigned int len)
463{
464	unsigned long port = drive->hwif->io_ports.data_addr;
465	unsigned short *ptr = buf;
466	unsigned int count = (len + 1) / 2;
467
468	while (count--) {
469		__raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
470		ptr++;
471	}
472	__ide_flush_dcache_range((unsigned long)buf, roundup(len, 2));
473}
474
475static const struct ide_tp_ops tx4939ide_tp_ops = {
476	.exec_command		= ide_exec_command,
477	.read_status		= ide_read_status,
478	.read_altstatus		= ide_read_altstatus,
479	.write_devctl		= ide_write_devctl,
480
481	.dev_select		= ide_dev_select,
482	.tf_load		= tx4939ide_tf_load,
483	.tf_read		= ide_tf_read,
484
485	.input_data		= tx4939ide_input_data_swap,
486	.output_data		= tx4939ide_output_data_swap,
487};
488
489#else	/* __LITTLE_ENDIAN */
490
491static const struct ide_tp_ops tx4939ide_tp_ops = {
492	.exec_command		= ide_exec_command,
493	.read_status		= ide_read_status,
494	.read_altstatus		= ide_read_altstatus,
495	.write_devctl		= ide_write_devctl,
496
497	.dev_select		= ide_dev_select,
498	.tf_load		= tx4939ide_tf_load,
499	.tf_read		= ide_tf_read,
500
501	.input_data		= ide_input_data,
502	.output_data		= ide_output_data,
503};
504
505#endif	/* __LITTLE_ENDIAN */
506
507static const struct ide_port_ops tx4939ide_port_ops = {
508	.set_pio_mode		= tx4939ide_set_pio_mode,
509	.set_dma_mode		= tx4939ide_set_dma_mode,
510	.clear_irq		= tx4939ide_clear_irq,
511	.cable_detect		= tx4939ide_cable_detect,
512};
513
514static const struct ide_dma_ops tx4939ide_dma_ops = {
515	.dma_host_set		= tx4939ide_dma_host_set,
516	.dma_setup		= tx4939ide_dma_setup,
517	.dma_start		= ide_dma_start,
518	.dma_end		= tx4939ide_dma_end,
519	.dma_test_irq		= tx4939ide_dma_test_irq,
520	.dma_lost_irq		= ide_dma_lost_irq,
521	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
522	.dma_sff_read_status	= tx4939ide_dma_sff_read_status,
523};
524
525static const struct ide_port_info tx4939ide_port_info __initconst = {
526	.init_hwif		= tx4939ide_init_hwif,
527	.init_dma		= tx4939ide_init_dma,
528	.port_ops		= &tx4939ide_port_ops,
529	.dma_ops		= &tx4939ide_dma_ops,
530	.tp_ops			= &tx4939ide_tp_ops,
531	.host_flags		= IDE_HFLAG_MMIO,
532	.pio_mask		= ATA_PIO4,
533	.mwdma_mask		= ATA_MWDMA2,
534	.udma_mask		= ATA_UDMA5,
535	.chipset		= ide_generic,
536};
537
538static int __init tx4939ide_probe(struct platform_device *pdev)
539{
540	struct ide_hw hw, *hws[] = { &hw };
541	struct ide_host *host;
542	struct resource *res;
543	int irq, ret;
544	unsigned long mapbase;
545
546	irq = platform_get_irq(pdev, 0);
547	if (irq < 0)
548		return -ENODEV;
549	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
550	if (!res)
551		return -ENODEV;
552
553	if (!devm_request_mem_region(&pdev->dev, res->start,
554				     resource_size(res), "tx4938ide"))
555		return -EBUSY;
556	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
557					      resource_size(res));
558	if (!mapbase)
559		return -EBUSY;
560	memset(&hw, 0, sizeof(hw));
561	hw.io_ports.data_addr =
562		mapbase + tx4939ide_swizzlew(TX4939IDE_Data);
563	hw.io_ports.error_addr =
564		mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Feature);
565	hw.io_ports.nsect_addr =
566		mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
567	hw.io_ports.lbal_addr =
568		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
569	hw.io_ports.lbam_addr =
570		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
571	hw.io_ports.lbah_addr =
572		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
573	hw.io_ports.device_addr =
574		mapbase + tx4939ide_swizzleb(TX4939IDE_DevHead);
575	hw.io_ports.command_addr =
576		mapbase + tx4939ide_swizzleb(TX4939IDE_Stat_Cmd);
577	hw.io_ports.ctl_addr =
578		mapbase + tx4939ide_swizzleb(TX4939IDE_AltStat_DevCtl);
579	hw.irq = irq;
580	hw.dev = &pdev->dev;
581
582	pr_info("TX4939 IDE interface (base %#lx, irq %d)\n", mapbase, irq);
583	host = ide_host_alloc(&tx4939ide_port_info, hws, 1);
584	if (!host)
585		return -ENOMEM;
586	/* use extra_base for base address of the all registers */
587	host->ports[0]->extra_base = mapbase;
588	ret = ide_host_register(host, &tx4939ide_port_info, hws);
589	if (ret) {
590		ide_host_free(host);
591		return ret;
592	}
593	platform_set_drvdata(pdev, host);
594	return 0;
595}
596
597static int __exit tx4939ide_remove(struct platform_device *pdev)
598{
599	struct ide_host *host = platform_get_drvdata(pdev);
600
601	ide_host_remove(host);
602	return 0;
603}
604
605#ifdef CONFIG_PM
606static int tx4939ide_resume(struct platform_device *dev)
607{
608	struct ide_host *host = platform_get_drvdata(dev);
609	ide_hwif_t *hwif = host->ports[0];
610
611	tx4939ide_init_hwif(hwif);
612	return 0;
613}
614#else
615#define tx4939ide_resume	NULL
616#endif
617
618static struct platform_driver tx4939ide_driver = {
619	.driver = {
620		.name = MODNAME,
621	},
622	.remove = __exit_p(tx4939ide_remove),
623	.resume = tx4939ide_resume,
624};
625
626module_platform_driver_probe(tx4939ide_driver, tx4939ide_probe);
627
628MODULE_DESCRIPTION("TX4939 internal IDE driver");
629MODULE_LICENSE("GPL");
630MODULE_ALIAS("platform:tx4939ide");
631