77 	struct nv50_disp_base *base = (void *)parent->parent;  in gf110_disp_dmac_object_attach()  local
81 	return nvkm_ramht_insert(base->ramht, chan->chid, name, data);  in gf110_disp_dmac_object_attach()
87 	struct nv50_disp_base *base = (void *)parent->parent;  in gf110_disp_dmac_object_detach()  local
88 	nvkm_ramht_remove(base->ramht, cookie);  in gf110_disp_dmac_object_detach()
96 	int chid = dmac->base.chid;  in gf110_disp_dmac_init()
99 	ret = nv50_disp_chan_init(&dmac->base);  in gf110_disp_dmac_init()
129 	int chid = dmac->base.chid;  in gf110_disp_dmac_fini()
145 	return nv50_disp_chan_fini(&dmac->base, suspend);  in gf110_disp_dmac_fini()
299 	ret = nv50_disp_chan_init(&mast->base);  in gf110_disp_core_init()
342 	return nv50_disp_chan_fini(&mast->base, suspend);  in gf110_disp_core_fini()
347 	.base.ctor = nv50_disp_core_ctor,
348 	.base.dtor = nv50_disp_dmac_dtor,
349 	.base.init = gf110_disp_core_init,
350 	.base.fini = gf110_disp_core_fini,
351 	.base.ntfy = nv50_disp_chan_ntfy,
352 	.base.map  = nv50_disp_chan_map,
353 	.base.rd32 = nv50_disp_chan_rd32,
354 	.base.wr32 = nv50_disp_chan_wr32,
441 	.base.ctor = nv50_disp_base_ctor,
442 	.base.dtor = nv50_disp_dmac_dtor,
443 	.base.init = gf110_disp_dmac_init,
444 	.base.fini = gf110_disp_dmac_fini,
445 	.base.ntfy = nv50_disp_chan_ntfy,
446 	.base.map  = nv50_disp_chan_map,
447 	.base.rd32 = nv50_disp_chan_rd32,
448 	.base.wr32 = nv50_disp_chan_wr32,
522 	.base.ctor = nv50_disp_ovly_ctor,
523 	.base.dtor = nv50_disp_dmac_dtor,
524 	.base.init = gf110_disp_dmac_init,
525 	.base.fini = gf110_disp_dmac_fini,
526 	.base.ntfy = nv50_disp_chan_ntfy,
527 	.base.map  = nv50_disp_chan_map,
528 	.base.rd32 = nv50_disp_chan_rd32,
529 	.base.wr32 = nv50_disp_chan_wr32,
544 	int chid = pioc->base.chid;  in gf110_disp_pioc_init()
547 	ret = nv50_disp_chan_init(&pioc->base);  in gf110_disp_pioc_init()
570 	int chid = pioc->base.chid;  in gf110_disp_pioc_fini()
584 	return nv50_disp_chan_fini(&pioc->base, suspend);  in gf110_disp_pioc_fini()
593 	.base.ctor = nv50_disp_oimm_ctor,
594 	.base.dtor = nv50_disp_pioc_dtor,
595 	.base.init = gf110_disp_pioc_init,
596 	.base.fini = gf110_disp_pioc_fini,
597 	.base.ntfy = nv50_disp_chan_ntfy,
598 	.base.map  = nv50_disp_chan_map,
599 	.base.rd32 = nv50_disp_chan_rd32,
600 	.base.wr32 = nv50_disp_chan_wr32,
610 	.base.ctor = nv50_disp_curs_ctor,
611 	.base.dtor = nv50_disp_pioc_dtor,
612 	.base.init = gf110_disp_pioc_init,
613 	.base.fini = gf110_disp_pioc_fini,
614 	.base.ntfy = nv50_disp_chan_ntfy,
615 	.base.map  = nv50_disp_chan_map,
616 	.base.rd32 = nv50_disp_chan_rd32,
617 	.base.wr32 = nv50_disp_chan_wr32,
661 	struct nv50_disp_base *base = (void *)object;  in gf110_disp_main_init()  local
665 	ret = nvkm_parent_init(&base->base);  in gf110_disp_main_init()
730 	struct nv50_disp_base *base = (void *)object;  in gf110_disp_main_fini()  local
735 	return nvkm_parent_fini(&base->base, suspend);  in gf110_disp_main_fini()
756 	{ GF110_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base },
757 	{ GF110_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base },
758 	{ GF110_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base },
759 	{ GF110_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base },
760 	{ GF110_DISP_CURSOR, &gf110_disp_curs_ofuncs.base },
820 	list_for_each_entry(outp, &priv->base.outp, head) {  in exec_lookup()
1178 					    impl->mthd.base);  in gf110_disp_intr_error()
1246 				nvkm_disp_vblank(&priv->base, i);  in gf110_disp_intr()
1290 	&gf110_sor_dp_impl.base.base,
1296 	.base.base.handle = NV_ENGINE(DISP, 0x90),
1297 	.base.base.ofuncs = &(struct nvkm_ofuncs) {
1303 	.base.vblank = &gf110_disp_vblank_func,
1304 	.base.outp =  gf110_disp_outp_sclass,
1306 	.mthd.base = &gf110_disp_base_mthd_chan,
1310 }.base.base;