Lines Matching refs:base
73 static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg) in l2c_write_sec() argument
75 if (val == readl_relaxed(base + reg)) in l2c_write_sec()
80 writel_relaxed(val, base + reg); in l2c_write_sec()
88 static inline void l2c_set_debug(void __iomem *base, unsigned long val) in l2c_set_debug() argument
90 l2c_write_sec(val, base, L2X0_DEBUG_CTRL); in l2c_set_debug()
99 static inline void l2c_unlock(void __iomem *base, unsigned num) in l2c_unlock() argument
104 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE + in l2c_unlock()
106 writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE + in l2c_unlock()
111 static void l2c_configure(void __iomem *base) in l2c_configure() argument
119 l2x0_data->configure(base); in l2c_configure()
121 l2c_write_sec(l2x0_saved_regs.aux_ctrl, base, L2X0_AUX_CTRL); in l2c_configure()
128 static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock) in l2c_enable() argument
133 if (readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN) in l2c_enable()
137 l2c_configure(base); in l2c_enable()
139 l2c_unlock(base, num_lock); in l2c_enable()
142 __l2c_op_way(base + L2X0_INV_WAY); in l2c_enable()
143 writel_relaxed(0, base + sync_reg_offset); in l2c_enable()
144 l2c_wait_mask(base + sync_reg_offset, 1); in l2c_enable()
147 l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL); in l2c_enable()
152 void __iomem *base = l2x0_base; in l2c_disable() local
155 l2c_write_sec(0, base, L2X0_CTRL); in l2c_disable()
159 static void l2c_save(void __iomem *base) in l2c_save() argument
183 static void __l2c210_cache_sync(void __iomem *base) in __l2c210_cache_sync() argument
185 writel_relaxed(0, base + sync_reg_offset); in __l2c210_cache_sync()
199 void __iomem *base = l2x0_base; in l2c210_inv_range() local
203 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); in l2c210_inv_range()
209 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); in l2c210_inv_range()
212 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); in l2c210_inv_range()
213 __l2c210_cache_sync(base); in l2c210_inv_range()
218 void __iomem *base = l2x0_base; in l2c210_clean_range() local
221 __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end); in l2c210_clean_range()
222 __l2c210_cache_sync(base); in l2c210_clean_range()
227 void __iomem *base = l2x0_base; in l2c210_flush_range() local
230 __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end); in l2c210_flush_range()
231 __l2c210_cache_sync(base); in l2c210_flush_range()
236 void __iomem *base = l2x0_base; in l2c210_flush_all() local
240 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); in l2c210_flush_all()
241 __l2c210_cache_sync(base); in l2c210_flush_all()
276 static inline void __l2c220_cache_sync(void __iomem *base) in __l2c220_cache_sync() argument
278 writel_relaxed(0, base + L2X0_CACHE_SYNC); in __l2c220_cache_sync()
279 l2c_wait_mask(base + L2X0_CACHE_SYNC, 1); in __l2c220_cache_sync()
282 static void l2c220_op_way(void __iomem *base, unsigned reg) in l2c220_op_way() argument
287 __l2c_op_way(base + reg); in l2c220_op_way()
288 __l2c220_cache_sync(base); in l2c220_op_way()
317 void __iomem *base = l2x0_base; in l2c220_inv_range() local
324 writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA); in l2c220_inv_range()
330 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); in l2c220_inv_range()
331 writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA); in l2c220_inv_range()
335 flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA, in l2c220_inv_range()
337 l2c_wait_mask(base + L2X0_INV_LINE_PA, 1); in l2c220_inv_range()
338 __l2c220_cache_sync(base); in l2c220_inv_range()
344 void __iomem *base = l2x0_base; in l2c220_clean_range() local
349 l2c220_op_way(base, L2X0_CLEAN_WAY); in l2c220_clean_range()
354 flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA, in l2c220_clean_range()
356 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); in l2c220_clean_range()
357 __l2c220_cache_sync(base); in l2c220_clean_range()
363 void __iomem *base = l2x0_base; in l2c220_flush_range() local
368 l2c220_op_way(base, L2X0_CLEAN_INV_WAY); in l2c220_flush_range()
373 flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, in l2c220_flush_range()
375 l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1); in l2c220_flush_range()
376 __l2c220_cache_sync(base); in l2c220_flush_range()
394 static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock) in l2c220_enable() argument
403 l2c_enable(base, aux, num_lock); in l2c220_enable()
469 void __iomem *base = l2x0_base; in l2c310_inv_range_erratum() local
476 l2c_set_debug(base, 0x03); in l2c310_inv_range_erratum()
480 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); in l2c310_inv_range_erratum()
481 writel_relaxed(start, base + L2X0_INV_LINE_PA); in l2c310_inv_range_erratum()
487 writel_relaxed(end, base + L2X0_CLEAN_LINE_PA); in l2c310_inv_range_erratum()
488 writel_relaxed(end, base + L2X0_INV_LINE_PA); in l2c310_inv_range_erratum()
491 l2c_set_debug(base, 0x00); in l2c310_inv_range_erratum()
495 __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end); in l2c310_inv_range_erratum()
496 __l2c210_cache_sync(base); in l2c310_inv_range_erratum()
503 void __iomem *base = l2x0_base; in l2c310_flush_range_erratum() local
509 l2c_set_debug(base, 0x03); in l2c310_flush_range_erratum()
511 writel_relaxed(start, base + L2X0_CLEAN_LINE_PA); in l2c310_flush_range_erratum()
512 writel_relaxed(start, base + L2X0_INV_LINE_PA); in l2c310_flush_range_erratum()
515 l2c_set_debug(base, 0x00); in l2c310_flush_range_erratum()
523 __l2c210_cache_sync(base); in l2c310_flush_range_erratum()
528 void __iomem *base = l2x0_base; in l2c310_flush_all_erratum() local
532 l2c_set_debug(base, 0x03); in l2c310_flush_all_erratum()
533 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); in l2c310_flush_all_erratum()
534 l2c_set_debug(base, 0x00); in l2c310_flush_all_erratum()
535 __l2c210_cache_sync(base); in l2c310_flush_all_erratum()
539 static void __init l2c310_save(void __iomem *base) in l2c310_save() argument
543 l2c_save(base); in l2c310_save()
545 l2x0_saved_regs.tag_latency = readl_relaxed(base + in l2c310_save()
547 l2x0_saved_regs.data_latency = readl_relaxed(base + in l2c310_save()
549 l2x0_saved_regs.filter_end = readl_relaxed(base + in l2c310_save()
551 l2x0_saved_regs.filter_start = readl_relaxed(base + in l2c310_save()
554 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_save()
559 l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base + in l2c310_save()
564 l2x0_saved_regs.pwr_ctrl = readl_relaxed(base + in l2c310_save()
568 static void l2c310_configure(void __iomem *base) in l2c310_configure() argument
573 l2c_write_sec(l2x0_saved_regs.tag_latency, base, in l2c310_configure()
575 l2c_write_sec(l2x0_saved_regs.data_latency, base, in l2c310_configure()
577 l2c_write_sec(l2x0_saved_regs.filter_end, base, in l2c310_configure()
579 l2c_write_sec(l2x0_saved_regs.filter_start, base, in l2c310_configure()
582 revision = readl_relaxed(base + L2X0_CACHE_ID) & in l2c310_configure()
586 l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base, in l2c310_configure()
589 l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base, in l2c310_configure()
606 static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock) in l2c310_enable() argument
608 unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_RTL_MASK; in l2c310_enable()
622 u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL); in l2c310_enable()
654 l2c_enable(base, aux, num_lock); in l2c310_enable()
657 aux = readl_relaxed(base + L2X0_AUX_CTRL); in l2c310_enable()
660 u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL); in l2c310_enable()
672 power_ctrl = readl_relaxed(base + L310_POWER_CTRL); in l2c310_enable()
684 static void __init l2c310_fixup(void __iomem *base, u32 cache_id, in l2c310_fixup() argument
882 void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask) in l2x0_init() argument
887 l2x0_base = base; in l2x0_init()
889 cache_id = readl_relaxed(base + L2X0_CACHE_ID); in l2x0_init()
1280 void __iomem *base = l2x0_base; in aurora_pa_range() local
1297 writel_relaxed(start, base + AURORA_RANGE_BASE_ADDR_REG); in aurora_pa_range()
1298 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset); in aurora_pa_range()
1301 writel_relaxed(0, base + AURORA_SYNC_REG); in aurora_pa_range()
1330 void __iomem *base = l2x0_base; in aurora_flush_all() local
1335 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); in aurora_flush_all()
1338 writel_relaxed(0, base + AURORA_SYNC_REG); in aurora_flush_all()
1348 void __iomem *base = l2x0_base; in aurora_disable() local
1352 __l2c_op_way(base + L2X0_CLEAN_INV_WAY); in aurora_disable()
1353 writel_relaxed(0, base + AURORA_SYNC_REG); in aurora_disable()
1354 l2c_write_sec(0, base, L2X0_CTRL); in aurora_disable()
1359 static void aurora_save(void __iomem *base) in aurora_save() argument
1361 l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL); in aurora_save()
1362 l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL); in aurora_save()
1369 static void __init aurora_enable_no_outer(void __iomem *base, u32 aux, in aurora_enable_no_outer() argument
1380 l2c_enable(base, aux, num_lock); in aurora_enable_no_outer()
1383 static void __init aurora_fixup(void __iomem *base, u32 cache_id, in aurora_fixup() argument
1599 static void __init tauros3_save(void __iomem *base) in tauros3_save() argument
1601 l2c_save(base); in tauros3_save()
1604 readl_relaxed(base + TAUROS3_AUX2_CTRL); in tauros3_save()
1606 readl_relaxed(base + L310_PREFETCH_CTRL); in tauros3_save()
1609 static void tauros3_configure(void __iomem *base) in tauros3_configure() argument
1612 base + TAUROS3_AUX2_CTRL); in tauros3_configure()
1614 base + L310_PREFETCH_CTRL); in tauros3_configure()