Lines Matching refs:base
58 static void __iomem *base; variable
67 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_mode()
68 writel(~0, base + TIMER1_BASE + REG_LOAD); in moxart_clkevt_mode()
71 writel(clock_count_per_tick, base + TIMER1_BASE + REG_LOAD); in moxart_clkevt_mode()
72 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_mode()
77 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_mode()
87 writel(TIMER1_DISABLE, base + TIMER_CR); in moxart_clkevt_next_event()
89 u = readl(base + TIMER1_BASE + REG_COUNT) - cycles; in moxart_clkevt_next_event()
90 writel(u, base + TIMER1_BASE + REG_MATCH1); in moxart_clkevt_next_event()
92 writel(TIMER1_ENABLE, base + TIMER_CR); in moxart_clkevt_next_event()
125 base = of_iomap(node, 0); in moxart_timer_init()
126 if (!base) in moxart_timer_init()
143 if (clocksource_mmio_init(base + TIMER2_BASE + REG_COUNT, in moxart_timer_init()
150 writel(~0, base + TIMER2_BASE + REG_LOAD); in moxart_timer_init()
151 writel(TIMEREG_CR_2_ENABLE, base + TIMER_CR); in moxart_timer_init()