74 	void __iomem	*base;  member
100 static void vic_init2(void __iomem *base)  in vic_init2()  argument
105 		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);  in vic_init2()
109 	writel(32, base + VIC_PL190_DEF_VECT_ADDR);  in vic_init2()
115 	void __iomem *base = vic->base;  in resume_one_vic()  local
117 	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);  in resume_one_vic()
120 	vic_init2(base);  in resume_one_vic()
122 	writel(vic->int_select, base + VIC_INT_SELECT);  in resume_one_vic()
123 	writel(vic->protect, base + VIC_PROTECT);  in resume_one_vic()
126 	writel(vic->int_enable, base + VIC_INT_ENABLE);  in resume_one_vic()
127 	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);  in resume_one_vic()
131 	writel(vic->soft_int, base + VIC_INT_SOFT);  in resume_one_vic()
132 	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);  in resume_one_vic()
145 	void __iomem *base = vic->base;  in suspend_one_vic()  local
147 	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);  in suspend_one_vic()
149 	vic->int_select = readl(base + VIC_INT_SELECT);  in suspend_one_vic()
150 	vic->int_enable = readl(base + VIC_INT_ENABLE);  in suspend_one_vic()
151 	vic->soft_int = readl(base + VIC_INT_SOFT);  in suspend_one_vic()
152 	vic->protect = readl(base + VIC_PROTECT);  in suspend_one_vic()
157 	writel(vic->resume_irqs, base + VIC_INT_ENABLE);  in suspend_one_vic()
158 	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);  in suspend_one_vic()
204 	irq_set_chip_data(irq, v->base);  in vic_irqdomain_map()
220 	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {  in handle_one_vic()
237 	while ((stat = readl_relaxed(vic->base + VIC_IRQ_STATUS))) {  in vic_handle_irq_cascaded()
279 static void __init vic_register(void __iomem *base, unsigned int parent_irq,  in vic_register()  argument
293 	v->base = base;  in vic_register()
319 	void __iomem *base = irq_data_get_irq_chip_data(d);  in vic_ack_irq()  local
321 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);  in vic_ack_irq()
323 	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);  in vic_ack_irq()
328 	void __iomem *base = irq_data_get_irq_chip_data(d);  in vic_mask_irq()  local
330 	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);  in vic_mask_irq()
335 	void __iomem *base = irq_data_get_irq_chip_data(d);  in vic_unmask_irq()  local
337 	writel(1 << irq, base + VIC_INT_ENABLE);  in vic_unmask_irq()
386 static void __init vic_disable(void __iomem *base)  in vic_disable()  argument
388 	writel(0, base + VIC_INT_SELECT);  in vic_disable()
389 	writel(0, base + VIC_INT_ENABLE);  in vic_disable()
390 	writel(~0, base + VIC_INT_ENABLE_CLEAR);  in vic_disable()
391 	writel(0, base + VIC_ITCR);  in vic_disable()
392 	writel(~0, base + VIC_INT_SOFT_CLEAR);  in vic_disable()
395 static void __init vic_clear_interrupts(void __iomem *base)  in vic_clear_interrupts()  argument
399 	writel(0, base + VIC_PL190_VECT_ADDR);  in vic_clear_interrupts()
403 		value = readl(base + VIC_PL190_VECT_ADDR);  in vic_clear_interrupts()
404 		writel(value, base + VIC_PL190_VECT_ADDR);  in vic_clear_interrupts()
415 static void __init vic_init_st(void __iomem *base, unsigned int irq_start,  in vic_init_st()  argument
419 	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;  in vic_init_st()
422 	vic_disable(base);  in vic_init_st()
431 		vic_clear_interrupts(base);  in vic_init_st()
435 			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);  in vic_init_st()
439 		writel(32, base + VIC_PL190_DEF_VECT_ADDR);  in vic_init_st()
442 	vic_register(base, 0, irq_start, vic_sources, 0, node);  in vic_init_st()
445 void __init __vic_init(void __iomem *base, int parent_irq, int irq_start,  in __vic_init()  argument
456 		addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);  in __vic_init()
461 	       base, cellid, vendor);  in __vic_init()
465 		vic_init_st(base, irq_start, vic_sources, node);  in __vic_init()
475 	vic_disable(base);  in __vic_init()
478 	vic_clear_interrupts(base);  in __vic_init()
480 	vic_init2(base);  in __vic_init()
482 	vic_register(base, parent_irq, irq_start, vic_sources, resume_sources, node);  in __vic_init()
492 void __init vic_init(void __iomem *base, unsigned int irq_start,  in vic_init()  argument
495 	__vic_init(base, 0, irq_start, vic_sources, resume_sources, NULL);  in vic_init()
508 int __init vic_init_cascaded(void __iomem *base, unsigned int parent_irq,  in vic_init_cascaded()  argument
514 	__vic_init(base, parent_irq, 0, vic_sources, resume_sources, NULL);  in vic_init_cascaded()