96 	void __iomem *base;  member
111 	int_en = readl(idev->base + MST_INT_ENABLE);  in i2c_int_disable()
112 	writel(int_en & ~mask, idev->base + MST_INT_ENABLE);  in i2c_int_disable()
119 	int_en = readl(idev->base + MST_INT_ENABLE);  in i2c_int_enable()
120 	writel(int_en | mask, idev->base + MST_INT_ENABLE);  in i2c_int_enable()
145 	writel(0x01, idev->base + SOFT_RESET);  in axxia_i2c_init()
147 	while (readl(idev->base + SOFT_RESET) & 1) {  in axxia_i2c_init()
155 	writel(0x1, idev->base + GLOBAL_CONTROL);  in axxia_i2c_init()
170 	writel(t_high, idev->base + SCL_HIGH_PERIOD);  in axxia_i2c_init()
172 	writel(t_low, idev->base + SCL_LOW_PERIOD);  in axxia_i2c_init()
174 	writel(t_setup, idev->base + SDA_SETUP_TIME);  in axxia_i2c_init()
176 	writel(ns_to_clk(300, clk_mhz), idev->base + SDA_HOLD_TIME);  in axxia_i2c_init()
178 	writel(ns_to_clk(50, clk_mhz), idev->base + SPIKE_FLTR_LEN);  in axxia_i2c_init()
193 	writel(prescale, idev->base + TIMER_CLOCK_DIV);  in axxia_i2c_init()
195 	writel(WT_EN | WT_VALUE(tmo_clk), idev->base + WAIT_TIMER_CONTROL);  in axxia_i2c_init()
201 	writel(0x01, idev->base + INTERRUPT_ENABLE);  in axxia_i2c_init()
228 	size_t rx_fifo_avail = readl(idev->base + MST_RX_FIFO);  in axxia_i2c_empty_rx_fifo()
232 		int c = readl(idev->base + MST_DATA);  in axxia_i2c_empty_rx_fifo()
245 			writel(msg->len, idev->base + MST_RX_XFER);  in axxia_i2c_empty_rx_fifo()
260 	size_t tx_fifo_avail = FIFO_SIZE - readl(idev->base + MST_TX_FIFO);  in axxia_i2c_fill_tx_fifo()
265 		writel(msg->buf[idev->msg_xfrd++], idev->base + MST_DATA);  in axxia_i2c_fill_tx_fifo()
275 	if (!(readl(idev->base + INTERRUPT_STATUS) & INT_MST))  in axxia_i2c_isr()
279 	status = readl(idev->base + MST_INT_STATUS);  in axxia_i2c_isr()
318 			readl(idev->base + MST_RX_BYTES_XFRD),  in axxia_i2c_isr()
319 			readl(idev->base + MST_RX_XFER),  in axxia_i2c_isr()
320 			readl(idev->base + MST_TX_BYTES_XFRD),  in axxia_i2c_isr()
321 			readl(idev->base + MST_TX_XFER));  in axxia_i2c_isr()
327 	writel(INT_MST, idev->base + INTERRUPT_STATUS);  in axxia_i2c_isr()
371 	writel(rx_xfer, idev->base + MST_RX_XFER);  in axxia_i2c_xfer_msg()
372 	writel(tx_xfer, idev->base + MST_TX_XFER);  in axxia_i2c_xfer_msg()
373 	writel(addr_1, idev->base + MST_ADDR_1);  in axxia_i2c_xfer_msg()
374 	writel(addr_2, idev->base + MST_ADDR_2);  in axxia_i2c_xfer_msg()
382 	writel(CMD_MANUAL, idev->base + MST_COMMAND);  in axxia_i2c_xfer_msg()
391 	if (readl(idev->base + MST_COMMAND) & CMD_BUSY)  in axxia_i2c_xfer_msg()
411 	writel(0xb, idev->base + MST_COMMAND);  in axxia_i2c_stop()
419 	if (readl(idev->base + MST_COMMAND) & CMD_BUSY)  in axxia_i2c_stop()
462 	void __iomem *base;  in axxia_i2c_probe()  local
471 	base = devm_ioremap_resource(&pdev->dev, res);  in axxia_i2c_probe()
472 	if (IS_ERR(base))  in axxia_i2c_probe()
473 		return PTR_ERR(base);  in axxia_i2c_probe()
487 	idev->base = base;  in axxia_i2c_probe()