1 /*
2 * Pistachio platform setup
3 *
4 * Copyright (C) 2014 Google, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 */
10
11 #include <linux/init.h>
12 #include <linux/kernel.h>
13 #include <linux/of_address.h>
14 #include <linux/of_fdt.h>
15 #include <linux/of_platform.h>
16
17 #include <asm/cacheflush.h>
18 #include <asm/dma-coherence.h>
19 #include <asm/fw/fw.h>
20 #include <asm/mips-boards/generic.h>
21 #include <asm/mips-cm.h>
22 #include <asm/mips-cpc.h>
23 #include <asm/prom.h>
24 #include <asm/smp-ops.h>
25 #include <asm/traps.h>
26
get_system_type(void)27 const char *get_system_type(void)
28 {
29 return "IMG Pistachio SoC";
30 }
31
plat_setup_iocoherency(void)32 static void __init plat_setup_iocoherency(void)
33 {
34 /*
35 * Kernel has been configured with software coherency
36 * but we might choose to turn it off and use hardware
37 * coherency instead.
38 */
39 if (mips_cm_numiocu() != 0) {
40 /* Nothing special needs to be done to enable coherency */
41 pr_info("CMP IOCU detected\n");
42 hw_coherentio = 1;
43 if (coherentio == 0)
44 pr_info("Hardware DMA cache coherency disabled\n");
45 else
46 pr_info("Hardware DMA cache coherency enabled\n");
47 } else {
48 if (coherentio == 1)
49 pr_info("Hardware DMA cache coherency unsupported, but enabled from command line!\n");
50 else
51 pr_info("Software DMA cache coherency enabled\n");
52 }
53 }
54
plat_mem_setup(void)55 void __init plat_mem_setup(void)
56 {
57 if (fw_arg0 != -2)
58 panic("Device-tree not present");
59
60 __dt_setup_arch((void *)fw_arg1);
61 strlcpy(arcs_cmdline, boot_command_line, COMMAND_LINE_SIZE);
62
63 plat_setup_iocoherency();
64 }
65
66 #define DEFAULT_CPC_BASE_ADDR 0x1bde0000
67
mips_cpc_default_phys_base(void)68 phys_addr_t mips_cpc_default_phys_base(void)
69 {
70 return DEFAULT_CPC_BASE_ADDR;
71 }
72
mips_nmi_setup(void)73 static void __init mips_nmi_setup(void)
74 {
75 void *base;
76 extern char except_vec_nmi;
77
78 base = cpu_has_veic ?
79 (void *)(CAC_BASE + 0xa80) :
80 (void *)(CAC_BASE + 0x380);
81 memcpy(base, &except_vec_nmi, 0x80);
82 flush_icache_range((unsigned long)base,
83 (unsigned long)base + 0x80);
84 }
85
mips_ejtag_setup(void)86 static void __init mips_ejtag_setup(void)
87 {
88 void *base;
89 extern char except_vec_ejtag_debug;
90
91 base = cpu_has_veic ?
92 (void *)(CAC_BASE + 0xa00) :
93 (void *)(CAC_BASE + 0x300);
94 memcpy(base, &except_vec_ejtag_debug, 0x80);
95 flush_icache_range((unsigned long)base,
96 (unsigned long)base + 0x80);
97 }
98
prom_init(void)99 void __init prom_init(void)
100 {
101 board_nmi_handler_setup = mips_nmi_setup;
102 board_ejtag_handler_setup = mips_ejtag_setup;
103
104 mips_cm_probe();
105 mips_cpc_probe();
106 register_cps_smp_ops();
107 }
108
prom_free_prom_memory(void)109 void __init prom_free_prom_memory(void)
110 {
111 }
112
device_tree_init(void)113 void __init device_tree_init(void)
114 {
115 if (!initial_boot_params)
116 return;
117
118 unflatten_and_copy_device_tree();
119 }
120
plat_of_setup(void)121 static int __init plat_of_setup(void)
122 {
123 if (!of_have_populated_dt())
124 panic("Device tree not present");
125
126 if (of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL))
127 panic("Failed to populate DT");
128
129 return 0;
130 }
131 arch_initcall(plat_of_setup);
132