62 	struct nvkm_fifo base;  member
76 	struct nvkm_fifo_base base;  member
82 	struct nvkm_fifo_chan base;  member
107 	for (i = 0, p = 0; i < priv->base.max; i++) {  in gk104_fifo_runlist_update()
108 		struct gk104_fifo_chan *chan = (void *)priv->base.channel[i];  in gk104_fifo_runlist_update()
132 	struct gk104_fifo_base *base = (void *)parent->parent;  in gk104_fifo_context_attach()  local
143 		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;  in gk104_fifo_context_attach()
154 		ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,  in gk104_fifo_context_attach()
159 		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;  in gk104_fifo_context_attach()
162 	nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);  in gk104_fifo_context_attach()
163 	nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));  in gk104_fifo_context_attach()
174 	struct gk104_fifo_base *base = (void *)parent->parent;  in gk104_fifo_context_detach()  local
191 	nv_wr32(priv, 0x002634, chan->base.chid);  in gk104_fifo_context_detach()
192 	if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {  in gk104_fifo_context_detach()
194 			 chan->base.chid, nvkm_client_name(chan));  in gk104_fifo_context_detach()
200 		nv_wo32(base, addr + 0x00, 0x00000000);  in gk104_fifo_context_detach()
201 		nv_wo32(base, addr + 0x04, 0x00000000);  in gk104_fifo_context_detach()
218 	struct gk104_fifo_base *base = (void *)parent;  in gk104_fifo_chan_ctor()  local
254 	args->v0.chid = chan->base.chid;  in gk104_fifo_chan_ctor()
260 	usermem = chan->base.chid * 0x200;  in gk104_fifo_chan_ctor()
267 	nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));  in gk104_fifo_chan_ctor()
268 	nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));  in gk104_fifo_chan_ctor()
269 	nv_wo32(base, 0x10, 0x0000face);  in gk104_fifo_chan_ctor()
270 	nv_wo32(base, 0x30, 0xfffff902);  in gk104_fifo_chan_ctor()
271 	nv_wo32(base, 0x48, lower_32_bits(ioffset));  in gk104_fifo_chan_ctor()
272 	nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));  in gk104_fifo_chan_ctor()
273 	nv_wo32(base, 0x84, 0x20400000);  in gk104_fifo_chan_ctor()
274 	nv_wo32(base, 0x94, 0x30000001);  in gk104_fifo_chan_ctor()
275 	nv_wo32(base, 0x9c, 0x00000100);  in gk104_fifo_chan_ctor()
276 	nv_wo32(base, 0xac, 0x0000001f);  in gk104_fifo_chan_ctor()
277 	nv_wo32(base, 0xe8, chan->base.chid);  in gk104_fifo_chan_ctor()
278 	nv_wo32(base, 0xb8, 0xf8000000);  in gk104_fifo_chan_ctor()
279 	nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */  in gk104_fifo_chan_ctor()
280 	nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */  in gk104_fifo_chan_ctor()
288 	struct nvkm_gpuobj *base = nv_gpuobj(object->parent);  in gk104_fifo_chan_init()  local
291 	u32 chid = chan->base.chid;  in gk104_fifo_chan_init()
294 	ret = nvkm_fifo_channel_init(&chan->base);  in gk104_fifo_chan_init()
299 	nv_wr32(priv, 0x800000 + (chid * 8), 0x80000000 | base->addr >> 12);  in gk104_fifo_chan_init()
315 	u32 chid = chan->base.chid;  in gk104_fifo_chan_fini()
323 	return nvkm_fifo_channel_fini(&chan->base, suspend);  in gk104_fifo_chan_fini()
353 	struct gk104_fifo_base *base;  in gk104_fifo_context_ctor()  local
357 				       0x1000, NVOBJ_FLAG_ZERO_ALLOC, &base);  in gk104_fifo_context_ctor()
358 	*pobject = nv_object(base);  in gk104_fifo_context_ctor()
362 	ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,  in gk104_fifo_context_ctor()
363 			      &base->pgd);  in gk104_fifo_context_ctor()
367 	nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));  in gk104_fifo_context_ctor()
368 	nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));  in gk104_fifo_context_ctor()
369 	nv_wo32(base, 0x0208, 0xffffffff);  in gk104_fifo_context_ctor()
370 	nv_wo32(base, 0x020c, 0x000000ff);  in gk104_fifo_context_ctor()
372 	ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);  in gk104_fifo_context_ctor()
382 	struct gk104_fifo_base *base = (void *)object;  in gk104_fifo_context_dtor()  local
383 	nvkm_vm_ref(NULL, &base->vm, base->pgd);  in gk104_fifo_context_dtor()
384 	nvkm_gpuobj_ref(NULL, &base->pgd);  in gk104_fifo_context_dtor()
385 	nvkm_fifo_context_destroy(&base->base);  in gk104_fifo_context_dtor()
441 	spin_lock_irqsave(&priv->base.lock, flags);  in gk104_fifo_recover_work()
444 	spin_unlock_irqrestore(&priv->base.lock, flags);  in gk104_fifo_recover_work()
466 	u32 chid = chan->base.chid;  in gk104_fifo_recover()
475 	spin_lock_irqsave(&priv->base.lock, flags);  in gk104_fifo_recover()
477 	spin_unlock_irqrestore(&priv->base.lock, flags);  in gk104_fifo_recover()
489 	spin_lock_irqsave(&priv->base.lock, flags);  in gk104_fifo_swmthd()
490 	if (likely(chid >= priv->base.min && chid <= priv->base.max))  in gk104_fifo_swmthd()
491 		chan = (void *)priv->base.channel[chid];  in gk104_fifo_swmthd()
503 	spin_unlock_irqrestore(&priv->base.lock, flags);  in gk104_fifo_swmthd()
558 			if (!(chan = (void *)priv->base.channel[chid]))  in gk104_fifo_intr_sched_ctxsw()
846 			 nvkm_client_name_for_fifo_chid(&priv->base, chid),  in gk104_fifo_intr_pbdma_0()
896 	nvkm_fifo_uevent(&priv->base);  in gk104_fifo_intr_engine()
1016 	ret = nvkm_fifo_fini(&priv->base, suspend);  in gk104_fifo_fini()
1031 	ret = nvkm_fifo_init(&priv->base);  in gk104_fifo_init()
1074 	nvkm_fifo_destroy(&priv->base);  in gk104_fifo_dtor()
1118 	ret = nvkm_event_init(&gk104_fifo_uevent_func, 1, 1, &priv->base.uevent);  in gk104_fifo_ctor()
1131 	.base.handle = NV_ENGINE(FIFO, 0xe0),
1132 	.base.ofuncs = &(struct nvkm_ofuncs) {
1139 }.base;