24 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, hdmi_read_reg(wp->base, r))  in hdmi_wp_dump()
48 	return hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_get_irqstatus()
53 	hdmi_write_reg(wp->base, HDMI_WP_IRQSTATUS, irqstatus);  in hdmi_wp_set_irqstatus()
55 	hdmi_read_reg(wp->base, HDMI_WP_IRQSTATUS);  in hdmi_wp_set_irqstatus()
60 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_SET, mask);  in hdmi_wp_set_irqenable()
65 	hdmi_write_reg(wp->base, HDMI_WP_IRQENABLE_CLR, mask);  in hdmi_wp_clear_irqenable()
72 	if (REG_GET(wp->base, HDMI_WP_PWR_CTRL, 5, 4) == val)  in hdmi_wp_set_phy_pwr()
76 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 7, 6);  in hdmi_wp_set_phy_pwr()
79 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 5, 4, val)  in hdmi_wp_set_phy_pwr()
92 	REG_FLD_MOD(wp->base, HDMI_WP_PWR_CTRL, val, 3, 2);  in hdmi_wp_set_pll_pwr()
95 	if (hdmi_wait_for_bit_change(wp->base, HDMI_WP_PWR_CTRL, 1, 0, val)  in hdmi_wp_set_pll_pwr()
106 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, true, 31, 31);  in hdmi_wp_video_start()
113 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, false, 31, 31);  in hdmi_wp_video_stop()
121 	REG_FLD_MOD(wp->base, HDMI_WP_VIDEO_CFG, video_fmt->packing_mode,  in hdmi_wp_video_config_format()
126 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_SIZE, l);  in hdmi_wp_video_config_format()
139 	r = hdmi_read_reg(wp->base, HDMI_WP_VIDEO_CFG);  in hdmi_wp_video_config_interface()
144 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_CFG, r);  in hdmi_wp_video_config_interface()
158 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_H, timing_h);  in hdmi_wp_video_config_timing()
163 	hdmi_write_reg(wp->base, HDMI_WP_VIDEO_TIMING_V, timing_v);  in hdmi_wp_video_config_timing()
195 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG);  in hdmi_wp_audio_config_format()
208 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG, r);  in hdmi_wp_audio_config_format()
218 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CFG2);  in hdmi_wp_audio_config_dma()
221 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CFG2, r);  in hdmi_wp_audio_config_dma()
223 	r = hdmi_read_reg(wp->base, HDMI_WP_AUDIO_CTRL);  in hdmi_wp_audio_config_dma()
226 	hdmi_write_reg(wp->base, HDMI_WP_AUDIO_CTRL, r);  in hdmi_wp_audio_config_dma()
231 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 31, 31);  in hdmi_wp_audio_enable()
238 	REG_FLD_MOD(wp->base, HDMI_WP_AUDIO_CTRL, enable, 30, 30);  in hdmi_wp_audio_core_req_enable()
254 	wp->base = devm_ioremap_resource(&pdev->dev, res);  in hdmi_wp_init()
255 	if (IS_ERR(wp->base)) {  in hdmi_wp_init()
257 		return PTR_ERR(wp->base);  in hdmi_wp_init()