Lines Matching refs:base
426 u8 __iomem *base; member
469 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
479 dev->base + RXDP); in kick_rx()
620 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; in phy_intr()
624 tbisr = readl(dev->base + TBISR); in phy_intr()
625 tanar = readl(dev->base + TANAR); in phy_intr()
626 tanlpar = readl(dev->base + TANLPAR); in phy_intr()
634 writel(readl(dev->base + TXCFG) in phy_intr()
636 dev->base + TXCFG); in phy_intr()
637 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
638 dev->base + RXCFG); in phy_intr()
640 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, in phy_intr()
641 dev->base + GPIOR); in phy_intr()
651 writel((readl(dev->base + TXCFG) in phy_intr()
653 dev->base + TXCFG); in phy_intr()
654 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, in phy_intr()
655 dev->base + RXCFG); in phy_intr()
657 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, in phy_intr()
658 dev->base + GPIOR); in phy_intr()
677 writel(readl(dev->base + TXCFG) in phy_intr()
679 dev->base + TXCFG); in phy_intr()
680 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, in phy_intr()
681 dev->base + RXCFG); in phy_intr()
683 writel(readl(dev->base + TXCFG) in phy_intr()
685 dev->base + TXCFG); in phy_intr()
686 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), in phy_intr()
687 dev->base + RXCFG); in phy_intr()
692 writel(new_cfg, dev->base + CFG); in phy_intr()
735 writel(0, dev->base + RXDP_HI); in ns83820_setup_rx()
736 writel(dev->rx_info.phy_descs, dev->base + RXDP); in ns83820_setup_rx()
744 writel(0x0001, dev->base + CCSR); in ns83820_setup_rx()
745 writel(0, dev->base + RFCR); in ns83820_setup_rx()
746 writel(0x7fc00000, dev->base + RFCR); in ns83820_setup_rx()
747 writel(0xffc00000, dev->base + RFCR); in ns83820_setup_rx()
766 writel(dev->IMR_cache, dev->base + IMR); in ns83820_setup_rx()
767 writel(1, dev->base + IER); in ns83820_setup_rx()
787 writel(dev->IMR_cache, dev->base + IMR); in ns83820_cleanup_rx()
795 readl(dev->base + IMR); in ns83820_cleanup_rx()
798 writel(0, dev->base + RXDP_HI); in ns83820_cleanup_rx()
799 writel(0, dev->base + RXDP); in ns83820_cleanup_rx()
843 readl(dev->base + RXDP),
945 writel(ihr, dev->base + IHR);
949 writel(dev->IMR_cache, dev->base + IMR);
962 writel(CR_TXE, dev->base + CR);
1191 u8 __iomem *base = dev->base; local
1194 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1195 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1196 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1197 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1198 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1199 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1200 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1201 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1202 /*ndev->stats.rx_pause_count += */ readl(base + 0x80);
1203 /*ndev->stats.tx_pause_count += */ readl(base + 0x84);
1204 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1241 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1242 tanar = readl(dev->base + TANAR);
1243 tbicr = readl(dev->base + TBICR);
1292 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1293 tanar = readl(dev->base + TANAR);
1314 writel(readl(dev->base + TXCFG)
1316 dev->base + TXCFG);
1317 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
1318 dev->base + RXCFG);
1320 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
1321 dev->base + GPIOR);
1339 dev->base + TBICR);
1340 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1347 writel(0x00000000, dev->base + TBICR);
1373 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1386 writel(0, dev->base + IMR);
1387 writel(0, dev->base + IER);
1388 readl(dev->base + IER);
1410 isr = readl(dev->base + ISR);
1437 writel(dev->IMR_cache, dev->base + IMR);
1459 writel(CR_RXE, dev->base + CR);
1463 txdp = readl(dev->base + TXDP);
1494 writel(dev->IMR_cache, dev->base + IMR);
1508 writel(dev->IMR_cache, dev->base + IMR);
1522 writel(dev->ihr, dev->base + IHR);
1529 writel(which, dev->base + CR);
1532 } while (readl(dev->base + CR) & which);
1581 isr = readl(dev->base + ISR);
1631 writel(0, dev->base + PQCR);
1648 writel(0, dev->base + TXDP_HI);
1649 writel(desc, dev->base + TXDP);
1674 writel(i*2, dev->base + RFCR);
1675 data = readl(dev->base + RFDR);
1693 u8 __iomem *rfcr = dev->base + RFCR;
1728 writel(enable, dev->base + PTSCR);
1731 status = readl(dev->base + PTSCR);
1760 writel(dev->MEAR_cache, dev->base + MEAR);
1761 readl(dev->base + MEAR);
1771 writel(dev->MEAR_cache, dev->base + MEAR);
1772 readl(dev->base + MEAR);
1779 writel(dev->MEAR_cache, dev->base + MEAR);
1780 readl(dev->base + MEAR);
1793 writel(dev->MEAR_cache, dev->base + MEAR);
1794 readl(dev->base + MEAR);
1800 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1802 writel(dev->MEAR_cache, dev->base + MEAR);
1989 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1995 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
2029 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
2040 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
2048 dev->CFG_cache = readl(dev->base + CFG);
2084 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
2087 writel(readl(dev->base + TANAR)
2089 dev->base + TANAR);
2093 dev->base + TBICR);
2094 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
2100 writel(dev->CFG_cache, dev->base + CFG);
2105 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
2107 writel(dev->CFG_cache, dev->base + CFG);
2113 if (readl(dev->base + SRR))
2114 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2126 dev->base + TXCFG);
2129 writel(0x000, dev->base + IHR);
2130 writel(0x100, dev->base + IHR);
2131 writel(0x000, dev->base + IHR);
2142 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2145 writel(0, dev->base + PQCR);
2165 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2176 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2182 dev->base + PCR);
2185 writel(0, dev->base + WCSR);
2206 (unsigned)readl(dev->base + SRR) >> 8,
2207 (unsigned)readl(dev->base + SRR) & 0xff,
2231 if (dev->base)
2232 iounmap(dev->base);
2254 iounmap(dev->base);