Lines Matching refs:base
144 if (inb(host->base + ORC_HCTRL) & HOSTSTOP) /* Wait HOSTSTOP set */ in wait_chip_ready()
156 if (inb(host->base + ORC_HSTUS) & RREADY) /* Wait READY set */ in wait_firmware_ready()
169 if (!(inb(host->base + ORC_HCTRL) & SCSIRST)) /* Wait SCSIRST done */ in wait_scsi_reset_done()
182 if (!(inb(host->base + ORC_HCTRL) & HDO)) /* Wait HDO off */ in wait_HDO_off()
195 if ((*data = inb(host->base + ORC_HSTUS)) & HDI) in wait_hdi_set()
208 outb(ORC_CMD_VERSION, host->base + ORC_HDATA); in orc_read_fwrev()
209 outb(HDO, host->base + ORC_HCTRL); in orc_read_fwrev()
215 version = inb(host->base + ORC_HDATA); in orc_read_fwrev()
216 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ in orc_read_fwrev()
220 version |= inb(host->base + ORC_HDATA) << 8; in orc_read_fwrev()
221 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ in orc_read_fwrev()
229 outb(ORC_CMD_SET_NVM, host->base + ORC_HDATA); /* Write command */ in orc_nv_write()
230 outb(HDO, host->base + ORC_HCTRL); in orc_nv_write()
234 outb(address, host->base + ORC_HDATA); /* Write address */ in orc_nv_write()
235 outb(HDO, host->base + ORC_HCTRL); in orc_nv_write()
239 outb(value, host->base + ORC_HDATA); /* Write value */ in orc_nv_write()
240 outb(HDO, host->base + ORC_HCTRL); in orc_nv_write()
252 outb(ORC_CMD_GET_NVM, host->base + ORC_HDATA); /* Write command */ in orc_nv_read()
253 outb(HDO, host->base + ORC_HCTRL); in orc_nv_read()
257 outb(address, host->base + ORC_HDATA); /* Write address */ in orc_nv_read()
258 outb(HDO, host->base + ORC_HCTRL); in orc_nv_read()
264 *ptr = inb(host->base + ORC_HDATA); in orc_nv_read()
265 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ in orc_nv_read()
280 outb(scb->scbidx, host->base + ORC_PQUEUE); in orc_exec_scb()
375 data = inb(host->base + ORC_GCFG); in orc_load_firmware()
376 outb(data | EEPRG, host->base + ORC_GCFG); /* Enable EEPROM programming */ in orc_load_firmware()
377 outb(0x00, host->base + ORC_EBIOSADR2); in orc_load_firmware()
378 outw(0x0000, host->base + ORC_EBIOSADR0); in orc_load_firmware()
379 if (inb(host->base + ORC_EBIOSDATA) != 0x55) { in orc_load_firmware()
380 outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ in orc_load_firmware()
383 outw(0x0001, host->base + ORC_EBIOSADR0); in orc_load_firmware()
384 if (inb(host->base + ORC_EBIOSDATA) != 0xAA) { in orc_load_firmware()
385 outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ in orc_load_firmware()
389 outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Enable SRAM programming */ in orc_load_firmware()
392 outw(0x0010, host->base + ORC_EBIOSADR0); in orc_load_firmware()
393 *data32_ptr = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ in orc_load_firmware()
394 outw(0x0011, host->base + ORC_EBIOSADR0); in orc_load_firmware()
395 *(data32_ptr + 1) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ in orc_load_firmware()
396 outw(0x0012, host->base + ORC_EBIOSADR0); in orc_load_firmware()
397 *(data32_ptr + 2) = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ in orc_load_firmware()
398 outw(*(data32_ptr + 2), host->base + ORC_EBIOSADR2); in orc_load_firmware()
399 outl(le32_to_cpu(data32), host->base + ORC_FWBASEADR); /* Write FW address */ in orc_load_firmware()
408 outw(bios_addr, host->base + ORC_EBIOSADR0); in orc_load_firmware()
409 *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ in orc_load_firmware()
411 outl(le32_to_cpu(data32), host->base + ORC_RISCRAM); /* Write every 4 bytes */ in orc_load_firmware()
418 outb(PRGMRST | DOWNLOAD, host->base + ORC_RISCCTL); /* Reset program count 0 */ in orc_load_firmware()
423 outw(bios_addr, host->base + ORC_EBIOSADR0); in orc_load_firmware()
424 *data32_ptr++ = inb(host->base + ORC_EBIOSDATA); /* Read from BIOS */ in orc_load_firmware()
426 if (inl(host->base + ORC_RISCRAM) != le32_to_cpu(data32)) { in orc_load_firmware()
427 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ in orc_load_firmware()
428 outb(data, host->base + ORC_GCFG); /*Disable EEPROM programming */ in orc_load_firmware()
436 outb(PRGMRST, host->base + ORC_RISCCTL); /* Reset program to 0 */ in orc_load_firmware()
437 outb(data, host->base + ORC_GCFG); /* Disable EEPROM programming */ in orc_load_firmware()
450 outb(ORC_MAXQUEUE, host->base + ORC_SCBSIZE); /* Total number of SCBs */ in setup_SCBs()
452 outl(host->scb_phys, host->base + ORC_SCBBASE0); in setup_SCBs()
454 outl(host->scb_phys, host->base + ORC_SCBBASE1); in setup_SCBs()
506 outb(0xFF, host->base + ORC_GIMSK); /* Disable all interrupts */ in init_orchid()
508 if (inb(host->base + ORC_HSTUS) & RREADY) { /* Orchid is ready */ in init_orchid()
511 outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ in init_orchid()
516 outb(0x00, host->base + ORC_HCTRL); /* clear HOSTSTOP */ in init_orchid()
524 outb(DEVRST, host->base + ORC_HCTRL); /* Reset Host Adapter */ in init_orchid()
529 outb(HDO, host->base + ORC_HCTRL); /* Do Hardware Reset & */ in init_orchid()
554 outb(0xFB, host->base + ORC_GIMSK); /* enable RP FIFO interrupt */ in init_orchid()
573 outb(SCSIRST, host->base + ORC_HCTRL); in orc_reset_scsi_bus()
742 outb(ORC_CMD_ABORT_SCB, host->base + ORC_HDATA); /* Write command */ in orchid_abort_scb()
743 outb(HDO, host->base + ORC_HCTRL); in orchid_abort_scb()
747 outb(scb->scbidx, host->base + ORC_HDATA); /* Write address */ in orchid_abort_scb()
748 outb(HDO, host->base + ORC_HCTRL); in orchid_abort_scb()
754 status = inb(host->base + ORC_HDATA); in orchid_abort_scb()
755 outb(data, host->base + ORC_HSTUS); /* Clear HDI */ in orchid_abort_scb()
817 if (inb(host->base + ORC_RQUEUECNT) == 0) in orc_interrupt()
822 scb_index = inb(host->base + ORC_RQUEUE); in orc_interrupt()
829 } while (inb(host->base + ORC_RQUEUECNT)); in orc_interrupt()
875 sgent->base = cpu_to_le32((u32) sg_dma_address(sg)); in inia100_build_scb()
881 sgent->base = cpu_to_le32(0); in inia100_build_scb()
1122 host->base = port; in inia100_probe_one()
1150 shost->io_port = host->base; in inia100_probe_one()