39 	struct nvkm_fifo base;  member
58 	struct nvkm_fifo_base base;  member
64 	struct nvkm_fifo_chan base;  member
88 		struct gf100_fifo_chan *chan = (void *)priv->base.channel[i];  in gf100_fifo_runlist_update()
112 	struct gf100_fifo_base *base = (void *)parent->parent;  in gf100_fifo_context_attach()  local
130 		ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm,  in gf100_fifo_context_attach()
135 		nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;  in gf100_fifo_context_attach()
138 	nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4);  in gf100_fifo_context_attach()
139 	nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset));  in gf100_fifo_context_attach()
150 	struct gf100_fifo_base *base = (void *)parent->parent;  in gf100_fifo_context_detach()  local
166 	nv_wr32(priv, 0x002634, chan->base.chid);  in gf100_fifo_context_detach()
167 	if (!nv_wait(priv, 0x002634, 0xffffffff, chan->base.chid)) {  in gf100_fifo_context_detach()
169 			 chan->base.chid, nvkm_client_name(chan));  in gf100_fifo_context_detach()
174 	nv_wo32(base, addr + 0x00, 0x00000000);  in gf100_fifo_context_detach()
175 	nv_wo32(base, addr + 0x04, 0x00000000);  in gf100_fifo_context_detach()
190 	struct gf100_fifo_base *base = (void *)parent;  in gf100_fifo_chan_ctor()  local
218 	args->v0.chid = chan->base.chid;  in gf100_fifo_chan_ctor()
223 	usermem = chan->base.chid * 0x1000;  in gf100_fifo_chan_ctor()
230 	nv_wo32(base, 0x08, lower_32_bits(priv->user.mem->addr + usermem));  in gf100_fifo_chan_ctor()
231 	nv_wo32(base, 0x0c, upper_32_bits(priv->user.mem->addr + usermem));  in gf100_fifo_chan_ctor()
232 	nv_wo32(base, 0x10, 0x0000face);  in gf100_fifo_chan_ctor()
233 	nv_wo32(base, 0x30, 0xfffff902);  in gf100_fifo_chan_ctor()
234 	nv_wo32(base, 0x48, lower_32_bits(ioffset));  in gf100_fifo_chan_ctor()
235 	nv_wo32(base, 0x4c, upper_32_bits(ioffset) | (ilength << 16));  in gf100_fifo_chan_ctor()
236 	nv_wo32(base, 0x54, 0x00000002);  in gf100_fifo_chan_ctor()
237 	nv_wo32(base, 0x84, 0x20400000);  in gf100_fifo_chan_ctor()
238 	nv_wo32(base, 0x94, 0x30000001);  in gf100_fifo_chan_ctor()
239 	nv_wo32(base, 0x9c, 0x00000100);  in gf100_fifo_chan_ctor()
240 	nv_wo32(base, 0xa4, 0x1f1f1f1f);  in gf100_fifo_chan_ctor()
241 	nv_wo32(base, 0xa8, 0x1f1f1f1f);  in gf100_fifo_chan_ctor()
242 	nv_wo32(base, 0xac, 0x0000001f);  in gf100_fifo_chan_ctor()
243 	nv_wo32(base, 0xb8, 0xf8000000);  in gf100_fifo_chan_ctor()
244 	nv_wo32(base, 0xf8, 0x10003080); /* 0x002310 */  in gf100_fifo_chan_ctor()
245 	nv_wo32(base, 0xfc, 0x10000010); /* 0x002350 */  in gf100_fifo_chan_ctor()
253 	struct nvkm_gpuobj *base = nv_gpuobj(object->parent);  in gf100_fifo_chan_init()  local
256 	u32 chid = chan->base.chid;  in gf100_fifo_chan_init()
259 	ret = nvkm_fifo_channel_init(&chan->base);  in gf100_fifo_chan_init()
263 	nv_wr32(priv, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12);  in gf100_fifo_chan_init()
280 	u32 chid = chan->base.chid;  in gf100_fifo_chan_fini()
290 	return nvkm_fifo_channel_fini(&chan->base, suspend);  in gf100_fifo_chan_fini()
320 	struct gf100_fifo_base *base;  in gf100_fifo_context_ctor()  local
325 				       NVOBJ_FLAG_HEAP, &base);  in gf100_fifo_context_ctor()
326 	*pobject = nv_object(base);  in gf100_fifo_context_ctor()
330 	ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0,  in gf100_fifo_context_ctor()
331 			      &base->pgd);  in gf100_fifo_context_ctor()
335 	nv_wo32(base, 0x0200, lower_32_bits(base->pgd->addr));  in gf100_fifo_context_ctor()
336 	nv_wo32(base, 0x0204, upper_32_bits(base->pgd->addr));  in gf100_fifo_context_ctor()
337 	nv_wo32(base, 0x0208, 0xffffffff);  in gf100_fifo_context_ctor()
338 	nv_wo32(base, 0x020c, 0x000000ff);  in gf100_fifo_context_ctor()
340 	ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd);  in gf100_fifo_context_ctor()
350 	struct gf100_fifo_base *base = (void *)object;  in gf100_fifo_context_dtor()  local
351 	nvkm_vm_ref(NULL, &base->vm, base->pgd);  in gf100_fifo_context_dtor()
352 	nvkm_gpuobj_ref(NULL, &base->pgd);  in gf100_fifo_context_dtor()
353 	nvkm_fifo_context_destroy(&base->base);  in gf100_fifo_context_dtor()
416 	spin_lock_irqsave(&priv->base.lock, flags);  in gf100_fifo_recover_work()
419 	spin_unlock_irqrestore(&priv->base.lock, flags);  in gf100_fifo_recover_work()
441 	u32 chid = chan->base.chid;  in gf100_fifo_recover()
450 	spin_lock_irqsave(&priv->base.lock, flags);  in gf100_fifo_recover()
452 	spin_unlock_irqrestore(&priv->base.lock, flags);  in gf100_fifo_recover()
464 	spin_lock_irqsave(&priv->base.lock, flags);  in gf100_fifo_swmthd()
465 	if (likely(chid >= priv->base.min && chid <= priv->base.max))  in gf100_fifo_swmthd()
466 		chan = (void *)priv->base.channel[chid];  in gf100_fifo_swmthd()
478 	spin_unlock_irqrestore(&priv->base.lock, flags);  in gf100_fifo_swmthd()
505 			if (!(chan = (void *)priv->base.channel[chid]))  in gf100_fifo_intr_sched_ctxsw()
703 			 nvkm_client_name_for_fifo_chid(&priv->base, chid),  in gf100_fifo_intr_pbdma()
740 			nvkm_fifo_uevent(&priv->base);  in gf100_fifo_intr_engine_unit()
892 	ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &priv->base.uevent);  in gf100_fifo_ctor()
913 	nvkm_fifo_destroy(&priv->base);  in gf100_fifo_dtor()
922 	ret = nvkm_fifo_init(&priv->base);  in gf100_fifo_init()