53 	void __iomem		*base;  member
69 	int gpio = gc->base + offset;  in pl061_gpio_request()
79 	int gpio = gc->base + offset;  in pl061_gpio_free()
95 	gpiodir = readb(chip->base + GPIODIR);  in pl061_direction_input()
97 	writeb(gpiodir, chip->base + GPIODIR);  in pl061_direction_input()
114 	writeb(!!value << offset, chip->base + (BIT(offset + 2)));  in pl061_direction_output()
115 	gpiodir = readb(chip->base + GPIODIR);  in pl061_direction_output()
117 	writeb(gpiodir, chip->base + GPIODIR);  in pl061_direction_output()
123 	writeb(!!value << offset, chip->base + (BIT(offset + 2)));  in pl061_direction_output()
133 	return !!readb(chip->base + (BIT(offset + 2)));  in pl061_get_value()
140 	writeb(!!value << offset, chip->base + (BIT(offset + 2)));  in pl061_set_value()
157 	gpioiev = readb(chip->base + GPIOIEV);  in pl061_irq_type()
158 	gpiois = readb(chip->base + GPIOIS);  in pl061_irq_type()
159 	gpioibe = readb(chip->base + GPIOIBE);  in pl061_irq_type()
181 	writeb(gpiois, chip->base + GPIOIS);  in pl061_irq_type()
182 	writeb(gpioibe, chip->base + GPIOIBE);  in pl061_irq_type()
183 	writeb(gpioiev, chip->base + GPIOIEV);  in pl061_irq_type()
200 	pending = readb(chip->base + GPIOMIS);  in pl061_irq_handler()
201 	writeb(pending, chip->base + GPIOIC);  in pl061_irq_handler()
219 	gpioie = readb(chip->base + GPIOIE) & ~mask;  in pl061_irq_mask()
220 	writeb(gpioie, chip->base + GPIOIE);  in pl061_irq_mask()
232 	gpioie = readb(chip->base + GPIOIE) | mask;  in pl061_irq_unmask()
233 	writeb(gpioie, chip->base + GPIOIE);  in pl061_irq_unmask()
256 		chip->gc.base = pdata->gpio_base;  in pl061_probe()
263 		chip->gc.base = -1;  in pl061_probe()
267 	chip->base = devm_ioremap_resource(dev, &adev->res);  in pl061_probe()
268 	if (IS_ERR(chip->base))  in pl061_probe()
269 		return PTR_ERR(chip->base);  in pl061_probe()
293 	writeb(0, chip->base + GPIOIE); /* disable irqs */  in pl061_probe()
334 	chip->csave_regs.gpio_dir = readb(chip->base + GPIODIR);  in pl061_suspend()
335 	chip->csave_regs.gpio_is = readb(chip->base + GPIOIS);  in pl061_suspend()
336 	chip->csave_regs.gpio_ibe = readb(chip->base + GPIOIBE);  in pl061_suspend()
337 	chip->csave_regs.gpio_iev = readb(chip->base + GPIOIEV);  in pl061_suspend()
338 	chip->csave_regs.gpio_ie = readb(chip->base + GPIOIE);  in pl061_suspend()
363 	writeb(chip->csave_regs.gpio_is, chip->base + GPIOIS);  in pl061_resume()
364 	writeb(chip->csave_regs.gpio_ibe, chip->base + GPIOIBE);  in pl061_resume()
365 	writeb(chip->csave_regs.gpio_iev, chip->base + GPIOIEV);  in pl061_resume()
366 	writeb(chip->csave_regs.gpio_ie, chip->base + GPIOIE);  in pl061_resume()